9-line IPAD™, EMI filter and ESD protection
Features
■ 9-line EMI low-pass filter and ESD protection
■ High efficiency in EMI filtering
■ Lead-free package
■ 400 µm pitch
■ Very low PCB space occupation: < 4 mm
Very thin package: 0.6 mm
■
■ High reliability offered by monolithic integration
■ Reduction of parasitic elements thanks to CSP
integration
Complies with the following standards
■ IEC61000-4-2 level 4 on external pins:
– 15 kV (air discharge)
– 8 kV (contact discharge)
■ IEC61000-4-2 level 2 on internal pins:
– 2 kV (air discharge)
– 2 kV (contact discharge)
■ MIL STD 883F - Method 3015.7 Class 3
2
EMIF09-SD01F3
Flip Chip
24 bumps
Figure 1. Pin layout (bump side)
5
3
4
12
A
B
C
D
E
Application
■ Secure digital memory card in mobile phones
and communication systems
Description
The EMIF09-SD01F3 is a highly integrated array
designed to suppress EMI/RFI noise for secure
digital memory cards. The EMIF09-SD01F3 is in
a Flip Chip package to offer space saving and
high RF performance.
This low-pass filter includes ESD protection
circuitry, which prevents damage to the protected
device when subjected to ESD surges up 15 kV.
This filter also has a low line capacitance to be
compatible with high data rate signals.
TM: IPAD is a trademark of STMicroelectronics.
April 2008 Rev 4 1/9
www.st.com
Characteristics EMIF09-SD01F3
1 Characteristics
Figure 2. Device configuration
VSD
DAT3_PU
DAT3_PU
CLK
CLK
CMD
CMD
DATA0
DATA0
DATA1
DATA1
DATA2
DATA2
DATA3
DATA3
CD
CD
WP
WP
WP+CD
WP+CD
DAT3_PD
DAT3_PD
R21
R21
R11
R11
R13
R13
R15
R15
R12
R12
R14
R14
R1
R1
R2
R2
R3
R3
R4
R4
R5
R5
R6
R6
R7
R7
R8
R8
R9
R9
VSD
SDCLK
SDCLK
SDCMD
SDCMD
SDDATA0
SDDATA0
SDDATA1
SDDATA1
SDDATA2
SDDATA2
SDDATA3
SDDATA3
SDCD
SDCD
SDWP
SDWP
SDWP+CD
SDWP+CD
GND_H
Table 1. Pin-signal attribution
GND_H
GND_C
GND_C
Pin Description Pin Description Pin Description Pin Description Pin Description
A1 DATA2 B1 CD C1 DAT3_PD D1 WP+CD E1 DATA1
A2 DATA3 B2 CMD C2 WP D2 CLK E2 DATA0
A3 GND_H B3 C3 DAT3_PU D3 GND_C E3 GND_C
A4 SDDATA2 B4 SDCD C4 SDWP D4 SDWP+CD E4 SDDATA1
A5 SDDATA3 B5 SDCMD C5 VSD D5 SDCLK E5 SDDATA0
Table 2. Absolute ratings (limiting values)
Symbol Parameter Value Unit
Internal pins (A1, B1, C1, D1, E1, A2, B2, C2, D2, E2, C3)
ESD discharge IEC 61000-4-2, air discharge
V
PP
ESD discharge IEC 61000-4-2, contact discharge
External pins (A4, B4, C4, D4, E4, A5, B5, C5, D5, E5)
ESD discharge IEC 61000-4-2, air discharge
ESD discharge IEC 61000-4-2, contact discharge
T
T
op
T
stg
Junction temperature 125 °C
j
Operating temperature range -30 to + 85 °C
Storage temperature range -55 to 150 °C
15
2
2
kV
8
GND bumps (GND_H and GND_C - A3, D3 and E3) must be connected to ground on the
printed circuit board for ESD testing and RF measurements.
2/9
EMIF09-SD01F3 Characteristics
Table 3. Electrical characteristics (T
Symbol Parameters
V
BR
I
RM
V
RM
V
R
I
PP
R
C
line
Symbol Test conditions Min Typ Max Unit
Breakdown voltage
Leakage current @ V
Stand-off voltage
Clamping voltage
CL
Dynamic impedance
d
Peak pulse current
Series resistance between input
I/O
and output
Input capacitance per line
RM
amb
= 25 °C)
VCLVBRV
VCLVBRV
I
I
I
I
PP
PP
I
I
R
R
I
I
RM
RM
RM
RM
I
I
VRMVBRV
VRMVBRV
RM
RM
I
I
R
R
I
I
PP
PP
V
V
CL
CL
V
I
BR
RM
IR = 1 mA 6 20 V
VRM = 5 V per line 50 200 nA
R1, R2,
R3, R4,
R5, R6,
Tolerance ± 20% 40 Ω
R7, R8, R9
R11, R12,
R13, R14
Tolerance ± 30% 50 kΩ
R15 Tolerance ± 30% 15 kΩ
R21 Tolerance ± 30% 470 kΩ
V
= 0 V, V
C
line
line
(under zero light conditions)
= 30 mV, F = 1 MHz
OSC
20 pF
3/9
Characteristics EMIF09-SD01F3
Figure 3. S21(dB) all lines attenuation
Figure 4. Analog cross talk measurement
measurement
dB
0.00
0.00
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
F (Hz)
-50.00
-50.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
data0 data1
data0 data1
data2 data3
data2 data3
dB
0.00
0.00
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
-50.00
-50.00
-60.00
-60.00
-70.00
-70.00
-80.00
-80.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
data0_data1
data0_data1
F (Hz)
Figure 5. Digital crosstalk measurement Figure 6. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input
(V
) and on one output (V
IN
OUT
)
Output Line 2
200mV/d
Input Line 1
1V/d
10ns/d
5Gs/s
Figure 7. ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input
(V
) and on one output (V
IN
)
OUT
V =20V/d
external
V
internal
100ns/d
Figure 8. Line capacitance versus applied
voltage
C (pF)
line
25
20
15
10
=10V/d
5
0
0246 8101214
V (V)
line
V =20V/d
external
V
internal
100ns/d
F = 1 MHz
V = 30 mV
OSC
T = 25°C
j
=10V/d
4/9
EMIF09-SD01F3 Application information
2 Application information
Figure 9. Aplac model
data0
Lbump Rbump
Rline
LbumpRbump
sddata0
MODEL = D1
MODEL = D3
Rbump
Lbump
Rgnd
Lgnd
Figure 10. Aplac model variables
Variables
aplacvar Rline 40
aplacvar C_d1 14.5p
aplacvar C_d2 6.5p
aplacvar C_d3 303p
aplacvar C_d4 14.5p
aplacvar Lbump 43pH
aplacvar Rbump 17m
aplacvar Cbump 150f
aplacvar Lgnd 150pH
aplacvar Rgnd 10m
aplacvar Rsub 5
Diode D1
BV=7
IBV=1m
CJO=C_d1
M=0.28
RS=1.13
VJ=0.6
TT=100n
Rsub
Rbump
Lbump
Rgnd
Lgnd
MODEL = D2
MODEL = D4
Rbump
Lbump
Rgnd
Lgnd
Diode D2
BV=7
IBV=1m
CJO=C_d2
M=0.28
RS=0.8
VJ=0.6
TT=100n
Diode D3
BV=7
IBV=1m
CJO=C_d3
M=0.28
RS=0.37
VJ=0.6
TT=100n
Diode D4
BV=7
IBV=1m
CJO=C_d4
M=0.28
RS=1.13
VJ=0.6
TT=100n
5/9
Ordering information scheme EMIF09-SD01F3
EMIF
3 Ordering information scheme
Figure 11. Ordering information scheme
yy - xx zz F3
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10 (pF)
or
2 letters = application
2 digits = version
Package
F = Flip Chip
3 = Lead-free, pitch = 400 µm, bump = 255 µm
4 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 12. Package dimensions
400 µm ± 40
400 µm ± 40
185 µm ± 10 µm
1.97 mm ± 30 µm
255 µm± 40
185 µm ± 10 µm
1.97 mm ± 30 µm
605 µm ± 55
6/9
EMIF09-SD01F3 Ordering information
Figure 13. Footprint Figure 14. Marking
Dot, ST logo
Copper pad Diameter:
220 µm recommended
260 µm maximum
Solder mask opening:
300 µm minimum
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
E
xyxwz
Solder stencil opening :
220 µm recommended
Figure 15. Flip Chip tape and reel specifications
Dot identifying Pin A1 location
4 ± 0.1
Ø 1.5 ± 0.1
w
1.75 ± 0.1 3.5 ± 0.1
8 ± 0.3
ST
2.11
0.69 ± 0.05
All dimensions in mm
yww
xxz
E
User direction of unreeling
Note: More information is available in the application note:
AN2348: “STMicroelectronics 400 micro-metre Flip Chip: Package description and
recommendation for use”
AN1751: EMI Filters: Recommendations and measurements
5 Ordering information
Table 4. Ordering information
yww
2.11
xxz
ST
E
2.11
4 ± 0.1
yww
xxz
ST
E
Order code Marking Package Weight Base qty Delivery mode
EMIF09-SD01F3 GZ Flip Chip 5.2 mg 5000 Tape and reel (7”)
7/9
Revision history EMIF09-SD01F3
6 Revision history
Table 5. Document revision history
Date Revision Changes
19-Oct-2005 1 Initial release.
09-Feb-2006 2 Tape cavity dimensions added in Figure 13. Other graphics improved.
22-Mar-2006 3
Reformatted to current standard. Typical and maximum values updated
for IRM in Electrical characteristics, page 3.
28-Apr-2008 4
Updated ECOPACK statement. Updated Figure 11, Figure 12 and
Figure 15. Reformatted to current standards.
8/9
EMIF09-SD01F3
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9/9
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