ST EMIF08-LCD04M16 User Manual

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8-line L-C IPAD™, EMI filter and ESD protection in Micro QFN

Features

■ High cut off frequency low-pass filter:

= 400 MHz at -6 dB

■ High efficiency in EMI filtering:

better than -35 dB from 900 MHz to 2 GHz

■ Very low PCB space consuming with plastic

micro-package 3.3 x 1.35 mm

■ Very thin package: 0.55 mm

■ High efficiency in ESD (IEC 61000-4-2 level 4)

■ High reliability offered by monolithic integration

■ High reducing of parasitic elements through

integration

■ ECOPACK

Complies with the following standards

2 compliant component

EMIF08-LCD04M16

Micro QFN

3.3 x 1.35 16L

Figure 1. Device configuration

Low-pass Filter

Input

0 0 0 0

Output

■ IEC 61000-4-2 level 4:

– 15 kV (air discharge) – 8 kV (contact discharge)

Applications

Where EMI filtering in ESD sensitive equipment is required:

■ L C D a n d c a m e r a f o r m o b i l e p h o n e s

■ Computers and printers

■ Communi catio n systems

■ MCU boards

GND GND GND

Description

The EMIF08-LCD04M16 is a 8-line inductorcapacitor (LC) EMI filter designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences requiring a large bandwidth.

This filter includes an ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up 15 kV contact discharge.

TM: IPAD is a trademark of STMicroelectronics.

November 2009 Doc ID 15673 Rev 2 1/10

www.st.com

Electrical characteristics EMIF08-LCD04M16

1 Electrical characteristics

Table 1. Absolute maximum ratings (T

Symbol Parameter Value Unit

amb

= 25 °C)

ESD discharge IEC 61000-4-2, contact discharge ± 15 kV

Operating temperature range -40 to 85 °C

Maximum junction temperature 125 °C

Storage temperature range -55 to 150 °C

stg

Figure 2. Electrical characteristics (definitions)

Symbol Parameter

V = Breakdown voltage

I = Leakage current @ V

RM RM

V = Stand-off voltage

V = Clamping voltage

R = Dynamic impedance

I = Peak pulse current

I = Breakdown current

T = Voltage temperature coefficient

V = Forward voltage drop

Table 2. Electrical characteristics (T

amb

= 25 °C)

VCLVBRV

Symbol Test conditions Min. Typ. Max. Unit

BRIR

= 1 mA 6 - - V

VRM = 3 V per line - - 100 nA

L Inductance - 12 - nH

VR = 3 V DC, F = 1 MHz, V

line

osc

R Parasitic resistance of the inductance 9 12.5 20 Ω

50 Ω source and 50 Ω load termination at -6 dB - 400 - MHz

2/10 Doc ID 15673 Rev 2

= 30 mV 17 18 19 pF

EMIF08-LCD04M16 Electrical characteristics

Figure 3. S21 attenuation measurements Figure 4. Analog crosstalk measurements

-5

-10

-15

-20

-25

-30

-35

I2-O2 #1

-40

-45

-50

-55

-60

-65

-70

Figure 5. ESD response to IEC 61000-4-2

I3 O3 #1

O4 #1

O5 #1

O6 #1

O7 #1

O8 #1

100k 1M 10M 100M 1G

(+15 kV air discharge)

5V/Div

OUT

F/Hz

Figure 6. ESD response to IEC 61000-4-2

(-15 kV air discharge)

5V/Div

OUT

Figure 7. Line capacitance versus applied voltage

C(pF)

012345

2V/Div

V (V)

2V/Div

Doc ID 15673 Rev 2 3/10

Ordering information scheme EMIF08-LCD04M16

2 Ordering information scheme

Figure 8. Ordering information scheme

EMIF yy - xxxzz Mxx

EMI Filter

Number of lines

Information xxx = application zz = version

Package Mxx = Micro QFN - xx leads

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EMIF08-LCD04M16 Package information

3 Package information

● Epoxy meets UL94, V0

● Lead-free package

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com ECOPACK

Table 3. Micro QFN 3.3x1.35 16L dimensions

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

Dimensions

INDEX AREA

(D/2 x E/2)

TOP VIEW

Ref.

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.45 0.50 0.55 0.018 0.020 0.022

SIDE VIEW

A1 0.00 0.02 0.05 0.00 0.0008 0.002

b 0.15 0.20 0.25 0.006 0.008 0.010

D - 3.30 - - 0.13 -

BOTTOMVIEW

INDEX AREA

(D/2 x E/2)

PIN # 1 ID

EXPOSED PAD

D2 2.65 2.80 2.90 0.104 0.110 0.114

E - 1.35 - - 0.053 -

E2 0.25 0.40 0.50 0.010 0.016 0.020

e - 0.40 - - 0.016 -

k 0.20 - - 0.008 - -

L 0.15 0.25 0.35 0.006 0.010 0.014

Figure 9. Footprint Figure 10. Marking

0.40

0.45

0.40

2.80

3.00

0.20

0.85

1.75

Y P

Dot: Pin 1 XX: Marking WW: Assembly week Y: Assembly year P: Assembly plant

Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should

this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose.

Doc ID 15673 Rev 2 5/10

Recommendation on PCB assembly EMIF08-LCD04M16

4 Recommendation on PCB assembly

4.1 Stencil opening design

1. General recommendation on stencil opening design

a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).

Figure 11. Stencil opening dimensions

b) General design rule

Stencil thickness (T) = 75 ~ 125 µm

Aspect Ratio

Aspect Area

-----

1.5≥=

LW×

---------------------------2T L W+()

0.66≥=

2. Reference design

a) Stencil opening thickness: 100 µm

b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%.

c) Stencil opening for leads: Opening to footprint ratio is 90%.

Figure 12. Recommended stencil window position

4µm 4µm

14 µm

T=100 µm

450 µm

422 µm

192 µm

200 µm

400 µm

µm

60 µm

Footprint

Stencil window

Footprint

2800 µm

400 µm

280 µm

2000 µm

6/10 Doc ID 15673 Rev 2

EMIF08-LCD04M16 Recommendation on PCB assembly

4.2 Solder paste

1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.

2. “No clean” solder paste is recommended.

3. Offers a high tack force to resist component movement during high speed.

4. Solder paste with fine particles: powder particle size is 20-45 µm.

4.3 Placement

1. Manual positioning is not recommended.

2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering.

3. Standard tolerance of ± 0.05 mm is recommended.

4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.

5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.

6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.

4.4 PCB design preference

1. To control the solder paste amount, the closed via is recommended instead of open vias.

2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.

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Recommendation on PCB assembly EMIF08-LCD04M16

4.5 Reflow profile

Figure 13. ST ECOPACK® recommended soldering reflow profile for PCB mounting

Temperature (°C)

260°C max

255°C

220°C

180°C

125 °C

3°C/s max

2°C/s recommended

6°C/s max

3°C/s max

012345 67

Time (min)

90 to 150 sec

10-30 sec

90 sec max

Note: Minimize air convection currents in the reflow oven to avoid component movement.

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EMIF08-LCD04M16 Ordering information

5 Ordering information

Table 4. Ordering information

Order code Marking Package Weight Base qty Delivery mode

EMIF08-LCD04M16 JA

(1)

1. The marking can be rotated by 90° to differentiate assembly location

µQFN 6.74 mg 3000 Tape and reel

6 Revision history

Table 5. Document revision history

Date Revision Changes

20-May-2009 1 Initial release.

10-Nov-2009 2 Updated Features on page 1. Added Figure 2 on page 2.

Doc ID 15673 Rev 2 9/10

EMIF08-LCD04M16

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