EMIF07-LCD02F3
7-line IPAD™, EMI filter and ESD protection for LCD and cameras
Features
■ EMI symmetrical (I/O) low-pass filter
■ High efficiency in EMI filtering
■ Lead-free package
■ Very low PCB space occupation:
1.94 mm x 1.54 mm
■ Very thin package: 0.65 mm
■ High efficiency in ESD suppression
■ High reliability offered by monolithic integration
■ High reduction of parasitic elements through
integration and wafer level packaging
Complies with the following standards
■ IEC 61000-4-2 level 4 on inputs and outputs:
– 15 kV (air discharge)
– 8 kV (contact discharge)
■ MIL STD 883G - Method 3015-7 Class 3
Figure 1. Pin layout (bump side)
5
O1
O3
O4
O6
Flip Chip
(18 bumps)
4
GND
O2
GND
GND
O5
GND
O7
3
I1 I2
I4
I6
12
A
B
I3
I5
C
I7
D
Applications
Where EMI filtering in ESD sensitive equipment is
required:
■ LCD for mobile phones
■ Computers and printers
■ Communication systems
■ MCU boards
Figure 2. Device configuration
Low-pass Filter
Input
GND GND GND
Output
Ri/o = 70
Ω
Cline = 30 pF
Description
The EMIF07-LCD02F3 is a 7-line highly
integrated device designed to suppress EMI/RFI
noise in all systems subjected to electromagnetic
interference. The EMIF07 Flip Chip package
means the package size is equal to the die size.
This filter includes ESD protection circuitry, which
prevents damage to the protected device when
subjected to ESD surges up 15 kV.
February 2010 Doc ID 11639 Rev 3 1/8
TM: IPAD is a trademark of STMicroelectronics.
www.st.com
8
Characteristics EMIF07-LCD02F3
1 Characteristics
Table 1. Absolute maximum ratings (T
Symbol Parameter and test conditions Value Unit
amb
= 25 °C)
T
T
T
Table 2. Electrical characteristics (T
Maximum junction temperature 125 °C
j
Operating temperature range -40 to +85 °C
op
Storage temperature range -55 to 150 °C
stg
= 25 °C)
amb
Symbol Parameters
V
BR
I
RM
V
RM
V
CL
I
PP
R
I/O
C
line
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Peak pulse current
Series resistance between input and output
Input capacitance per line
V
V
CL
I
I
F
V
V
RM
BR
F
I
RM
I
R
I
PP
Symbol Test conditions Min Typ Max Unit
V
BR
I
RM
R
C
line
IR = 1 mA 6 8 10 V
VRM = 3 V 50 200 nA
Tolerance ± 20% 70 Ω
2
Vline = 0 V, V
= 30 mV, F =1 MHz 30 pF
OSC
V
2/8 Doc ID 11639 Rev 3
EMIF07-LCD02F3 Characteristics
t
Figure 3. Attenuation measurement and
Aplac simulation
dB
0.00
-10.00
-20.00
-30.00
-40.00
-50.00
100.0k 1.0M 10.0M 100.0M 1.0G
Line 1 Line 2
Line 3 Line 4
Line 5 Line 6
Line 7
F (Hz)
Figure 5. Voltages when IEC 61000-4-2
(+15 kV air discharge) applied to
input pin
10 V/div
Input
Figure 4. Analog cross talk measurement
dB
0.00
0.00
0.00
-10.00
-10.00
-10.00
-20.00
-20.00
-20.00
-30.00
-30.00
-30.00
-40.00
-40.00
-40.00
-50.00
-50.00
-50.00
-60.00
-60.00
-60.00
-70.00
-70.00
-70.00
-80.00
-80.00
-80.00
-90.00
-90.00
-90.00
-100.00
-100.00
-100.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
Xtalk 1/2
Xtalk 1/2
Xtalk 1/2
F (Hz)
Figure 6. Voltages when IEC 61000-4-2
(-15 kV air discharge) applied to
input pin
10 V/div
Input
10 V/div
10 V/div
Outpu
100 ns/div
Figure 7. Line capacitance versus applied voltage
C (pF)
line
30
25
20
15
10
5
0
0123456
V (V)
line
Output
100 ns/div
Doc ID 11639 Rev 3 3/8
Application information EMIF07-LCD02F3
MODEL = D2
Rline
MODEL = D1
Lbump Rbump LbumpRbump
bulk
I1
O1
MODEL = D3
Rbump
Lbump
Cbump
Rgnd
Lgnd
bulk
Rbump
Lbump
Cbump
Rgnd
Lgnd
Rbump
Lbump
Cbump
Rgnd
Lgnd
Rbump
Lbump
Cbump
Rgnd
Lgnd
2 Application information
Figure 8. Aplac model
Figure 9. Aplac parameters
aplacvar Rline 70
aplacvar C_d1 15p
aplacvar C_d2 15p
aplacvar C_d3 600p
aplacvar Ls 950pH
aplacvar Rs 150m
aplacvar Lbump 50pH
aplacvar Rbump 20m
aplacvar Cbump 150f
aplacvar Lgnd 50pH
aplacvar Rgnd 100m
aplacvar Rsub 10m
Diode D1
BV=7
IBV=1m
CJO=C_d1
M=0.28
RS=0.1
VJ=0.6
TT=100n
Diode D2
BV=7
IBV=1m
CJO=C_d2
M=0.28
RS=0.1
VJ=0.6
TT=100n
Diode D3
BV=7
IBV=1m
CJO=C_d3
M=0.28
RS=0.01
VJ=0.6
TT=100n
4/8 Doc ID 11639 Rev 3
EMIF07-LCD02F3 Ordering information scheme
3 Ordering information scheme
Figure 10. Ordering information scheme
EMIF yy - xxx zz F3
EMI filter
Number of lines
Information
x = resistance value (ohm)
z = capacitance value / 10 (pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
3 = Lead-free, pitch = 400 µm, bump = 255 µm
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
Figure 11. Package dimensions
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
400 µm ± 40
400 µm ± 40
170 µm
1.94 mm ± 30µm
255 µm± 40
1.54 mm ± 30 µm
170 µm
605 µm ± 55
Doc ID 11639 Rev 3 5/8
Ordering information EMIF07-LCD02F3
Figure 12. Footprint Figure 13. Marking
Copper pad Diameter:
220 µm recommended
260 µm maximum
Solder mask opening:
300 µm minimum
Solder stencil opening:
220 µm recommended
Dot, ST logo
ECOPACK status
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location
0.20 ± 0.02
2.08
8.0 ± 0.3
2.0 ± 0.05
yww
ST
xxz
4.0 ± 0.1
ST
yww
xxz
xyxwz
Ø 1.55 ± 0.1
ST
yww
xxz
w
1.75 ± 0.1
3.5 ± 0.1
1.71
0.69 ± 0.05
All dimensions in mm
User direction of unreeling
Note: More information is available in the application notes:
AN2348: “STMicroelectronics 400 micro-metre Flip Chip : Package description and
recommendation for use”
AN1751: “EMI filters: Recommendations and measurements”
5 Ordering information
Table 3. Ordering information
Order code Marking Package Weight Base qty Delivery mode
EMIF07-LCD02F3 GX Flip Chip 3.9 mg 5000 Tape and reel 7”
4.0 ± 0.1
6/8 Doc ID 11639 Rev 3
EMIF07-LCD02F3 Revision history
6 Revision history
Table 4. Document revision history
Date Revision Changes
12-Sep-2005 1 First issue.
28-Apr-2008 2
19-Feb-2010 3 Updated die size in Figure 11.
Updated ECOPACK statement. Updated Figure 10, Figure 11 and
Figure 14. Reformatted to current standards.
Doc ID 11639 Rev 3 7/8
EMIF07-LCD02F3
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8/8 Doc ID 11639 Rev 3
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