ST EMIF07-LCD02F3 User Manual

EMIF07-LCD02F3

7-line IPAD™, EMI filter and ESD protection for LCD and cameras

Features

■ EMI symmetrical (I/O) low-pass filter

■ High efficiency in EMI filtering

■ Lead-free package

■ Very low PCB space occupation:

1.94 mm x 1.54 mm

■ Very thin package: 0.65 mm

■ High efficiency in ESD suppression

■ High reliability offered by monolithic integration

■ High reduction of parasitic elements through

integration and wafer level packaging

Complies with the following standards

■ IEC 61000-4-2 level 4 on inputs and outputs:

– 15 kV (air discharge)
– 8 kV (contact discharge)

■ MIL STD 883G - Method 3015-7 Class 3

Figure 1. Pin layout (bump side)

5

O1

O3

O4

O6

Flip Chip

(18 bumps)

4

GND

O2

GND

GND

O5

GND

O7

3

I1 I2

I4

I6

12

A

B

I3

I5

C

I7

D

Applications

Where EMI filtering in ESD sensitive equipment is
required:

■ LCD for mobile phones

■ Computers and printers

■ Communication systems

■ MCU boards

Figure 2. Device configuration

Low-pass Filter

Input

GND GND GND

Output

Ri/o = 70

Ω

Cline = 30 pF

Description

The EMIF07-LCD02F3 is a 7-line highly
integrated device designed to suppress EMI/RFI
noise in all systems subjected to electromagnetic
interference. The EMIF07 Flip Chip package
means the package size is equal to the die size.

This filter includes ESD protection circuitry, which
prevents damage to the protected device when
subjected to ESD surges up 15 kV.

February 2010 Doc ID 11639 Rev 3 1/8

TM: IPAD is a trademark of STMicroelectronics.

www.st.com

8

Characteristics EMIF07-LCD02F3

1 Characteristics

Table 1. Absolute maximum ratings (T

Symbol Parameter and test conditions Value Unit

amb

= 25 °C)

T

T

T

Table 2. Electrical characteristics (T

Maximum junction temperature 125 °C

j

Operating temperature range -40 to +85 °C

op

Storage temperature range -55 to 150 °C

stg

= 25 °C)

amb

Symbol Parameters

V

BR

I

RM

V

RM

V

CL

I

PP

R

I/O

C

line

Breakdown voltage

Leakage current @ V

RM

Stand-off voltage

Clamping voltage

Peak pulse current

Series resistance between input and output

Input capacitance per line

V

V

CL

I

I

F

V

V

RM

BR

F

I

RM

I

R

I

PP

Symbol Test conditions Min Typ Max Unit

V

BR

I

RM

R

C

line

IR = 1 mA 6 8 10 V

VRM = 3 V 50 200 nA

Tolerance ± 20% 70 Ω

2

Vline = 0 V, V

= 30 mV, F =1 MHz 30 pF

OSC

V

2/8 Doc ID 11639 Rev 3

EMIF07-LCD02F3 Characteristics

t

Figure 3. Attenuation measurement and

Aplac simulation

dB

0.00

-10.00

-20.00

-30.00

-40.00

-50.00

100.0k 1.0M 10.0M 100.0M 1.0G

Line 1 Line 2
Line 3 Line 4
Line 5 Line 6
Line 7

F (Hz)

Figure 5. Voltages when IEC 61000-4-2

(+15 kV air discharge) applied to
input pin

10 V/div

Input

Figure 4. Analog cross talk measurement

dB

0.00

0.00

0.00

-10.00

-10.00

-10.00

-20.00

-20.00

-20.00

-30.00

-30.00

-30.00

-40.00

-40.00

-40.00

-50.00

-50.00

-50.00

-60.00

-60.00

-60.00

-70.00

-70.00

-70.00

-80.00

-80.00

-80.00

-90.00

-90.00

-90.00

-100.00

-100.00

-100.00

100.0k 1.0M 10.0M 100.0M 1.0G

100.0k 1.0M 10.0M 100.0M 1.0G

100.0k 1.0M 10.0M 100.0M 1.0G

Xtalk 1/2

Xtalk 1/2

Xtalk 1/2

F (Hz)

Figure 6. Voltages when IEC 61000-4-2

(-15 kV air discharge) applied to
input pin

10 V/div

Input

10 V/div

10 V/div

Outpu

100 ns/div

Figure 7. Line capacitance versus applied voltage

C (pF)

line

30

25

20

15

10

5

0

0123456

V (V)

line

Output

100 ns/div

Doc ID 11639 Rev 3 3/8