6-line IPAD™, low capacitance EMI filter and ESD protection
Features
■ High efficiency EMI filtering
(-40 dB @ 900 MHz)
■ Low line capacitance suitable for high speed
data bus
■ Low serial resistance for camera impedance
adaptation
■ Lead-free package
■ Optimized PCB space occupation:
2.92 mm x 1.29 mm
■ Very thin package: 0.65 mm
■ High efficiency in ESD suppression on inputs
pins (IEC 61000-4-2 level 4)
■ High reliability offered by monolithic integration
■ High reduction of parasitic elements through
integration and wafer level packaging
EMIF06-VID01F2
®
Flip Chip
(15 bumps)
Figure 1. Pin layout (bump side)
987 654 321
I6
I5
Gnd Gnd Gnd
O6
O5
Figure 2. Device configuration
O4
I3
I4
O3
I2
O2
O1
A
I1
B
C
Complies with the following standards:
■ IEC 61000-4-2 Level 4 on input pins
– 15 kV (air discharge)
– 8 kV (contact discharge)
■ MIL STD 883E - Method 3015-6 Class 3
Application
Where EMI filtering in ESD sensitive equipment is
required:
■ LCD and camera for mobile phones
■ Computers and printers
■ Communication sy stems
■ MCU board
Input
R = 100
C = 16pF typ. @ 3V
R
Output
Ω
LINE
Description
The EMIF06-VID01F2 is a 6-line highly integrated
array designed to suppress EMI / RFI noise in all
systems subjected to electromagnetic
interference.
The EMIF06-VID01F2 Flip Chip packaging means
the package size is equal to the die size.
Additionally, this filter includes ESD protection
circuitry which prevents damage to the protected
device when subjected to ESD surges up to
15 kV.
April 2008 Rev 2 1/7
www.st.com
7
Characteristics EMIF06-VID01F2
I
1 Characteristics
Table 1. Absolute ratings (limiting values)
Symbol Parameter and test conditions Value Unit
Maximum junction temperature 125 °C
T
j
T
T
Table 2. Electrical characteristics (T
Symbol Parameter
Operating temperature range - 40 to + 85 °C
op
Storage temperature range - 55 to + 150 °C
stg
= 25 °C)
amb
V
I
RM
V
Breakdown voltage
BR
Leakage current @ V
Stand-off voltage
RM
RM
IR
IRM
VRMVBR
IRM
IR
V
V
BRVRM
R Series resistance between input and output
C
Input capacitance per line
line
Symbol Test conditions Min. Typ. Max. Unit
V
I
IR = 1 mA 6 8 10 V
BR
VRM = 3 V per line 500 nA
RM
R I = 10 mA 80 100 120 Ω
C
VR = 3 V dc, 1 MHz V
line
= 30 mV 16 19 pF
OSC
2/7
EMIF06-VID01F2 Characteristics
Figure 3. S21 (dB) attenuation measurement Figure 4. Analog crosstalk measurement
0
dB
-10
-20
-30
-40
-50
-60
100k 1M 10M 100M 1G
f/Hz
Figure 5. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input
(V
Input
10V/d
Output
10V/d
) and on one output (V
in
out
)
0
dB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100k 1M 10M 100M 1G
f/Hz
Figure 6. ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input
(Vin) and on one output (V
Input
10V/d
Output
10V/d
out
)
200ns/d
200ns/d
Figure 7. Junction capacitance versus reverse voltage applied (typical values)
C
(pF)
LINE
28
28
26
26
24
24
22
22
20
20
18
18
16
16
14
14
12
12
10
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
V
(V)
LINE
3/7
Ordering information scheme EMIF06-VID01F2
5
2 Ordering information scheme
Figure 8. Ordering information scheme
EMIF yy - xxx zz Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
x = 2: Lead-free, pitch = 500 µm, bump = 315 µm
3 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 9. Flip Chip package dimensions
500 µm ± 50
250 µm ± 50
01µm ± 50
2.92 mm ± 50 µm
315 µm ± 50
650 µm ± 65
210 µm
435 µm ± 50
1.29 mm ± 50 µm
210 µm
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EMIF06-VID01F2 Package information
Figure 10. Footprint recommendations Figure 11. Marking
Dot, ST logo
xx = marking
Copper pad diameter:
250 µm recommended, 300 µm max
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 300 µm copper pad diameter
z = manufacturing location
yww = date code
(y = year
ww = week)
x
y
E
z
wxw
Figure 12. Flip Chip tape and reel specification
Dot identifying Pin A1 location
4 ± 0.1
1.52
8 ± 0.3
0.73 ± 0.05
All dimensions in mm
yww
xxx
ST
E
User direction of unreeling
yww
xxx
ST
E
Note: More packing information is available in the application note
AN1235: “Flip Chip: Package description and recommendations for use”
AN1751: “EMI Filters: Recommendations and measurements”
3.0
4 ± 0.1
Ø 1.5 ± 0.1
yww
xxx
1.75 ± 0.1 3.5 ± 0.1
ST
E
5/7
Ordering information EMIF06-VID01F2
4 Ordering information
Table 3. Ordering information
Order code Marking Package Weight Base qty Delivery mode
EMIF06-VID01F2 GR Flip Chip 5.4 mg 5000 Tape and reel 7”
5 Revision history
Table 4. Document revision history
Date Revision Changes
15-Feb-2005 1 First issue.
28-Apr-2008 2
Added ECOPACK statement. Updated Figure 9, Figure 11, and
Figure 12. Reformatted to current standards.
6/7
EMIF06-VID01F2
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