IPAD™
6 line low capacitance EMI filter and ESD protection
Main application
Where EMI filtering in ESD sensitive equipment is
required:
■ LCD and camera for mobile phones
■ Computers and printers
■ Co mmunic ation s ystem s
■ MCU board
EMIF06-VID01C2
®
Description
The EMIF06-VID01C2 is a 6 line highly integrated
device designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic
interference. The Flip-Chip packaging means the
package size is equal to the die size.
This filter includes ESD protection circuitry, which
prevents damage to the application when it is
subjected to ESD surges up to 15 kV.
Benefits
■ High efficiency EMI filtering (-40db @ 900MHz)
■ Low line capacitance suitable for high speed
data bus
■ Low serial resistance for camera impedance
adaptation
■ Optimized PCB space consuming:
2.92mm x 1.29mm
■ Very thin package: 0.69 mm
■ High efficiency in ESD suppression on inputs
pins (IEC61000-4-2 level 4)
■ High reliability offered by monolithic integration
■ High reducing of parasitic elements through
integration and wafer level packaging
■ Lead free package
Lead free coated Flip-Chip
(15 Bumps)
Order code
Part Number Marking
EMIF06-VID01C2 GR
Pin identities (bump side)
987 654 321
I6
I5
I4
I3
Gnd Gnd Gnd
O6
O5
O4
O3
Circuit configuration
R
Input
I2
O2
I1
O1
Output
A
B
C
Complies with the following standards:
IEC 61000-4-2
level 4 input pins 15 kV (air discharge)
8 kV (contact discharge
MIL STD 883E - Method 3015-6 Class 3
June 2006 Rev 2 1/7
R = 100
C = 16pF typ. @ 3V
Ω
LINE
www.st.com
7
Characteristics EMIF06-VID01C2
1 Characteristics
Table 1. Absolute Ratings (limiting values)
Symbol Parameter and test conditions Value Unit
Maximum junction temperature 125 °C
T
j
T
T
Table 2. Electrical Characteristics (T
Symbol Parameter
Operating temperature range - 40 to + 85 °C
op
Storage temperature range - 55 to + 150 °C
stg
= 25° C)
amb
I
V
I
V
C
Breakdown voltage
BR
Leakage current @ V
RM
Stand-off voltage
RM
Series resistance between
R
Input and Output
Input capacitance per line
line
RM
IR
IRM
VRMVBR
IRM
IR
V
BRVRM
V
Symbol Test conditions Min. Typ. Max. Unit
V
BR
I
RM
IR = 1 mA 6 8 10 V
VRM = 3 V per line 500 nA
R I = 10 mA 80 100 120 Ω
C
line
VR = 3 V DC 1 MHz V
= 30 mV 16 19 pF
OSC
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EMIF06-VID01C2 Characteristics
Figure 1. S21 (db) attenuation measurement Figure 2. Analog crosstalk measurement
0
dB
-10
-20
-30
-40
-50
-60
100k 1M 10M 100M 1G
f/Hz
Figure 3. ESD response to IEC 61000-4-2
(+15kV air discharge) on one input
(Vin) and on one output (Vout)
Input
10V/d
Output
10V/d
0
dB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
100k 1M 10M 100M 1G
f/Hz
Figure 4. ESD response to IEC 61000-4-2
(-15kV air discharge) on one input
(Vin) and on one output (Vout)
Input
10V/d
Output
10V/d
200ns/d
Figure 5. Junction capacitance versus
reverse voltage applied (typical
values)
C (pF)
LINE
28
28
26
26
24
24
22
22
20
20
18
18
16
16
14
14
12
12
10
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
V (V)
LINE
200ns/d
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Ordering information scheme EMIF06-VID01C2
5
2 Ordering information scheme
EMIF yy - xxx zz Cx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
C = Coated Flip-Chip
x = 1: 500µm, Bump = 315µm
= 2: Leadfree Pitch = 500µm, Bump = 315µm
3 Package information
Figure 6. Flip-Chip Dimensions
500µm ± 50
250µm ± 50
01µm ± 50
2.92mm ± 50µm
315µm ± 50
690µm ± 65
435µm ± 50
1.29mm ± 50µm
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EMIF06-VID01C2 Package information
Figure 7. Footprint recommendations Figure 8. Marking
Dot, ST logo
xx = marking
Copper pad Diameter :
250µm recommended , 300µm max
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 300µm copper pad diameter
z = manufacturing location
yww = date code
(y = year
ww = week)
x
y
E
z
wxw
Figure 9. Flip-Chip Tape and reel specifications
Dot identifying Pin A1 location
4 +/- 0.1
Ø 1.5 +/- 0.1
1.75 +/- 0.1 3.5 +/- 0.1
8 +/- 0.3
0.78 +/- 0.05
All dimensions in mm
yww
xxx
ST
E
User direction of unreeling
yww
xxx
ST
E
4 +/- 0.1
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Note: More packing informations are available in the application note
AN1235: “Flip-Chip: Package description and recommendations for use”
AN1751: “EMI Filters: Recommendations and measurements”
yww
xxx
ST
E
5/7
Ordering information EMIF06-VID01C2
4 Ordering information
Ordering code Marking Package Weight Base qty Delivery mode
EMIF06-VID01C2 GR Flip-Chip 5.9 mg 5000 Tape and reel 7”
5 Revision history
Date Revision Changes
12-Aug-2005 1 First issue.
01-Jun-2006 2
Reformatted to current standards. Modified marking illustration to
remove dimensions. Depth dimension changed in Figure 9.
6/7
EMIF06-VID01C2
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