ST EMIF06-SD03F3 User Manual

6-line IPAD™, EMI filter and ESD protection for SD card

Features

■ ESD protection (IEC standard)

■ EMI Filtering

■ Level translator

■ Signal conditionning

■ Integrated power supply with:

– Thermal shutdown (TSD) – Under voltage lockout (UVLO) – Short-circuit current limitation (I – Power on/off feature with Enable pin

SC

EMIF06-SD03F3

Flip Chip

)

(24 bumps)

Benefits

■ EMI Low-pass-filter and ESD protection (up to

15 kV on external pins)

■ Integrated pull up resistors prevent bus floating

■ 50 MHz clock frequency compatible with

C

< 40 pF

line

■ Lead-free package in 400 µm pitch

■ Low power consumption

■ Very low PCB space consumption

■ High reliability offered by monolithic integration

■ Reduction of parasitic elements thanks to CSP

integration

Complies with the following standards:

■ IEC 61000-4-2, Level 4: External pins

– 15 kV (air discharge) – 8 kV (contact discharge)

■ HBM IEC 61340-3-1: All pins

– 2 kV (air discharge) – 2 kV (contact discharge)

Figure 1. Pin configuration (bump side)

5

3

4

12

A

B

C

D

E

Applications

■ Removable memory cards in mobile phones,

communication systems, and portable applications

■ Memory cards compliant with: SD (standard

and high speed), MiniSD, µSD and MMC/Trans-flash standards

Description

The EMIF06-SD03F3 is a highly integrated device, based on IPAD technology, combining the

TM: IPAD is a trademark of STMicroelectronics.

February 2010 Doc ID 15194 Rev 2 1/23

5 functions described under Features.

www.st.com

23

Contents EMIF06-SD03F3

1 Functional description

A SIDE (Host-CPU) pin list:

V

, Enable, Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK -f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h,

ccA

Dat3.h, V

B SIDE (SD-Card) pin list:

bat

WP, CD, V

Table 1. Pin definition

, CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B

ccB

Pin name Bump Type Side Description

V

ccA

V

ccB

V

bat

B3 Power input A

B4 Power output B

A4 Power input A

GND C4 Ground - Ground

GND C3 Ground - Ground

Enable C2 Input A Internal power supply enable

CMD.dir A2 Input A Command direction

CMD.h D2 IO A A side command

CLK.h C1 Input A Clock input

CLK-f E2 Output A Clock feedback

Dat0.dir A3 Input A Data direction

Dat0.h D1 IO A Data host

Dat123.dir E3 Input A Data direction

Dat1.h E1 IO A Data host

Dat2.h A1 IO A Data host

Dat3.h B1 IO A Data host

WP E4 Input to CPU A Write protect

CD D3 Input to CPU A Card detect

CMD-B D4 IO B Command direction

CLK-B C5 Output B Clock output

Dat0-B D5 IO B Data SD

Dat1-B E5 IO B Data SD

Dat2-B A5 IO B Data SD

Dat3-B B5 IO B Data SD

Power supply (1.8v)

Power supply (internally generated, 2.9 V)

Battery power supply

Note: In Ta bl e 5 , 6, 7, and 10, collective names are used for groups of pins. The names used are:

*.dir = CMD.dir, Dat0.dir, Dat123.dir *.h = CMD.h, CLK.h, Dat0.h, Dat1.h, Dat2.h, Dat3.h *-B = CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B V

= All A side input pins

iA

V

= All B side input pins.

iB

Doc ID 15194 Rev 2 3/23

Functional description EMIF06-SD03F3

Table 2. Function table

Command signals A side signals direction B side signal direction

Enable CMD. dir Dat0.dir Dat123.dir CMD.h CLK.h CLK-f Dat0.h

Dat1.h

Dat2.h

Dat3.h

CMD-B CLK-B Dat0-B

Dat1-B

Dat2-B

Dat3-B

H H X X IN IN OUT X X OUT OUT X X

H L X X OUT IN OUT X X IN OUT X X

H X H X X IN OUT IN X X OUT OUT X

H X L X X IN OUT OUT X X OUT IN X

HX X HXINOUTXINXOUTXOUT

H X X L X IN OUT X OUT X OUT X IN

L X X X X X Z X X L* Z L* L*

Note: 1 When A side signals direction is INPUT, SD-CARD is WRITTEN by CPU-Host (i.e B side

signals direction is OUTPUT) When A side signals direction is OUTPUT, SD-CARD is READ by CPU-Host (i.e B side signals direction is INPUT)

2 For B side signals when Enable = L:

* Defined by internal pull-down (see Figure 3 for pins CMD.B and data bus Dat[0…3].B)

Figure 2. Configuration

CPU

Feedback Clk

CMD

CMD Dir

Dir0

Dir1-3

WP, CD

VccA 1.8 V

ESD 2 kV

Vbat

IPAD

Low drop out

voltage regulator

Clk Clk

CMD CMD

Data 0 - 3 Data 0 - 3

ESD (15 kV)

and EMI

VccB

Mini

SD

4/23 Doc ID 15194 Rev 2

EMIF06-SD03F3 Functional description

Figure 3. Block diagram

Enable

EnableEnable

CMD.dir

CMD.h

CLK.h

CLK-f

Dat0.dir

Dat0.h

Dat123.dir

Dat1.h

Dat2.h

2KV

2KV2KV

2KV

2 kV

500KW

500KW500KW

500KW

500 k Ω

2KV

2 kV

2KV

2 kV

2KV

2 kV

2KV

2 kV

2KV

2 kV

2KV

2 kV

2KV

2 kV

2KV

2 kV

2KV

2 kV

VCCA

VCCAVCCA

VCCA

V

ccA

R

V

ccA

EN

V

VCCA

VCCAVCCA

VCCA

ccA

2KV

2KV2KV

2KV

2 kV

V

VCCB

VCCBVCCB

VCCB

ccB

R9

R10

R11

V

REF

VREF

REF

V

VCCB

VCCBVCCBVCCB

VCCB

ccB

V

VCCB

VCCBVCCBVCCB

VCCB

ccB

V

VCCB

VCCBVCCBVCCB

VCCB

ccB

V

ccB

VCCB

VCCBVCCBVCCB

VCCB

15KW

15 k Ω

70KW

70 k Ω

70KW

70 kR12

A

OTP

UVLO

Ω70 k

Ω

LDO

R,C

Filters

FiltersFilters

EMI

V

bat

15KV

15KV15KV15KV15KV

15KV

2 kV

VCCB

VCCBVCCB

VCCB

V

ccB

V

15KV

15 kV

15KV

ccB

CMD-B

15KV

15 kV

15KV

CLK-B

15KV

15 kV

Dat0-B

15KV

15 kV

15KV

Dat1-B

-

15KV

15 kV

15KV

Dat2-B

15KV

15 kV

15KV

Dat3.h

R14

V

VCCA

VCCAVCCA

VCCA

ccA

2KV

2kV

100KW

100k

Level-Shifters

Level-ShiftersLevel-Shifters

Level-Shifters

Level-shifters-

Ω

470KW

470KW470KW

470KW

470kR7 Ω

V

VCCA

VCCAVCCAVCCA

VCCA

ccA

100KW

100 kR13 Ω

15KV

15KV15KV

15KV

15 kV

Dat3CD-B

WP

15KV

15kV

EMIF06--

EMIF06

EMIF06-

SD02F3

SD03F3

GND

15KV

15 kV

Doc ID 15194 Rev 2 5/23

Characteristics EMIF06-SD03F3

2 Characteristics

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

A SIDE (Host-CPU) All pins: HBM IEC61340-3-1

, Enable, Dat123.dir, CMD.dir, CMD.h, CLK.h,

V

ccA

CLK -f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h, V

bat

Air discharge

Contact discharge

2 2

ESD

B SIDE (SD-Card) External pins : IEC 61000-4-2, level 4

, CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B,

V

ccB

Dat3-B, WP, CD

Maximum junction temperature 150 °C

Thermal resistance from junction to ambient

(1)

Board: Epoxy FR4, copper thickness = 40 µm, 4 layers

Maximum power dissipation: P

= (T

dmax

Storage temperature range -55 to +150 °C

stg

V

, V

bat

- T

jmax

, Enable -0.3 to 5.5V

ccB

aopmax

)/ Rth (j-a)

R

th (j-a)

T

P

jmax

dmax

T

CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B -0.3 to V

Voltage

V

ccA

Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK -f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h, WP, CD

1. V

is an internally generated power supply, no external voltage should be applied on this pin other than a current clamp.

ccB

The thermal resistance depends on printed circuit board layout. To dissipate the heat efficiently away from Flip Chip bumps, it is better to make copper planes the largest possible as well as considering thermal vias usage.

Air discharge

Contact discharge

-0.3 to 3.3

-0.3 to V

15

8

64

1W

+ 0.3

ccB

+0.3

ccA

kV

°C/

W

V

6/23 Doc ID 15194 Rev 2

EMIF06-SD03F3 Characteristics

Table 4. Recommended operating conditions

Symbol Parameter Conditions Min. Typ. Max. Unit

V

ccA

V

bat

I

out

C

bat

(1)

C

out

(2)

ESR

T

aop

T

jop

P

dop

Enable Enable input voltage 0 - V

Power supply 1.62 1.8 1.92 V

Battery power supply 3.1 - 5 V

V

output current 0.10 100 200 mA

ccB

External battery capacitance

External output capacitance

Equivalent series resistance for C

out

Ceramic capacitor - 2.20 - µF

= -40 °C to +85 °C, V

T

a

Multi-layer ceramic capacitor type like: C20RX7R1C225K

= 0 V to 3.3 V

bias

1.4

(-35%)

2.20

3.0

(+35%)

F = 1 Hz to 10 MHz Multi-layer ceramic capacitor type like:

-3200mΩ

C2012X7R1C225KT

Ambient operating temperature -30 25 85 °C

Juntion operating temperature -30 25 125 °C

Maximum power dissipation

P

= (T

- T

dop

jop

aop

)/R

th (j-a)

--625mW

ccA

External pins (without

CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B 0 - V

ccB

WP and CD)

Internal pins (except Enable, with

WP, CD, Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK-f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h

0-V

ccA

WP and CD)

1. C

= 2.2 µF is minimum allowable capacitance value to guarantee LDO stability

out

2. Values for ESR include the V minimized in PCB design.

ccB

resistance path and C

- C

out

- GND resistance path. These resistance paths need to be

out

µF

V

Doc ID 15194 Rev 2 7/23