ST EMIF06-SD02F3 User Manual

EMIF06-SD02F3

6-line IPAD™, EMI filter and ESD protection for SD card

Features

■ESD protection (IEC standard)

■EMI Filtering

■Level translator

■Signal conditionning

■Integrated power supply with:

–Thermal shutdown (TSD)

–Under voltage lockout (UVLO)

–Short-circuit current limitation (ISC)

–Power on/off feature with Enable pin.

Benefits

■EMI Low-pass-filter and ESD protection (up to 15 kV on external pins)

■Integrated pull up resistors to prevent bus floating

■50 MHz clock frequency compatible with Cline< 40 pF

■Lead-free package in 400 µm pitch

■Low power consumption

■Very low PCB space consumption

■High reliability offered by monolithic integration

■Reduction of parasitic elements thanks to CSP integration

Complies with the following standards

■IEC 61000-4-2, Level 4 (external pins)

–15 kV (air discharge)

–8 kV (contact discharge)

■HBM IEC 61340-3-1 (all pins)

–2 kV (air discharge)

–2 kV (contact discharge)

Flip Chip 24 bumps

Figure 1. Pin configuration (bump side)

5 4 3 2 1

A

B

C

D

E

Applications

■Removable memory cards in mobile phones, communication systems, and portable applications

■Memory cards compliant with: SD (standard and high speed), MiniSD, µSD and MMC/Trans-flash standards

Description

The EMIF06-SD02F3 is a highly integrated device, based on IPAD technology, combining 5 functions. The Flip-Chip packaging means the package size is equal to the die size.

TM: IPAD is a trademark of STMicroelectronics.

February 2010

Doc ID 17109 Rev 4

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www.st.com

Contents	EMIF06-SD02F3

Contents

1	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 3
2	Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
3	Passive integration and low pass filter . . . . . . . . . . . . . . . . . . . . . . . . . .		8
4	Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	4.1	Test circuit from host to SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	4.2	Test circuit from SD to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	4.3	Measurement of tskew (SD to host) from rising edge CLK.h . . . . . . . . . . .	12
	4.4	Measurement of tskew.f (read mode) from rising edge CLK.h . . . . . . . . . .	12
5	Low drop out voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13

5.1 Line regulation and transient line regulation . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 Load regulation and transient load regulation . . . . . . . . . . . . . . . . . . . . . 17 5.3 Dropout definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6	Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
7	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
8	Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
9	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

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EMIF06-SD02F3	Functional description

1 Functional description

A SIDE (Host-CPU) pin list:

VccA, Enable, Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK -f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h, Vbat

B SIDE (SD-Card) pin list:

WP, CD, VccB, CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B

	Table 1.	Pin definition
	Pin Name	Bump	Type	Side	Description
	VccA	B3	Power input	A	Power supply (1.8v)
	VccB	B4	Power output	B	Power supply (internally generated, 2.9 V)
	Vbat	A4	Power input	A	Battery power supply
	GND	C4	Ground	-	Ground
	GND	C3	Ground	-	Ground
	Enable	C2	Input	A	Internal power supply enable
	CMD.dir	A2	Input	A	Command direction
	CMD.h	D2	IO	A	A side command
	CLK.h	C1	Input	A	Clock input
	CLK-f	E2	Output	A	Clock feedback
	Dat0.dir	A3	Input	A	Data direction
	Dat0.h	D1	IO	A	Data host
	Dat123.dir	E3	Input	A	Data direction
	Dat1.h	E1	IO	A	Data host
	Dat2.h	A1	IO	A	Data host
	Dat3.h	B1	IO	A	Data host
	WP	E4	Input to CPU	A	Write protect
	CD	D3	Input to CPU	A	Card detect
	CMD-B	D4	IO	B	Command direction
	CLK-B	C5	Output	B	Clock output
	Dat0-B	D5	IO	B	Data SD
	Dat1-B	E5	IO	B	Data SD
	Dat2-B	A5	IO	B	Data SD
	Dat3-B	B5	IO	B	Data SD
Note:	In Table 5, 6, 7, and 10, collective names are used for groups of pins. The names used are:
	*.dir = CMD.dir, Dat0.dir, Dat123.dir
	*.h = CMD.h, CLK.h, Dat0.h, Dat1.h, Dat2.h, Dat3.h

*-B = CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B ViA = All A side input pins

ViB = All B side input pins.

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Functional description

EMIF06-SD02F3

Table 2.

Function table

Command signals

A side signals direction

B side signal direction

Dat1.h

Dat1-B

Enable

CMD. dir

Dat0.dir

Dat123.dir

CMD.h

CLK.h

CLK-f

Dat0.h

Dat2.h

CMD-B

CLK-B

Dat0-B

Dat2-B

Dat3.h

Dat3-B

H

H

X

X

IN

IN

OUT

X

X

OUT

OUT

X

X

H

L

X

X

OUT

IN

OUT

X

X

IN

OUT

X

X

H

X

H

X

X

IN

OUT

IN

X

X

OUT

OUT

X

H

X

L

X

X

IN

OUT

OUT

X

X

OUT

IN

X

H

X

X

H

X

IN

OUT

X

IN

X

OUT

X

OUT

H

X

X

L

X

IN

OUT

X

OUT

X

OUT

X

IN

L

X

X

X

X

X

Z

X

X

L*

Z

L*

L*

Note: 1 When A side signals direction is INPUT, SD-CARD is WRITTEN by CPU-Host (i.e B side signals direction is OUTPUT)

When A side signals direction is OUTPUT, SD-CARD is READ by CPU-Host (i.e B side signals direction is INPUT)

2For B side signals when Enable = L:

*Defined by internal pull-down (cf Block Diagram for pins CMD.B and data bus Dat[0…3].B)

Figure 2.	Configuration
		VccA 1.8 V	Vbat
				IPAD
	Feedback Clk				VccB
	CMD			Low drop out
			voltage regulator
	CMD Dir
	CPU	ESD				Mini
		2 kV	Clk		Clk	SD
	Dir0		CMD		CMD
				ESD (15 kV)
	Dir1-3		Data 0 - 3		Data 0 - 3
				and EMI
	WP, CD

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EMIF06-SD02F3	Functional description

Figure 3. Block diagram

VccA			Vbat

		VCCA
		ccA						215KVkV
					VREF	LDO
					V
		2KVk
Enable					A
	2KVk							VCCB
								ccB
						R,C		VccB
500Kk ΩW		REN			OTP			15KVk
		VCCAccA	VCCBccB		REF
					UVLO
CMD.dir				CCBccB
	2KVk			V
				R9	15KkWΩ
CMD.h	2KVk							CMD-B
								15KVk
CLK.h	2KVk							CLK-B
								15KVk
CLK-f
	2KVk
						EMI
Dat0.dir	2KVk			VCCBccB		Filters
				R10	70KkWΩ
Dat0.h	2KVk							Dat0-B
								15KVk
Dat123.dir	2KVk			VCCBccB
				R11
					70KkWΩ
Dat1.h	2KVk							Dat1-B
				V				15KVk
				VCCBccB
				R12	70KkWΩ
Dat2.h	2KVk							Dat2-B
								15KVk
Dat3.h	2kVKV							Dat3-B
				R7	470kKΩW			15KVk
VCCAccA		Level-shS ifters				VCCAccA
R14	100kKΩW					R13	100KkWΩ
WP								CD
	15kVKV						15KVk
		EMIF06EMIF06--SD02F3SD02F3
				GND

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Characteristics	EMIF06-SD02F3

2	Characteristics
Table 3.	Absolute maximum ratings
Symbol	Parameter		Value	Unit
	A SIDE (Host-CPU)
	All pins: HBM IEC61340-3-1
	VccA, Enable, Dat123.dir, CMD.dir, CMD.h, CLK.h,	Air discharge	2
	CLK -f, Dat0.dir, Dat0.h, Dat1.h, Dat2.h, Dat3.h, Vbat	Contact discharge	2
ESD				kV
	B SIDE (SD-Card)
	External pins : IEC 61000-4-2, level 4
	VccB, CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B,	Air discharge	15
	Dat3-B, WP, CD	Contact discharge	8
Tjmax	Maximum junction temperature		150	°C
(1)	Thermal resistance from junction to ambient		64	°C/W
Rth (j-a)	Board: epoxy FR4, copper thickness = 40 µm, 4 layers
Pdmax	Maximum power dissipation:		1	W
	Pdmax= (Tjmax - Taopmax)/ Rth (j-a)
Tstg	Storage temperature range		-55 to +150	°C
	Vbat, VccB, Enable		-0.3 to 5.5
	CMD-B, CLK-B, Dat0-B, Dat1-B, Dat2-B, Dat3-B		-0.3 to VccB + 0.3
Voltage	VccA		-0.3 to 3.3	V
	Dat123.dir, CMD.dir, CMD.h, CLK.h, CLK -f, Dat0.dir,		-0.3 to VccA+0.3
	Dat0.h, Dat1.h, Dat2.h, Dat3.h, WP, CD

1.VccB is an internally generated power supply, no external voltage should be applied on this pin other than a current clamp. The thermal resistance depends on printed circuit board layout. To dissipate the heat efficiently away from Flip Chip bumps, it is better to make copper planes the largest possible as well as considering thermal vias usage.

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EMIF06-SD02F3						Characteristics
Table 4.	Recommended operating conditions
Symbol		Parameter	Conditions	Min.	Typ.		Max.	Unit
VccA		Power supply		1.62	1.8		1.92	V
Vbat		Battery power supply		3.1			5	V
Iout		VccB output current		0.10	100		200	mA
Cbat		External battery	Ceramic capacitor		2.20			µF
		capacitance
(1)		External output	Ta = -40 °C to +85 °C, Vbias = 0 V to 3.3 V	1.4			3.0
			Multi-layer ceramic capacitor type like:
Cout		capacitance		(-35%)	2.20		(+35%)	µF
			C20RX7R1C225K
ESR(2)		Equivalent series	F = 1 Hz to 10 MHz					mΩ
			Multi-layer ceramic capacitor type like:	0	3		200
		resistance for Cout
			C20RX7R1C225K
Taop		Ambient operating		-30	25		85	°C
		temperature
Tjop		Juntion operating		-30	25		125	°C
		temperature
Pdop		Maximum power	Pdop = (Tjop - Taop)/Rth (j-a)				625	mW
		dissipation
Enable		Enable input voltage		0			VccA	V
External		CMD-B, CLK-B, Dat0-
pins (without		B, Dat1-B,		0			VccB	V
WP and CD)		Dat2-B, Dat3-B
		WP, CD, Dat123.dir,
Internal pins		CMD.dir, CMD.h,
(except		CLK.h,		0			VccA	V
Enable, with		CLK-f, Dat0.dir,
WP and CD)		Dat0.h, Dat1.h,
		Dat2.h, Dat3.h

1.Cout = 2.2 µF is minimum allowable capacitance value to guarantee LDO stability

2.Values for ESR include the VccB - Cout resistance path and Cout - GND resistance path. These resistance paths need to be minimized in PCB design.

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