ST EMIF06-10006F2 User Manual

IPAD™

Main product characteristics

EMIF06-10006F2

6 line EMI filter and ESD protection

Where EMI filtering in ESD sensitive equipment is required:
Computers, printers and MCU Boards
Description
The EMIF06-10006F2 is a highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF06 Flip-Chip packaging means the package size is equal to the die size.
This filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up 15 kV. This device includes 6 EMIF filters.
Benefits
EMI symmetrical (I/O) low-pass filter
High efficiency in EMI filtering
Lead free package
Very low PCB space consumption
2.92 mm x 1.29 mm
Very thin package: 0.65 mm
High efficiency in ESD suppression
(IEC 61000-4-2 level 4)
High reliability offered by monolithic integration
High reduction of parasitic elements through
integration and wafer level packaging
®
Flip-Chip
(15 Bumps)
Order code
Part Number Marking
EMIF06-10006F2 FT

Figure 1. Pin configuration (bump side)

987 654 321
I6
I5
Gnd Gnd Gnd
O5
O4
O6
Complies with the following standards:
IEC 61000-4-2 level 4:
15 kV (air discharge)
8 kV (contact discharge)
MIL STD 883E - Method 3015-6 Class 3: 30 kV
I3
I4
O3
I2
O2
I1
O1
A
B
C
TM: IPAD is a trademeark of STMicroelectronics
November 2006 Rev 4 1/9
www.st.com
9
Characteristics EMIF06-10006F2

1 Characteristics

Figure 2. Basic cell configuration

Input 1
100 Ω
Output 1 Input 4
30 pF 30 pF
100 Ω
Output 4
30 pF 30 pF
Input 2 Output 2
Input 3 Output 3

Table 1. Absolute Ratings (limiting values)

100 Ω
30 pF 30 pF
100 Ω
30 pF 30 pF
Input 5
Input 6
100 Ω
Output 5
30 pF 30 pF
100 Ω
Output 6
30 pF 30 pF
Symbol Parameter and test conditions Value Unit
P
P
T
T
Table 2. Electrical Characteristics (T
Symbol Parameter
V
I
RM
V
V
R
I
PP
R
C
DC power per resistance 0.1 W
R
Total DC power per package 0.6 W
T
Maximum junction temperature 125 ° C
T
j
Operating temperature range - 40 to + 85 ° C
op
Storage temperature range 125 ° C
stg
= 25 °C)
amb
I
Breakdown voltage
BR
I
F
Leakage current @ VRM
Stand-off voltage
RM
Clamping voltage
CL
Dynamic impedance
d
VCL
VRMVBR
IRM IR
Peak pulse current
Series resistance between Input and output
I/O
Capacitance per line
line
IPP
VF
Symbol Test conditions Min. Typ. Max. Unit
V
V
I
RM
R
C
IR = 1 mA 5.5 7 9 V
BR
VRM = 3.3 V per line 500 nA
I = 10 mA 80 100 120 Ω
I/O
VR = 2.5 V, F = 1 MHz, 30 mV (on filter cells) 50 60 70 pF
line
2/9
EMIF06-10006F2 Characteristics
Figure 3. S21 (db) attenuation measurements

Figure 4. Analog crosstalk measurements

and Aplac simulation
Aplac 7.62 User: ST Microelectronics
0.00
0.00
dB
dB
-12.50
-12.50
-25.00
-25.00
-37.50
-37.50
-50.00
-50.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
Measurement
Measurement
Measurement
Simulation
Simulation
Simulation
f/Hz
f/Hz
00
-25
-50
-75
-100
100k
Aplac 7.62 User: ST Microelectronics
dBdB
1M
i3_o2.s2p
f/Hz
10M 100M 1G
Figure 5. Digital crosstalk measurements Figure 6. ESD response to IEC 61000-4-2
(+15 kV air discharge) on one imput (V
) and one output (V
in
out
)
Figure 7. ESD response to IEC 61000-4-2
(–15 kV air discharge) on one imput (V
) and one output (V
in
out
)
Figure 8. Line capacitance versus applied
voltage for filter
C(pF)
100
90
80
70
60
50
40
30
20
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V (V)
R
3/9
V
osc
F=1MHz
=30mV
Tj=25°C
RMS
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