Datasheet EMIF06-10006C2 Datasheet (ST)

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Main product characteristics

EMIF06-10006C2

6 line EMI filter and ESD protection

Where EMI filtering in ESD sensitive equipment is required:

■ Mobile phones and communication systems

■ Computers, printers and MCU Boards

Description

The EMIF06-10006C2 is a highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF06 Flip-Chip packaging means the package size is equal to the die size.

This filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up 15 kV. This device includes 6 EMIF filters.

Benefits

■ EMI symmetrical (I/O) low-pass filter

■ High efficiency in EMI filtering

■ Lead free coated package

■ Very low PCB space consumption

2.92 mm x 1.29 mm

■ Very thin package: 0.695 mm

■ High efficiency in ESD suppression

(IEC 61000-4-2 level 4)

■ High reliability offered by monolithic integration

■ High reduction of parasitic elements through

integration and wafer level packaging

Flip-Chip

(15 Bumps)

Order Code

Part Number Marking

EMIF06-10006C2 FT

Figure 1. Pin Configuration (bump side)

987 654 321

Gnd Gnd Gnd

Complies with the following standards:

IEC 61000-4-2 level 4:

15 kV (air discharge)

8 kV (contact discharge)

MIL STD 883G - Method 3015-7 Class 3: 30 kV

TM: IPAD is a trademeark of STMicroelectronics

November 2006 Rev 1 1/9

www.st.com

Characteristics EMIF06-10006C2

1 Characteristics

Figure 2. Basic cell configuration

Input 1

100 Ω

Output 1 Input 4

30 pF 30 pF

100 Ω

Output 4

30 pF 30 pF

Input 2 Output 2

Input 3 Output 3

Table 1. Absolute Ratings (limiting values)

100 Ω

30 pF 30 pF

100 Ω

30 pF 30 pF

Input 5

Input 6

100 Ω

Output 5

30 pF 30 pF

100 Ω

Output 6

30 pF 30 pF

Symbol Parameter and test conditions Value Unit

Table 2. Electrical Characteristics (T

Symbol Parameter

DC power per resistance 0.1 W

Total DC power per package 0.6 W

Maximum junction temperature 125 ° C

Operating temperature range - 40 to + 85 ° C

Storage temperature range 125 ° C

stg

= 25 °C)

amb

Breakdown voltage

Leakage current @ VRM

Stand-off voltage

Clamping voltage

Dynamic impedance

VCL

VRMVBR

IRM IR

Peak pulse current

Series resistance between Input and output

I/O

Capacitance per line

line

IPP

Symbol Test conditions Min. Typ. Max. Unit

IR = 1 mA 5.5 7 9 V

VRM = 3.3 V per line 500 nA

I = 10 mA 80 100 120 Ω

I/O

VR = 2.5 V, F = 1 MHz, 30 mV (on filter cells) 50 60 70 pF

line

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EMIF06-10006C2 Characteristics

Figure 3. S21 (db) attenuation measurements

Figure 4. Analog crosstalk measurements

and Aplac simulation

Aplac 7.62 User: ST Microelectronics

0.00

-12.50

-25.00

-37.50

-50.00

100.0k 1.0M 10.0M 100.0M 1.0G

Measurement

Simulation

f/Hz

-25

-50

-75

-100

100k

Aplac 7.62 User: ST Microelectronics

dBdB

i3_o2.s2p

f/Hz

10M 100M 1G

Figure 5. Digital crosstalk measurements Figure 6. ESD response to IEC 61000-4-2

(+15 kV air discharge) on one imput (V

) and one output (V

out

)

Figure 7. ESD response to IEC 61000-4-2

(–15 kV air discharge) on one imput (V

) and one output (V

out

)

Figure 8. Line capacitance versus applied

voltage for filter

C(pF)

100

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

V (V)

3/9

osc

F=1MHz

=30mV

Tj=25°C

RMS

Characteristics EMIF06-10006C2

Figure 9. Aplac model

Ii*

Cbump

Rsub

Oi * = Output of each filter cell

Ii* = Input of each filter cell

Rs=100LbumpRbump

Cz=41pF@0V

EMIF06-10006C2 model Ground return for each GND bump

Lbump Rbump

sub

Figure 10. Figure 10: Aplac parameters

aplacvar RS

aplacvar Cz

aplacvar Lbump

aplacvar Rbump

aplacvar Cbump

aplacvar Rsub

aplacvar Rgnd

aplacvar Lgnd

aplacvar Cgnd

Rsub

Oi*

Cbump

100

41 pF

50 pH

20 m

1.2 pF

100 m

100 pH

0.15 pF

CgndCgndCgnd

sub

Rsub

Rbump

Lbump

Lgnd

Rgnd

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EMIF06-10006C2 Ordering Information Scheme

2 Ordering Information Scheme

EMIF yy - xxx zz Cx

EMI Filter

Number of lines

Information

x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version

Package

C = Coated Flip-Chip x = 2: Lead free Pitch = 500 µm, Bump = 315 µm

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Package information EMIF06-10006C2

3 Package information

Figure 11. Flip-Chip Package dimensions

315 µm ± 50

500 µm ± 50

250 µm ± 50

501 µm ± 50

2.92 mm ± 50 µm

435 µm ± 50

1.29 mm ± 50 µm

Figure 12. Foot print recommendations Figure 13. Marking

Dot, ST logo

Copper pad Diameter:

250 µm recommended , 300 µm max

Solder stencil opening: 330 µm

Solder mask opening recommendation:

340 µm min for 300 µm copper pad diameter

xx = marking z = manufacturing location yww = datecode

(y = year

ww = week)

x y

695 µm ± 75

wxw

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EMIF06-10006C2 Package information

Figure 14. Flip-Chip Tape and reel specification

Dot identifying Pin A1 location

8 +/- 0.3

yww

xxz

4 +/- 0.1

yww

xxz

Ø 1.5 +/- 0.1

yww

xxz

1.75 +/- 0.1 3.5 +/- 0.1

0.73 +/- 0.05

All dimensions in mm

User direction of unreeling

4 +/- 0.1

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Note: Note: More packing information is available in the application notes:

AN1235: “Flip-Chip: Package description and recommendations for use”

AN1751: "EMI Filters: Recommendations and measurements"

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Ordering Information EMIF06-10006C2

4 Ordering Information

Ordering code Marking Package Weight Base qty Delivery mode

EMIF06-10006C2 FT Flip-Chip 5.9 mg 5000 Tape and reel 7”

5 Revision History

Date Revision Description of Changes

17-Nov-2006 1 First issue

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EMIF06-10006C2

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Datasheet EMIF06-10006C2 Datasheet (ST)

Specifications and Main Features

Frequently Asked Questions

User Manual

IPAD™

EMIF06-10006C2

6 line EMI filter and ESD protection

Figure 1. Pin Configuration (bump side)

1 Characteristics

Figure 2. Basic cell configuration

Table 1. Absolute Ratings (limiting values)

Figure 4. Analog crosstalk measurements

Figure 9. Aplac model

Figure 10. Figure 10: Aplac parameters

2 Ordering Information Scheme

3 Package information

Figure 11. Flip-Chip Package dimensions

Figure 14. Flip-Chip Tape and reel specification

4 Ordering Information

5 Revision History