ST EMIF04-1502M8 User Manual

low capacitance EMI filter and ESD protection in micro QFN package
Features
EMI asymmetrical (I/O) low-pass filter
High efficiency in EMI filtering
Very low PCB space consumption:
Very thin package: 0.6 mm max
High efficiency in ESD suppression on input
pins (IEC 61000-4-2 level 4)
High reliability offered by monolithic integration
High reducing of parasitic elements through
integration and wafer level packaging
Lead-free package
EMIF04-1502M8
4-line IPAD™
8
7
6
5
Micro QFN 1.7 mm x 1.5 mm
GND
GND
(bottom view)

Figure 1. Pin configuration (top view)

1 Input Output 8
1
2
3
4
Complies with following standards:
IEC 61000-4-2 level 4 input pins
– 15 kV (air discharge) – 8 kV (contact discharge)
MIL STD 883G - Method 3015-7 Class 3A
(all pins)
Applications
Where EMI filtering in ESD sensitive equipment is required:
LCD and camera for mobile phones
Computers and printers
Communication systems
MCU boards
Description
The EMIF04-1502M8 is a 4-line, highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference.
This filter includes an ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 15 kV on the input pins.
2 Input
3 Input
4 Input

Figure 2. Basic cell configuration

Input
Typical line capacitance = 14 pF @ 2.5 V
TM: IPAD is a trademark of STMicroelectronics
170 Ω
Output 7
Output 6
Output 5
Output
January 2009 Rev 6 1/10
www.st.com
Characteristics EMIF04-1502M8

1 Characteristics

Table 1. Absolute ratings (limiting values at T
= 25° C unless otherwise specified)
amb
Symbol Parameter Value Unit
ESD IEC 61000-4-2 air discharge on input pins
V
ESD IEC 61000-4-2 contact discharge on input pins
PP
ESD IEC 61000-4-2 contact discharge on output pins
Junction temperature 125 °C
T
j
T
T
Table 2. Electrical characteristics (T
Operating temperature range -40 to + 85 °C
op
Storage temperature range -55 to +150 °C
stg
Symbol Parameter
V
I
V
V
R
I
R
C
BR
RM
RM
CL
PP
I/O
line
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic resistance
d
Peak pulse current
Series resistance between Input & Output
Input capacitance per line
amb
= 25° C)
I
I
F
V
BR
V
V
RM
CL
I
RM
I
R
I
PP
15
8 4
V
F
V
kV
Symbol Test conditions Min. Typ. Max. Unit
V
BR
I
RM
R
I/O
C
line
IR = 1 mA 6 8 10 V
VRM = 3 V per line 100 nA
Tolerance ± 10% 153 170 187 Ω
V
= 2.5 V dc, V
LINE
= 30 mV, F = 1 MHz 12 14 16.5 pF
OSC
Figure 3. S21 attenuation measurement Figure 4. Analog cross talk measurements
dB
0.00
-15.00
-30.00
F (Hz)
-45.00
100.0k 1.0M 10.0M 100.0M 1.0G
dB
0.00
0.00
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
-50.00
-50.00
-60.00
-60.00
-70.00
-70.00
-80.00
-80.00
-90.00
-90.00
-100.00
-100.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
F (Hz)
2/10
EMIF04-1502M8 Ordering information scheme
Figure 5. ESD response to IEC 61000-4-2
V
in
V
out
(+15 kV air discharge) on one input (V
) and on one output (V
in
)
out
C1 = 10 V/d
C2 = 5 V/d
100 ns/d
Figure 6. ESD response to IEC 61000-4-2
(- 15 kV air discharge) on one input (Vin) and on one output (V
V
in
V
out

Figure 7. Line capacitance versus reverse voltage applied (typical value)

C
(pF)
LINE
24 22 20 18 16 14 12 10
8 6 4 2 0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
(V)
LINE
)
out
C1 = 10 V/d
C2 = 5 V/d
100 ns/d

2 Ordering information scheme

Figure 8. Ordering information scheme

EMI Filter
Number of lines
Information
x = resistance value (Ohms) z = capacitance value / 10(pF)
Package
Mx = Micro QFN x leads
3/10
EMIF yy - xxx z Mx
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