low capacitance EMI filter and ESD protection in micro QFN package
Features
■ EMI asymmetrical (I/O) low-pass filter
■ High efficiency in EMI filtering
■ Very low PCB space consumption:
1.7 mm x 1.5 mm
■ Very thin package: 0.6 mm max
■ High efficiency in ESD suppression on input
pins (IEC 61000-4-2 level 4)
■ High reliability offered by monolithic integration
■ High reducing of parasitic elements through
integration and wafer level packaging
■ Lead-free package
EMIF04-1502M8
4-line IPAD™
8
7
6
5
Micro QFN 1.7 mm x 1.5 mm
GND
GND
(bottom view)
Figure 1. Pin configuration (top view)
1 Input Output 8
1
2
3
4
Complies with following standards:
■ IEC 61000-4-2 level 4 input pins
– 15 kV (air discharge)
– 8 kV (contact discharge)
■ MIL STD 883G - Method 3015-7 Class 3A
(all pins)
Applications
Where EMI filtering in ESD sensitive equipment is
required:
■ LCD and camera for mobile phones
■ Computers and printers
■ Communication systems
■ MCU boards
Description
The EMIF04-1502M8 is a 4-line, highly integrated
device designed to suppress EMI/RFI noise in all
systems exposed to electromagnetic interference.
This filter includes an ESD protection circuitry,
which prevents damage to the application when
subjected to ESD surges up to 15 kV on the input
pins.
2 Input
3 Input
4 Input
Figure 2. Basic cell configuration
Input
Typical line capacitance = 14 pF @ 2.5 V
TM: IPAD is a trademark of STMicroelectronics
170 Ω
Output 7
Output 6
Output 5
Output
January 2009 Rev 6 1/10
www.st.com
Characteristics EMIF04-1502M8
1 Characteristics
Table 1. Absolute ratings (limiting values at T
= 25° C unless otherwise specified)
amb
Symbol Parameter Value Unit
ESD IEC 61000-4-2 air discharge on input pins
V
ESD IEC 61000-4-2 contact discharge on input pins
PP
ESD IEC 61000-4-2 contact discharge on output pins
Junction temperature 125 °C
T
j
T
T
Table 2. Electrical characteristics (T
Operating temperature range -40 to + 85 °C
op
Storage temperature range -55 to +150 °C
stg
Symbol Parameter
V
I
V
V
R
I
R
C
BR
RM
RM
CL
PP
I/O
line
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic resistance
d
Peak pulse current
Series resistance between Input & Output
Input capacitance per line
amb
= 25° C)
I
I
F
V
BR
V
V
RM
CL
I
RM
I
R
I
PP
15
8
4
V
F
V
kV
Symbol Test conditions Min. Typ. Max. Unit
V
BR
I
RM
R
I/O
C
line
IR = 1 mA 6 8 10 V
VRM = 3 V per line 100 nA
Tolerance ± 10% 153 170 187 Ω
V
= 2.5 V dc, V
LINE
= 30 mV, F = 1 MHz 12 14 16.5 pF
OSC
Figure 3. S21 attenuation measurement Figure 4. Analog cross talk measurements
dB
0.00
-15.00
-30.00
F (Hz)
-45.00
100.0k 1.0M 10.0M 100.0M 1.0G
dB
0.00
0.00
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
-50.00
-50.00
-60.00
-60.00
-70.00
-70.00
-80.00
-80.00
-90.00
-90.00
-100.00
-100.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
F (Hz)
2/10
EMIF04-1502M8 Ordering information scheme
Figure 5. ESD response to IEC 61000-4-2
V
in
V
out
(+15 kV air discharge) on one input
(V
) and on one output (V
in
)
out
C1 = 10 V/d
C2 = 5 V/d
100 ns/d
Figure 6. ESD response to IEC 61000-4-2
(- 15 kV air discharge) on one input
(Vin) and on one output (V
V
in
V
out
Figure 7. Line capacitance versus reverse voltage applied (typical value)
C
(pF)
LINE
24
22
20
18
16
14
12
10
8
6
4
2
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
(V)
LINE
)
out
C1 = 10 V/d
C2 = 5 V/d
100 ns/d
2 Ordering information scheme
Figure 8. Ordering information scheme
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
Package
Mx = Micro QFN x leads
3/10
EMIF yy - xxx z Mx
Package information EMIF04-1502M8
3 Package information
● Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
Table 3. QFN 1.7 x 1.5 package dimensions
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
D
N
E
Ref
Millimeters inches
MIN TYP MAX MIN TYP MAX
A 0.50 0.55 0.60 0.20 0.22 0.24
2
1
A
A1
E2
D2
1
2
L
k
N
b
A1 0.00 0.02 0.05 0.00 0.01 0.02
b 0.15 0.18 0.25 0.06 0.07 0.10
D 1.70 0.67
D2 0.9 1.00 1.10 0.35 0.39 0.43
E 1.50 0.59
E2 0.30 0.40 0.50 0.12 0.16 0.24
e 0.40 0.16
k 0.20 0.08
e
L 0.25 0.30 0.35 0.10 0.12 0.14
Figure 9. Footprint Figure 10. Marking
.
Dimensions
0.40
0.40
1.00
0.20
0.60
0.25
2.10
4/10
Dot: Pin 1 Identification
XX= Marking
XX
EMIF04-1502M8 Package information
Figure 11. Tape and reel specification
1.75 +/- 0.1
4.00+/-0.1
2.0+/-0.05
2.0+/-0.05
8.0 +/- 0.3
8.0 +/- 0.3
1.90
1.90
XX XX
XX XX
4.00+/-0.1
φ 1.5 +/- 0.1
φ 1.5 +/- 0.1
XX
XX
1.75 +/- 0.1
3.5 +/- 0.03
3.5 +/- 0.03
0.75 1.70
0.75 1.70
User direction of unreeling
User direction of unreeling
4.00
4.00
Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin 1
mark is to be used for this purpose.
5/10
Recommendation on PCB assembly EMIF04-1502M8
4 Recommendation on PCB assembly
4.1 Stencil opening design
1. General recommendation on stencil opening design
a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 12. Stencil opening dimensions
L
T
W
b) General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
Aspect Ratio
Aspect Area
-----
1.5≥=
T
LW×
---------------------------2T L W+()
0.66≥=
2. Reference design
a) Stencil opening thickness: 100 µm
b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%.
c) Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 13. Recommended stencil window position
5µm 5µm
15 µm
400 µm
160 µm
0.40
600 µm
570 µm
190 µm
15 µm
160 µm
0.40
50 µm
50 µm
1.00
Footprint
Stencil window
Footprint
200 µm
1000 µm
300 µm
680 µm
0.20
0.60
0.25
2.10
6/10
EMIF04-1502M8 Recommendation on PCB assembly
4.2 Solder paste
1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component movement during high speed
4. Solder paste with fine particles: powder particle size is 20-45 µm.
4.3 Placement
1. Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering
3. Standard tolerance of ±0.05 mm is recommended.
4. 3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
4.4 PCB design preference
1. To control the solder paste amount, the closed via is recommended instead of open
vias.
2. The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
7/10
Recommendation on PCB assembly EMIF04-1502M8
4.5 Reflow profile
Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting
Temperature (°C)
Temperature (°C)
260°C max
260°C max
255°C
255°C
220°C
220°C
180°C
180°C
125 °C
125 °C
3°C/s max
3°C/s max
0
0
012345 67
012345 67
10-30 sec
10-30 sec
90 to 150 sec
90 to 150 sec
90 sec max
90 sec max
2°C/s recommended
2°C/s recommended
6°C/s max
6°C/s max
Time (min)
Time (min)
Note: Minimize air convection currents in the reflow oven to avoid component movement.
8/10
EMIF04-1502M8 Ordering information
5 Ordering information
Table 4. Ordering information
Order code Marking Package Weight Base qty Delivery mode
EMIF04-1502M8 G4
1. The marking can be rotated by 90° to differentiate assembly location
(1)
Micro QFN 4 mg 3000 Tape and reel (7”)
6 Revision history
Table 5. Document revision history
Date Revision Changes
12-Dec-2005 1 Initial release.
03-Jul-2006 2
Reformatted to current standard. Changed Figure 1 to show
improved results.
01-Feb-2007 3 Added note on marking rotation in section 3. Package information.
26-Feb-2007 4 Pins range corrected on Micro QFN bottom view picture on page 1.
04-Feb-2008 5
Reformatted to current standards. Updated ECOPACK statement.
Updated Section 4: Recommendation on PCB assembly.
05-Jan-2009 6 Corrected graphic in Ta b le 3 . Reformatted to current standards.
9/10
EMIF04-1502M8
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