3-line IPAD™, EMI filter including ESD protection
Features
■ EMI symmetrical (I/O) low-pass filter
■ High efficiency in EMI filtering
■ Lead-free package
■ Very low PCB space consuming: 1.2 mm
Very thin package: 0.60 mm
■
■ High efficiency in ESD suppression
■ High reliability offered by monolithic integration
■ High reduction of parasitic elements through
integration and wafer level packaging
Complies with the following standards
■ IEC 61000-4-2 Level 4 on external and V
pins:
– 15 kV (air discharge)
– 8 kV (contact discharge)
■ IEC 61000-4-2 Level 1on internal pins:
– 2 kV (air discharge)
– 2 kV (contact discharge)
■ MIL STD 883E - Method 3015-6 Class 3
Applications
EMI filtering and ESD protection for:
■ SIM Interface (subscriber identify module)
■ UIM Interface (universal identify module)
2
cc
EMIF03-SIM02F3
Flip Chip
(8 bumps)
Figure 1. Pin configuration (bump side)
123
RST
RST
ext
in
Gnd
V
CLK
ext
Data
CC
CLK
in
Data
in
Figure 2. Configuration
V
CC
RST in RST ext
CLK in
Data in
100 Ω
R1
47 Ω
R2
100 Ω
R3
GND
ext
A
B
C
Cline = 20 pF max.
CLK ext
Data ext
Description
The EMIF03-SIM02F3 is a highly integrated
device designed to suppress EMI / RFI noise in all
systems subjected to electromagnetic
interferences.
This filter includes an ESD protection circuitry
which prevents damage to the application when
subjected to ESD surges up to 15 kV.
TM: IPAD is a trademark of STMicroelectronics.
April 2010 Doc ID 11554 Rev 5 1/9
www.st.com
9
Electrical characteristics EMIF03-SIM02F3
1 Electrical characteristics
Table 1. Absolute maximum ratings (T
Symbol Parameter and test conditions Value Unit
Internal pins (A3, B3, C3):
ESD discharge IEC 61000-4-2, air discharge
V
PP
T
j
T
op
ESD discharge IEC 61000-4-2, contact discharge
External pins (A2, B1, C2, C1):
ESD discharge IEC 61000-4-2, air discharge
ESD discharge IEC 61000-4-2, contact discharge
Maximum junction temperature 125 °C
Operating temperature range -40 to +85 °C
amb
= 25 °C)
15
2
2
kV
8
T
Storage temperature range -55 to 150 °C
stg
Figure 3. Electrical characteristics (definitions)
I
Symbol Parameter
V = Breakdown voltage
BR
I = Leakage current @ V
RM RM
V = Stand-off voltage
RM
V = Clamping voltage
CL
I = Peak pulse current
PP
I = Breakdown current
R
V = Forward voltage drop
F
C = Line capacitance
line
R Series resistance between Input and Output
Table 2. Electrical characteristics (T
=
I/O
amb
= 25 °C)
V
V
CL
BR
Symbol Test conditions Min. Typ. Max. Unit
V
BRIR
I
RM
R
d
R
1, R3
R
2
C
line
= 1 mA 6 - 20 V
VRM = 3 V - - 0.2 µA
-1.5- Ω
Tolerance ± 20% - 100 - Ω
Tolerance ± 20% - 47 - Ω
V
line
= 0 V, V
= 30 mV, F = 1 MHz - - 20 pF
osc
I
F
V
F
V
RM
I
RM
I
R
I
PP
V
2/9 Doc ID 11554 Rev 5
EMIF03-SIM02F3 Electrical characteristics
Figure 4. S21 (dB) attenuation measurement
Figure 6. S21 (dB) attenuation measurement
(A2-A3 line)
db
0.00
-10.00
-20.00
-30.00
-40.00
100.0k 1.0M 10.0M 100.0M 1.0G
F (Hz)
a2/a3
Figure 5. S21 (dB) attenuation measurement
(B1-B3 line)
db
0.00
0.00
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
F (Hz)
b1/b3
b1/b3
Figure 7. Analog crosstalk measurements
(C1-C3 line)
db
0.00
0.00
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
F (Hz)
c1/c3
c1/c3
db
0.00
0.00
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
-50.00
-50.00
-60.00
-60.00
-70.00
-70.00
-80.00
-80.00
-90.00
-90.00
-100.00
-100.00
100.0k 1.0M 10.0M 100.0M 1.0G
100.0k 1.0M 10.0M 100.0M 1.0G
F (Hz)
Xtalka3/b1
Xtalka3/b1
Figure 8. Digital crosstalk measurements Figure 9. Line capacitance versus reverse
applied voltage (typical)
Bumps A3 (RST ) and B1 (CLK )
in out
10 ns/div
C(pF)
Output Line 2
2 mV/div
18
15
12
9
Input Line 1
1 V/div
6
3
0
0246
VR(V)
Doc ID 11554 Rev 5 3/9
Aplac model EMIF03-SIM02F3
2 Aplac model
Figure 10. Aplac model
c2
Lbump
Rbump
a2
Lbump Rbump
Lbump Rbump
b1
Lbump Rbump
c1
Figure 11. Aplac parameters
aplacvar Ls 950pH
aplacvar Rs 150m
aplacvar Cext1 12pF
aplacvar Cext2 14pF
aplacvar Cext3 18pF
aplacvar Cint1 4.5pF
aplacvar Cint2 4pF
aplacvar Rbump 17m
aplacvar Lbump 43pH
aplacvar Rgnd 500m
aplacvar Lgnd 50pH
aplacvar Cgnd 0.15pF
aplacvar Rsub 100m
Dint1
BV=15
CJO=Cint1
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.29
VJ=0.6
TT=50n
MODEL = Dext2MODEL = Dext3
MODEL = Dext1MODEL = Dext1
Dext1
BV=15
CJO=Cext1
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.25
VJ=0.6
TT=50n
100
47
100
Cgnd
MODEL = Dint1
Bulk
MODEL = Dint2
Lbump
Rbump
Lgnd
Rgnd
Dint2
BV=15
CJO=Cint2
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.31
VJ=0.6
TT=50n
MODEL = Dint1
Dext2
BV=15
CJO=Cext2
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.28
VJ=0.6
TT=50n
LbumpRbump
LbumpRbump
LbumpRbump
Dext3
BV=15
CJO=Cext3
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.25
VJ=0.6
TT=50n
a3
b3
c3
4/9 Doc ID 11554 Rev 5
EMIF03-SIM02F3 Aplac model
Figure 12. Voltages when IEC 61000-4-2 (+15 kV air discharge) applied to
external pin
Vin: 10 V/div
V
: 10 V/div
out
100 ns/div
Figure 13. Voltages when IEC 61000-4-2 (- 15 kV air discharge) applied to
external pin
Vin: 10 V/div
100 ns/div
V
out
: 10 V/div
Doc ID 11554 Rev 5 5/9
Ordering information scheme EMIF03-SIM02F3
3 Ordering information scheme
Figure 14. Ordering information scheme
EMIF yy - xxx zz Fx
EMI Filter
Number of lines
Information
x = resistance value (ohm)
z = capacitance value / 10 (pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
x = 3: lead-free, pitch = 400 µm, bump = 255 µm
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
Figure 15. Package dimensions
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
400 µm ± 40
1.14 mm ± 30 µm
170 µm ± 10
400 µm ± 40
255 µm ± 40
.
605 µm ± 55
1.14 mm ± 30 µm
170 µm ± 10
6/9 Doc ID 11554 Rev 5
EMIF03-SIM02F3 Ordering information
Figure 16. Footprint Figure 17. Marking
Dot, ST logo
Copper pad Diameter:
220 µm recommended
260 µm maximum
Solder mask opening:
300 µm minimum
ECOPACK status
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
xyxwz
Solder stencil opening :
220 µm recommended
Figure 18. Flip Chip tape and reel specification
w
Dot identifying Pin A1 location
2.0 ± 0.05
0.20 ± 0.02
1.24
8.0 ± 0.3
0.69 ± 0.05
All dimensions in mm
5 Ordering information
4.0 ± 0.1
ST
ST
ST
yww
yww
xxz
xxz
E
E
ST
yww
yww
xxz
xxz
E
E
1.24
User direction of unreeling
4.0 ± 0.1
Ø 1.55 ± 0.1
ST
ST
yww
yww
xxz
xxz
E
E
1.75 ± 0.1
3.5 ± 0.1
Table 3. Ordering information
Order code Marking Package Weight Base qty Delivery mode
EMIF03-SIM02F3 HA Flip Chip 1.74 mg 5000 Tape and reel 7”
Note: More information is available in the application notes:
AN2348: “STMicroelectronics 400 micro-metre Flip Chip: package description and
recommendation for use”
AN1751: "EMI filters: recommendations and measurements"
Doc ID 11554 Rev 5 7/9
Revision history EMIF03-SIM02F3
6 Revision history
Table 4. Document revision history
Date Revision Changes
19-Jul-2005 1 Initial release.
Changed out to ext in Configuration diagram on page 1. Added
26-Feb-2007 2
Ecopack statement. Reformatted to current layour standard.
Updated Application note AN2348 reference and description.
28-Nov-2007 3
09-Feb-2010 4
07-Apr-2010 5 Updated tolerance dimensions in Figure 15: Package dimensions.
Updated ECOPACK statement. Updated Figure 14, Figure 15,
Figure 16 and Figure 18. Reformatted to current standards.
Updated die dimensions in Figure 15 and pocket dimensions in
Figure 18.
8/9 Doc ID 11554 Rev 5
EMIF03-SIM02F3
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Doc ID 11554 Rev 5 9/9
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