3-line IPAD™, EMI filter including ESD protection
Features
■ EMI symmetrical (I/O) low-pass filter
■ High efficiency in EMI filtering
■ Lead-free package
■ Very low PCB space consuming:
1.42 mm x 1.42 mm
■ Very thin package: 0.65 mm
■ High efficiency in ESD suppression
■ High reliability offered by monolithic integration
■ High reduction of parasitic elements through
integration and wafer level packaging
Complies with the following standards
■ IEC 61000-4-2, Level 4 on external and V
pins:
– 15 kV (air discharge)
– 8 kV (contact discharge)
■ IEC 61000-4-2, Level 1 on internal pins:
– 2 kV (air discharge)
– 2 kV (contact discharge)
■ MIL STD 883E - Method 3015-6 Class 3
Applications
EMI filtering and ESD protection for:
■ SIM Interface (Subscriber Identify Module)
■ UIM Interface (Universal Identify Module)
cc
EMIF03-SIM02F2
Flip Chip
(8 bumps)
Figure 1. Pin configuration (bump side)
123
RST
RST
ext
in
Gnd
V
CLK
Data
CC
CLK
in
Data
in
Figure 2. Configuration
V
CC
RST in RST ext
CLK in
Data in
100 Ω
R1
47 Ω
R2
100 Ω
R3
GND
A
B
ext
C
ext
Cline = 20pF max.
CLK ext
Data ext
Description
The EMIF03-SIM02F2 is a highly integrated
device designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic
interference.The EMIF03 Flip Chip packaging
means the package size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents damage to the application when
subjected to ESD surges up 15kV.
April 2008 Rev 6 1/8
TM: IPAD is a trademark of STMicroelectronics.
www.st.com
8
Characteristics EMIF03-SIM02F2
1 Characteristics
Table 1. Absolute maximum ratings (T
Symbol Parameter and test conditions Value Unit
Internal pins (A3, B3, C3):
ESD discharge IEC61000-4-2, air discharge
V
ESD discharge IEC61000-4-2, contact discharge
PP
External pins (A2, B1, C2, C1):
ESD discharge IEC61000-4-2, air discharge
ESD discharge IEC61000-4-2, contact discharge
amb
= 25 °C)
15
2
2
kV
8
T
T
T
Table 2. Electrical characteristics (T
Maximum junction temperature 125 °C
j
Operating temperature range -40 to +85 °C
op
Storage temperature range -55 to 150 °C
stg
= 25 °C)
amb
Symbol Parameters
V
BR
I
RM
V
RM
V
R
I
PP
R
C
line
Breakdown voltage
Leakage current @ V
Stand-off voltage
Clamping voltage
CL
Dynamic impedance
d
Peak pulse current
Series resistance between Input &
I/O
Output
Input capacitance per line
RM
V
V
CL
BR
I
I
F
V
V
RM
F
I
RM
I
R
I
PP
V
Symbol Test conditions Min Typ Max Unit
V
R
C
BR
I
RM
R
1, R3
R
line
IR = 1 mA 6 20 V
VRM = 3V 0.2 µA
d
1.5 Ω
Tolerance ± 20% 100 Ω
Tolerance ± 20% 47 Ω
2
@ 0V 20 pF
2/8
EMIF03-SIM02F2 Characteristics
Figure 3. S21 (dB) attenuation measurement
(A2-A3 line)
EMIF03-SIM02F2_FREQ-MEAS_PM428
0.00
dB
-10.00
-20.00
-30.00
-40.00
100.0k 1.0M 10.0M 100.0M 1.0G
Aplac 7.70 User: ST Microelectronics Sep 22 2004
A2/A3 Line
f/Hz
Figure 5. S21 (dB) attenuation measurement
(C1-C3 line)
EMIF03-SIM02F2_FREQ-MEAS_PM428
0.00
dB
-10.00
-20.00
-30.00
-40.00
100.0k 1.0M 10.0M 100.0M 1.0G
Aplac 7.70 User: ST Microelectronics Sep 22 2004
C1/C3 line
f/Hz
Figure 7. Voltages when IEC61000-4-2
(+15 kV air discharge) applied to
external pin
Figure 4. S21 (dB) attenuation measurement
(B1-B3 line)
EMIF03-SIM02F2_FREQ-MEAS_PM428
0.00
dB
-10.00
-20.00
-30.00
-40.00
100.0k 1.0M 10.0M 100.0M 1.0G
Aplac 7.70 User: ST Microelectronics Sep 22 2004
B1/B3 line
f/Hz
Figure 6. Analog crosstalk measurements
EMIF03-SIM02F2_FREQ-MEAS_PM428
0.00
dB
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
100.0k 1.0M 10.0M 100.0M 1.0G
Aplac 7.70 User: ST Microelectronics Sep 22 2004
Xtalk A2/B3
f/Hz
Figure 8. Voltages when IEC61000-4-2 (-15 kV
air discharge) applied to external
pin
Vexternal : 10V/d
Vinternal : 10V/d
100ns/d
Vexternal : 5V/d
Vinternal
: 5V/d
100ns/d
3/8
Application information EMIF03-SIM02F2
Figure 9. Line capacitance versus reverse applied voltage (typical)
C(pF)
20.00
16.00
12.00
8.00
4.00
0.00
012345
2 Application information
Figure 10. Aplac model
LbumpRbump
a2
b3
c1
Por t1
50
RsubCbump
Lbump Rbump
RsubCbump
LbumpRbump
Rsub
Cbump
Ls 100m
bulk
bulk
bulk
Dext1
0.25
a2
Dext2
0.28
Cgnd
Dext1
0.25
100
47
100
Bulk
VR(V)
Dint1
Lbump
Rbump
Lgnd
Rgnd
Dint1
Dint2
0.29 0.31
0.29
bulk
bulk
bulk
a3
LbumpRbump
Rsub Cbump
LbumpRbump
Rsub Cbump
LbumpRbump
Rsub Cbump
100m Ls
a3
b1
c3
Por t2
50
Figure 11. Aplac parameters
Ls 950pH
Rs 150m
Cext1 15pF
Cint1 4.5pF
Cext2 14pF
Cint2 4pF
Rbump 20m
Lbump 50pH
Cbump 0.15pF
Rgnd 500m
Lgnd 50pH
Cgnd 0.15pF
Rsub 100m
4/8
Model Dint1
BV=15
CJO=Cint1
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.001m
VJ=0.6
TT=50n
Model Dext1
BV=15
CJO=Cext1
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.001m
VJ=0.6
TT=50n
Model Dint2
BV=15
CJO=Cint2
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.001m
VJ=0.6
TT=50n
Model Dext2
BV=15
CJO=Cext2
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.001m
VJ=0.6
TT=50n
EMIF03-SIM02F2 Ordering information scheme
3 Ordering information scheme
Figure 12. Ordering information scheme
EMIF yy - xxx zz Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
x = 2: lead-free pitch = 500 µm, bump = 315 µm
4 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 13. Package dimensions
500 µm ± 50
195 µm
500 µm ± 50
1.39 mm ± 30 µm
315 µm ± 50
650 µm ± 65
1.39 mm ± 30 µm
195 µm
5/8
Ordering information EMIF03-SIM02F2
Figure 14. Footprint Figure 15. Marking
Dot, ST logo
Copper pad Diameter:
250 µm recommended, 300 µm max
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 315 µm copper pad diameter
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
E
xyxwz
w
Figure 16. Flip Chip tape and reel specification
Dot identifying Pin A1 location
4 ± 0.1
Ø 1.5 ± 0.1
1.75 ± 0.1 3.5 ± 0.1
8 ± 0.3
ST
0.73 ± 0.05
All dimensions in mm
yww
xxz
E
yww
User direction of unreeling
Note: More information isavailable in the application notes:
AN1235:"Flip Chip: Package description and recommendations for use"
AN1751: “EMI filters: Recommendations and measurements”
5 Ordering information
Table 3. Ordering information
Order code Marking Package Weight Base qty Delivery mode
EMIF03-SIM02F2 GJ Flip Chip 2.65 mg 5000 Tape and reel 7”
1.52
xxz
ST
E
1.52
4 ± 0.1
yww
ST
xxz
E
6/8
EMIF03-SIM02F2 Revision history
6 Revision history
Table 4. Document revision history
Date Revision Changes
08-Oct-2004 1 First issue.
20-Oct-2004 2 Minor layout update.
25-Mar-2005 3
13-Jun-2005 4 Titles in Figures 7 and 8 changed - No technical data changed
12-Sep-2005 5 “out” changed to “ext” in Figure 2.
24-Apr-2008 6
Figure 1 on page 1: pin configuration definitions changed from RST
out, CLK out and Data out to RST ext, CLK ext and Data ext.
Updated ECOPACK statement. Updated Figure 12, Figure 13,
Figure 14, Figure 15 and Figure 16. Reformatted to current
standards.
7/8
EMIF03-SIM02F2
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