ST EMIF02-USB01F2 User Manual

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2-line IPAD™, EMI filter including ESD protection

Features

■ 2-line low-pass filter + ESD protection

■ High efficiency in EMI filtering

■ Lead-free package

■ Very low PCB space occupation: < 2.5 mm

Very thin package: 0.65 mm

■

■ High efficiency in ESD suppression

(IEC 61000-4-2 level 4)

■ High reliability offered by monolithic integration

■ High reduction of parasitic elements through

integration and wafer level packaging

Complies with the following standards

■ IEC 61000-4-2 level 4

– ±15 kV (air discharge) – ±8 kV (contact discharge)

Application

EMIF02-USB01F2

Flip Chip

(8 bumps)

Figure 1. Pin configuration (bump side

view)

32 1

Pup

Vbus

D+ in

GND

Din

D+ out

Dout

■ ESD protection and EMI filtering for USB port

Description

The EMIF02-USB01F2 is a highly integrated array

Figure 2. Schematic

Vbus

D+ out

1.3K

designed to suppress EMI / RFI noise for USB port filtering. The EMIF02-USB01F2 Flip-Chip packaging means the package size is equal to the die size.

Additionally, this filter includes ESD protection

GND

D- out D- in

circuitry which prevents damage to the protected device when subjected to ESD surges up to 15 kV.

TM: IPAD is a trademark of STMicroelectronics.

September 2009 Doc ID 10950 Rev 4 1/8

Pup

D+ in

www.st.com

Characteristics EMIF02-USB01F2

1 Characteristics

Table 1. Absolute ratings (T

Symbol Parameter Value Unit

amb

= 25 °C)

Junction temperature 125 °C

Operating temperature range -40 to +85 °C

Storage temperature range -55 to 150 °C

stg

Figure 3. Electrical characteristics - definitions

Symbol Parameter

V Stand-off voltage

V Breakdown voltage

I Leakage current @ V

RM RM

Table 2. Electrical characteristics - values (T

eak pulse current

Input capacitance per line

line

VBRV

amb

Symbol Test conditions Min. Typ. Max. Unit

line

, R

IR = 1 mA 6 - - V

VRM = 3 V - - 0.5 µA

@ 0 V - 40 45 pF

Tolerance ± 5 % - 33 - Ω

Tolerance ± 5 % - 1.30 - kΩ

= 25 °C)

VRMV

2/8 Doc ID 10950 Rev 4

EMIF02-USB01F2 Characteristics

Figure 4. S21 (dB) attenuation measurement Figure 5. Analog crosstalk measurements

EMIF02-USB01: filtering response of lines C1/C3 and E1/E3

0.00

0.00 dB

-5.00

-10.00

-15.00

-20.00

-25.00

-30.00

-35.00

-40.00

-45.00

-50.00

1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G

E1_E3

Frequency/Hz

C1_C3

Figure 6. ESD response to IEC 61000-4-2

(+15 kV air discharge) on one input (Vin) and one output (Vout)

0.00 dB

-10.00

-20.00

-30.00

-40.00

-50.00

-60.00

-70.00

-80.00

-90.00

-100.0

1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G

f/Hz

Figure 7. ESD response to IEC 61000-4-2

(-15 kV air discharge) on one input (Vin) and on one output (Vout)

Vin: 10 V/d

Vin: 5 V/d

50 ns/d

Figure 8. Capacitance versus reverse applied voltage (typical)

C(pF)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

VR(V)

Vin: 5 V/d

100 ns/d

Doc ID 10950 Rev 4 3/8

Application information EMIF02-USB01F2

2 Application information

Figure 9. Aplac model (resistors, diodes and bumps and ground connections)

rsub_1k3

rsub_33R

R_1k3

bulk

R_33R

bulk

R_33R

bulk

rsub_1k3

Csub

rsub_33R

Csub

rsub_33R

Csub

0.23nH

cap_33RCsub

0.7nH

cap_33RCsub

3.8nH

0.15nH

cap_33R

0.3nH

cap_33R

Csub

Figure 10. Aplac model parameters

R_33R 33.9

R_33R 33.9 cap_33R 1.2pF

cap_33R 1.2pF

R_1k3 1.3k

Cz29pF Rsub_D 100

Csub0.3pF Rsub_33R 15 Rsub_1k3 50

A1, A3, B2, C1, C3, E1, E3

D02_usb

Lgnd_D

Model D02_Nw BV=100 IBV=1m CJO=6.8p M=0.3333 RS=2 VJ=0.6 TT=100n

0.15nH

D2 bulk

I/O

D02_Nw

Rsub_D

Model D02_usb BV=16 IBV=1m CJO=Cz M=0.3333 RS=2 VJ=0.6 TT=100n

Cbump Rsubump

100m

bulk

caphole

Lbump

Rbump

Lhole

Rhole

lhole10pH Rhole400m Caphole0.4pF Lgnd_D 150pH

Lbump50pH Rbump50m Cbump1.5pF Rsubump150

4/8 Doc ID 10950 Rev 4

EMIF02-USB01F2 Ordering information scheme

EMIF

3 Ordering information scheme

Figure 11. Ordering information scheme

yy - xxx zz Fx

EMI filter

Number of lines

Information

x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version

Package

F = Flip Chip X = 2: lead-free, pitch = 500 µm, bump = 315 µm

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com ECOPACK

Figure 12. Package dimensions

packages, depending on their level of environmental compliance. ECOPACK®

is an ST trademark.

495µm ± 50

285 µm

1.27mm ± 50µm

315 ± 50700 ± 50

1.97mm ± 50µm

285µm

650µm ± 65

Doc ID 10950 Rev 4 5/8

Ordering information EMIF02-USB01F2

Figure 13. Footprint Figure 14. Marking

Dot, ST logo xx = marking

Copper pad Diameter:

250 µm recommended, 300 µm max

Solder stencil opening: 330 µm

Solder mask opening recommendation:

340 µm min for 315 µm copper pad diameter

z = manufacturing location yww = datecode

(y = year

ww = week)

Figure 15. Flip Chip tape and reel specification

Dot identifying Pin A1 location

4 ± 0.1

yww

2.07

xxz

1.37

4 ± 0.1

0.73 ± 0.05

8 ± 0.3

yww

xxz

Ø 1.5 ± 0.1

yww

xxz

xxz y

1.75 ± 0.1 3.5 ± 0.1

All dimensions in mm

5 Ordering information

Table 3. Ordering information

Order code Marking Package Weight Base qty Delivery mode

EMIF02-USB01F2 FF Flip Chip 3.35 mg 5000 Tape and reel 7”

Note: More information is available in the application notes:

AN1235:"Flip Chip: Package description and recommendations for use" AN1751: “EMI filters: Recommendations and measurements”

User direction of unreeling

6/8 Doc ID 10950 Rev 4

EMIF02-USB01F2 Revision history

6 Revision history

Table 4. Document revision history

Date Revision Changes

26-Oct-2004 1 Initial release.

16-Apr-2007 2

Updated ECOPACK statement. Updated Figure 11, Figure 12 and

Figure 15. Reformatted to current standards.

29-Apr-2008 3 Typographical errors corrected.

18-Sep-2009 4 Updated ESD graphic in Figure 6 and Figure 7.

Doc ID 10950 Rev 4 7/8

EMIF02-USB01F2

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Information in this document supersedes and replaces all information previously supplied.

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www.st.com

8/8 Doc ID 10950 Rev 4

ST EMIF02-USB01F2 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Figure 2. Schematic

1 Characteristics

Figure 3. Electrical characteristics - definitions

Figure 8. Capacitance versus reverse applied voltage (typical)

2 Application information

Figure 9. Aplac model (resistors, diodes and bumps and ground connections)

Figure 10. Aplac model parameters

3 Ordering information scheme

Figure 11. Ordering information scheme

4 Package information

Figure 12. Package dimensions

Figure 13. Footprint Figure 14. Marking

Figure 15. Flip Chip tape and reel specification

5 Ordering information

Table 3. Ordering information

6 Revision history

Table 4. Document revision history