2-line IPAD™ EMI filter and ESD protection
Features
■ 2-line symmetrical low-pass filter
■ Lead-free package
■ Very low PCB space consuming: < 1.5 mm
Very thin package: 0.65 mm
■
■ High efficiency in ESD suppression
IEC 61000-4-2 level 4
■ High reliability offered by monolithic integration
■ High reduction of parasitic elements through
integration and wafer level packaging
Complies with the following standards
■ IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)
2
EMIF02-MIC06F3
Lead-free Flip-Chip package
(8 bumps)
Figure 1. Pin configuration (bump side)
123
MIC
Bias
ECI
A
Application
■ Mobile phones (differential microphone filtering
and ESD protection)
Description
The EMIF02-MIC06F3 is a highly integrated
device designed to suppress EMI/RFI noise for
dual microphone line filtering.
The EMIF02-MIC06F3 Flip-Chip packaging
means the package size is equal to the die size.
That's why EMIF02-MIC06F3 is a very small
device.
Additionally, this filter includes an ESD protection
circuitry which prevents damage to the application
when subjected to ESD surges up to 15 kV.
TM: IPAD is a trademark of STMicroelectronics.
Op
On
n
Gnd
A
Gnd
Mic2p
Mic2n
B
C
September 2011 Doc ID 15195 Rev 4 1/8
www.st.com
8
Characteristics EMIF02-MIC06F3
1 Characteristics
Figure 2. Configuration
GND
GND
B1
Mic2p
Mic2n
C1 C3
GND
GND
ECI
A2
Mic Bias
C11 C21
C12
GND
B2 and C2 are ground pins
A3
R11
R12
GND
R21R31
R22
C22
GND
B3
to ASIC
ECI pin connection
The ECI pin (enhancement control interface) is an input pin for the audio pre-amplifier chip
which detects the voltage of the microphone line MIC2P in case the user presses the onhook/off-hook button on the headset. When the user selects off-hook using the headset
button, the MIC2P is shorted to MIC2N which is grounded. If your design does not support
the ECI feature, the ECI pin must be left open (not connected).
Table 1. Absolute ratings (limiting values)
Symbol Parameter and test conditions Value Unit
Pins B1 and C1:
ESD discharge IEC 61000-4-2, level 4
air discharge
V
PP
contact discharge
Pins A2, A3, B2, B3, C2, C3:
ESD discharge IEC 61000-4-2, level 1
air discharge
contact discharge
P
T
T
op
T
stg
Power dissipation at T
D
Maximum junction temperature 125 °C
j
Operating temperature range - 40 to + 85 °C
Storage temperature range - 55 to + 150 °C
= 25 °C 60 mW
amb
2/8 Doc ID 15195 Rev 4
15
8
kV
2
2
EMIF02-MIC06F3 Characteristics
Figure 3. Electrical characteristics (definitions)
I
Symbol Parameter
V = Breakdown voltage
BR
I = Leakage current @ V
RM RM
R = Series resistance
I/O
between input and output
C = Line capacitance
line
IR
IRM
VRMVBR
IRM
IR
V
V
BRVRM
Table 2. Electrical characteristics - values (T
Symbol Test conditions Min. Typ. Max. Unit
V
BR
I
RM
R
11
R
12
R
, R
21
22
R
31
, C
C
11
12
C
, C
21
22
IR = 1 mA 14 V
VRM = 3 V per line 100 nA
VR = 0 V 0.8 1 nF
VR = 0 V 1 1.25 nF
Figure 4. Attenuation simulation with
1 kΩ input and 10 kΩ output
db
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
10 100 1k 10k 100k 1M 10M 100M 1G
Input: 1 k
Output: 10 k
AC simulation
Ω
Ω
50Ω measurements
50Ω simulations
F (Hz)
= 25 °C)
amb
1.922.1kΩ
0.811.2kΩ
1.76 2.2 2.64 kΩ
20 25 30 Ω
Figure 5. Analog crosstalk measurement
db
0.00
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.00
100.0k 1.0M 10.0M 100.0M 1.0G
Mic2p-On
F (Hz)
Mic2n-Op
Doc ID 15195 Rev 4 3/8
Characteristics EMIF02-MIC06F3
Figure 6. ESD response to IEC 61000-4-2
(+15 kV air discharge) on Mic2p
10 V/div
Input
5 V/div
Output
500 ns/div
Figure 8. ESD response to IEC 61000-4-2
(+15 kV air discharge) on Mic2n
10 V/div
Input
2 V/div
Figure 7. ESD response to IEC 61000-4-2
(-15 kV air discharge) on Mic2p
10 V/div
5 V/div
Input
Output
500 ns/div
Figure 9. ESD response to IEC 61000-4-2
(-15 kV air discharge) on Mic2n
10 V/div
2 V/div
Input
Output
200 ns/div
Figure 10. Line capacitance versus applied voltage
C
(pF)
0.00
LINE
V
LINE
0
0.5
1
1 200.00
1 000.00
800.00
600.00
400.00
200.00
1.5
(V)
V
2
OSC
Output
F = 1 Mhz
= 30 mV rms
Tj= 25 °C
2.5
200 ns/div
3
4/8 Doc ID 15195 Rev 4
EMIF02-MIC06F3 Ordering information scheme
2 Ordering information scheme
Figure 11. Ordering information scheme
EMIF yy - xxx zz Fx
EMI filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
x = 3: lead-free, pitch = 400 µm
3 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
Figure 12. Flip Chip package dimensions
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
400 µm ± 40
200 µm
1.20 mm ± 30 µm
400 µm ± 40
255 µm ± 40
.
605 µm ± 55
1.20 mm ± 30 µm
200 µm
Doc ID 15195 Rev 4 5/8
Ordering information EMIF02-MIC06F3
Figure 13. Footprint recommendations Figure 14. Marking
Dot, ST logo
Copper pad Diameter:
220µm recommended
260µm maximum
Solder mask opening:
300µm minimum
ECOPACK status
xx = marking
z = manufacturing location
yww = datecode
(y = year
xyxwz
Solder stencil opening :
220µm recommended
Figure 15. Flip Chip tape and reel specification
w
Dot identifying Pin A1 location
0.22
1.30
8.0
0.69
All dimensions are typical values in mm
4 Ordering information
Table 3. Ordering information
2.0
4.0
ST
ST
yww
yww
xxz
xxz
ST
yww
xxz
1.30
User direction of unreeling
4.0
Ø 1.55
ST
yww
xxz
1.75
3.5
Order code Marking Package Weight Base qty Delivery mode
EMIF02-MIC06F3 JB Flip Chip 1.8 mg 5000 Tape and reel 7”
Note: More information is available in the application notes
AN2348: “Flip Chip: Package description and recommendations for use”
AN1751: “EMI Filters: Recommendations and measurements”
6/8 Doc ID 15195 Rev 4
EMIF02-MIC06F3 Revision history
5 Revision history
Table 4. Document revision history
Date Revision Changes
21-Nov-2008 1 Initial release
05-Mar-2009 2 Updated Figure 4 and Figure 12.
07-Apr-2010 3 Updated tolerance Figure 12.
23-Sep-2011 4 Added ECI pin connection on page 2.
Doc ID 15195 Rev 4 7/8
EMIF02-MIC06F3
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8/8 Doc ID 15195 Rev 4
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