Where EMI filtering in ESD sensitive equipment is
required :
■ Mobile phones and communication systems
■ Computers, printers and MCU Boards
DESCRIPTION
The EMIF02-MIC03 is a highly integrated device
designed to suppress EMI/RFI noise in all systems
subjected to electromagnetic interferences. The
EMIF02 Flip-Chip packaging means the package
size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents damage to the application when
subjected to ESD surges up 15 kV.
BENEFITS
■ EMI symmetrical (I/O) low-pass filter
■ High efficiency in EMI filtering
■ Very low PCB space consuming:
1.07 mm x 1.47 mm
■ Very thin package: 0.65 mm
■ High efficiency in ESD suppression
■ High reliability offered by monolithic integration
■ High reducing of parasitic elements through
integration & wafer level packaging
EMIF02-MIC03F2
2 LINE EMI FILTER
AND ESD PROTECTIONIPAD™
Flip-Chip package
PIN CONFIGURATION (bump side)
132
I1
I2
A
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC 61000-4-2
Level 4 on input pins15 kV (air discharge)
8 kV (contact discharge)
Level 1 on output pins 2 kV (air discharge)
2 kV (contact discharge)
MIL STD 883E - Method 3015-6 Class 3
BASIC CELL CONFIGURATION
Low-pass Filter
Input
GNDGNDGND
TM: IPAD is a trademark of STMicroelectronics.
October 2004
REV. 1
GND
O2
Output
B
O1
C
Ri/o = 68
Ω
Cline = 100 pF
1/6
EMIF02-MIC03F2
ABSOLUTE RATINGS (limiting values)
SymbolParameter and test conditionsValueUnit
T
T
op
T
stg
Maximum junction temperature
j
Operating temperature range - 40 to + 85
Storage temperature range - 55 to 150
125°C
°C
°C
ELECTRICAL CHARACTERISTICS (T
SymbolParameter
V
I
RM
V
V
R
I
R
C
Breakdown voltage
BR
Leakage current @ VRM
Stand-off voltage
RM
Clamping voltage
CL
Dynamic impedance
d
Peak pulse current
PP
Series resistance between Input & Output
I/O
Input capacitance per line
line
= 25 °C)
amb
I
I
PP
I
R
I
V
CL
BR
RM
VRMV
I
RM
I
R
I
PP
VBRV
RM
V
V
CL
SymbolTest conditionsMin.Typ.Max.Unit
V
BR
I
RM
R
I/O
C
line
Fig. 1: S21 (dB) attenuation measurements and
IR = 1 mA68V
VRM = 3 V per line
500nA
Tolerance ± 20 %68Ω
VR = 0 V
100pF
Fig. 2: Analog crosstalk measurements.
Aplac simulation.
2/6
0.00
0.00
dB
dB
-5.00
-5.00
-10.00
-10.00
-15.00
-15.00
-20.00
-20.00
-25.00
-25.00
-30.00
-30.00
-35.00
-35.00
-40.00
-40.00
-45.00
-45.00
-50.00
-50.00
100.0k1.0M10.0M100.0M1.0G
100.0k1.0M10.0M100.0M1.0G
f/Hz
f/Hz
0.00
0.00
dB
dB
-10.00
-10.00
-20.00
-20.00
-30.00
-30.00
-40.00
-40.00
-50.00
-50.00
-60.00
-60.00
-70.00
-70.00
-80.00
-80.00
100.0k1.0M10.0M100.0M1.0G
100.0k1.0M10.0M100.0M1.0G
f/Hz
f/Hz
®
EMIF02-MIC03F2
Fig. 3: ESD response to IEC61000-4-2 (+15kV air
discharge) on one input V(in) and one output V(out).
Fig. 5: Line capacitance versus applied voltage.
C(pF)
140
120
100
80
60
40
20
0
012345
V(V)R
V
F=1MHz
=30mV
osc
Tj=25°C
RMS
Fig. 4: ESD response to IEC61000-4-2 (–15kV air
discharge) on one input V(in) and one output V(out).
®
3/6
EMIF02-MIC03F2
Aplac model
IN1
IN2OUT2
Rbump LbumpLbump Rbump
model = D1model = D2
model = D1
Rbump LbumpLbump RbumpRmicLmic
RmicLmic
model = D3
model = D2
EMIF02-MIC03F1 model
Aplac parameters
Model D1
CJO=Cdiode1
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.7
VJ=0.6
TT=50n
Model D3
CJO=Cdiode3
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.12
VJ=0.6
TT=50n
Model D2
CJO=Cdiode2
BV=7
IBV=1u
IKF=1000
IS=10f
ISR=100p
N=1
M=0.3333
RS=0.3
VJ=0.6
TT=50n
OUT1
GND
Cgnd
aplacvar Rmic 68
aplacvar Lmic 10p
aplacvar Cdiode1 100pF
aplacvar Cdiode2 3.6pF
aplacvar Cdiode3 1.17nF
aplacvar Lbump 50pH
aplacvar Rbump 20m
aplacvar Rsub 0.5m
aplacvar Rgnd 10m
aplacvar Lgnd 50pH
aplacvar Cgnd 0.15pF
aplacvar Lsub 10pH
GND
Lsub
Rsub
Rbump
Lbump
Lgnd
Rgnd
Ground return
ORDER CODE
EMI Filter
Number of lines
4/6
EMIF yyF x-xxx zz
1: Pitch = 500µm
Bump = 315µm
2: Leadfree Pitch = 500µm
Bump = 315µm
Flip Chip
x: resistance value (Ohms) z: capacitance value / 10(pF)
or
Application (3 letters) and Version (2 digits)
®
PACKAGE MECHANICAL DATA
5
FLIP CHIP
500µm ± 10
250µm ± 10
315µm ± 50
EMIF02-MIC03F2
650µm ± 50
00µm ± 15
1.07mm ± 50µm
FOOT PRINT RECOMMENDATIONS
Copper pad Diameter :
250µm recommended , 300µm max
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 300µm copper pad diameter
MARKING
1.47mm ± 50µm
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year ww = week)
E
xyxwz
w
®
5/6
EMIF02-MIC03F2
PACKING
Dot identifying Pin A1 location
4 ± 0.1
Ø 1.5 ± 0.1
1.75 ± 0.1
3.5 ± 0.1
0.73 ± 0.05
All dimensions in mm
8 ± 0.3
EEE
ST
xxz
yww
ST
xxz
yww
4 ± 0.1
User direction of unreeling
ST
xxz
yww
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Note: More packing informations are available in the application notes
AN1235: ''Flip-Chip: Package description and recommendations for use''
AN1751: "EMI Filters: Recommendations and measurements"
REVISION HISTORY
DateRevisionChanges
14-Oct-20051Initial release.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners