ST CR14 User Manual

ISO14443 type-B contactless coupler chip

SO16 (MQ)

150 mils width

Features

■ Single 5 V ±500 mV supply voltage

■ SO16N package

■ Contactless communication

– ISO14443 type-B protocol – 13.56MHz carrier frequency using an

external oscillator – 106 Kbit/s data rate – 36-byte input/output frame register – Supports frame answer with/without

SOF/EOF – CRC generation and check – Automated ST anti-collision exchange

■ I²C communication

– Two-wire I²C serial interface – Supports 400 kHz protocol – 3 chip enable pins – Up to 8 CR14 connected on the same bus

CR14

with anti-collision and CRC management

March 2010 Doc ID 11922 Rev 2 1/47

www.st.com

Contents CR14

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Oscillator (OSC1, OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Antenna output driver (RF

2.3 Antenna input filter (RF

2.4 Transmitter reference voltage (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

OUT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

REF

2.5 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.6 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7 Chip enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.8 Power supply (V

, GND, GND_RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 CR14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Parameter register (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2 Input/Output Frame Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Slot marker register (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 CR14 I²C protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 I²C start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 I²C stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 I²C acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 I²C data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5 I²C memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.6 CR14 I²C write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 CR14 I²C read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Applying the I²C protocol to the CR14 registers . . . . . . . . . . . . . . . . . 22

5.1 I²C parameter register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 I²C input/output frame register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 I²C slot marker register protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4 Addresses above location 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2/47 Doc ID 11922 Rev 2

CR14 Contents

6 CR14 ISO14443 type-B radio frequency data transfer . . . . . . . . . . . . . 26

6.1 Output RF data transfer from the CR14 to the PICC (request frame) . . . 26

6.2 Transmission format of request frame characters . . . . . . . . . . . . . . . . . . 26

6.3 Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.4 Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.5 Input RF data transfer from the PICC to the CR14 (answer frame) . . . . . 28

6.6 Transmission format of answer frame characters . . . . . . . . . . . . . . . . . . . 28

6.7 Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.8 Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.9 Transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.10 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7 Tag access using the CR14 coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.1 Standard TAG command access description . . . . . . . . . . . . . . . . . . . . . . 31

7.2 Anti-collision TAG sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Appendix A ISO14443 type B CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Doc ID 11922 Rev 2 3/47

List of tables CR14

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. CR14 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Parameter register bits description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Input/output frame register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Slot marker register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 7. CR14 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 9. I²C AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 10. I²C Input Parameters(1,2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 11. I²C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 12. I²C AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 13. RF Table 14. RF Table 15. SO16 narrow - 16 lead plastic small outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 16. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

OUT

AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4/47 Doc ID 11922 Rev 2

CR14 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. SO pin connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. CR14 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Maximum R

Figure 6. I²C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7. CR14 I²C write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. I²C polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. CR14 I²C read modes sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Host-to-CR14 transfer: I²C write to parameter register . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11. CR14-to-host transfer: I²C random address read from parameter register . . . . . . . . . . . . 22

Figure 12. CR14-to-host transfer: I²C current address read from parameter register . . . . . . . . . . . . . 22

Figure 13. Host-to-CR14 transfer: I²C write to I/O frame register for ISO14443B . . . . . . . . . . . . . . . . 23

Figure 14. CR14-to-host transfer: I²C random address read from I/O frame register for ISO14443B 23 Figure 15. CR14-to-host transfer: I²C current address read from I/O frame register for ISO14443B . 24

Figure 16. Host-to-CR14 transfer: I²C write to slot marker register . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17. CR14-to-host transfer: I²C random address read from slot marker register . . . . . . . . . . . 24

Figure 18. CR14-to-host transfer: I²C current address read from slot marker register . . . . . . . . . . . . 25

Figure 19. Wave transmitted using ASK modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 20. CR14 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 21. Request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 22. Request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 23. Wave received using BPSK sub-carrier modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 24. Answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 25. Answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 26. Example of a complete transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 27. CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 28. Standard TAG command: request frame transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 29. Standard TAG command: answer frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 30. Standard TAG command: complete TAG access description. . . . . . . . . . . . . . . . . . . . . . . 32

Figure 31. Anti-collision ST short range memory sequence (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 32. Anti-collision ST short range memory sequence continued . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 33. I²C AC testing I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 34. I²C AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 35. CR14 synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 36. SO16 narrow - 16 lead plastic small outline, 150 mils body width, Package outline . . . . . 42

value versus bus capacitance (C

) for an I²C bus . . . . . . . . . . . . . . . . . . 11

BUS

Doc ID 11922 Rev 2 5/47

Summary description CR14

1 Summary description

The CR14 is a contactless coupler that is compliant with the short range ISO14443 type-B

standard. It is controlled using the two wire I²C bus.

The CR14 generates a 13.56 MHz signal on an external antenna. Transmitted data are

modulated using Amplitude Shift Keying (ASK). Received data are demodulated from the

PICC (Proximity integrated Coupling Card) load variation signal, induced on the antenna,

using Bit Phase Shift Keying (BPSK) of a 847kHz sub-carrier. The Transmitted ASK wave is

10% modulated. The Data transfer rate between the CR14 and the PICC is 106 Kbit/s in

both transmission and reception modes.

The CR14 follows the ISO14443 type-B recommendation for Radio frequency power and

signal interface.

The CR14 is specifically designed for short range applications that need disposable and

reusable products.

The CR14 includes an automated anti-collision mechanism that allows it to detect and

select any ST short range memories that are present at the same time within its range. The

anti-collision mechanism is based on the STMicroelectronics probabilistic scanning method.

The CR14 provides a complete analog interface, compliant with the ISO14443 type-B

recommendations for Radio-Frequency power and signal interfacing. With it, any ISO14443

type-B PICC products can be powered and have their data transmission controlled via a

simple antenna.

The CR14 is fabricated in STMicroelectronics High Endurance Single Poly-silicon CMOS

technology.

The CR14 is organized as 4 different blocks (see Figure 2):

● The I²C bus controller. It handles the serial connection with the application host. It is

compliant with the 400kHz I²C bus specification, and controls the read/write access to all the CR14 registers.

● The RAM buffer. It is bi-directional. . It stores all the request frame Bytes to be

transmitted to the PICC, and all the received Bytes sent by the PICC on the answer frame.

● The transmitter. It powers the PICCs by generating a 13.56MHz signal on an external

antenna. The resulting field is 10% modulated using ASK (amplitude shift keying) for outgoing data.

● The receiver. It demodulates the signal generated on the antenna by the load variation

of the PICC. The resulting signal is decoded by a 847kHz BPSK (binary phase shift keying) sub-carrier decoder.

The CR14 is designed to be connected to a digital host (Microcontroller or ASIC). This host

has to manage the entire communication protocol in both transmit and receive modes,

through the I²C serial bus.

6/47 Doc ID 11922 Rev 2

CR14 Summary description

ai12059

OUT

CR14

OSC1

SCL

SDA

E0 E1 E2

GND GND_RF

REF

Antenna

OSC2

Figure 1. Logic diagram

Table 1. Signal names

Signal Description

OUT

Antenna Output Driver

Antenna Input Filter

OSC1 Oscillator Input

OSC2 Oscillator Output

E0, E1, E2 Chip Enable Inputs

SDA I²C Bi-Directional Data

SCL I²C Clock

Power Supply

GND Ground

REF

Transmitter Reference Voltage

GND_RF Ground for RF circuitry

Doc ID 11922 Rev 2 7/47

Summary description CR14

AI12060

OUT

CR14

OSC1

SCL

SDA

E0 E1 E2

GND

GND_RF

REF

Antenna

TransmitterReceiver

I²C Bus Controller

RAM Buffer

OSC2

AI10911

2 3 4

16 15 14 13

GND

OSC2

OSC1

REF

GND_RFE0

SO16

5 6 7 8

12 11 10

SDAGND

SCL

GND_RF

GND

OUT

Figure 2. Logic block diagram

Figure 3. SO pin connections

8/47 Doc ID 11922 Rev 2

CR14 Signal description

2 Signal description

See Figure 1: Logic diagram, and Table 1: Signal names, for an overview of the signals

connected to this device.

2.1 Oscillator (OSC1, OSC2)

The OSC1 and OSC2 pins are internally connected to the on-chip oscillator circuit. The

OSC1 pin is the input pin, the OSC2 is the output pin. For correct operation of the CR14, it is

required to connect a 13.56MHz quartz crystal across OSC1 and OSC2. If an external clock

is used, it must be connected to OSC1 and OSC2 must be left open.

2.2 Antenna output driver (RF

The Antenna Output Driver pin, RF

antenna. Care must be taken as it will not withstand a short-circuit.

schematic The LRC antenna circuitry must be connected across the RF

has to be connected to the antenna circuitry as shown in Figure 4: CR14 application

OUT

)

OUT

, generates the modulated 13.56MHz signal on the

2.3 Antenna input filter (RFIN)

The antenna input filter of the CR14, RFIN, has to be connected to the external antenna

through an adapter circuit, as shown in Figure 4.

The input filter demodulates the signal generated on the antenna by the load variation of the

PICC. The resulting signal is then decoded by the 847kHz BPSK decoder.

2.4 Transmitter reference voltage (V

The Transmitter Reference Voltage input, V

output driver for ASK modulation.

The Transmitter Reference Voltage input should be connected to an external capacitor, as

shown in Figure 4.

REF

pin and GND.

OUT

)

REF

, provides a reference voltage used by the

2.5 Serial clock (SCL)

The SCL input pin is used to strobe all I²C data in and out of the CR14. In applications

where this line is used by slave devices to synchronize the bus to a slower clock, the master

must have an open drain output, and a pull-up resistor must be connected from the Serial

Clock (SCL) to V

calculated).

In most applications, though, this method of synchronization is not employed, and so the

pull-up resistor is not necessary, provided that the master has a push-pull (rather than open

drain) output.

. (Figure 5 indicates how the value of the pull-up resistor can be

Doc ID 11922 Rev 2 9/47

Signal description CR14

REF

GND_RF

GND

SDA

SCL

GND

OSC2

OSC1

GND_RF

OUT

CR14

13.56MHz

C1 7pF50V

C2 7pF50V

22nF50V

100pF50V

C8'

8pF50V

C7 120pF50V

C7' 33pF50V

100nF50V

C4 22uF 10V

FL4

FL5

FL6

FL7

WURTH 742-792-042

OPT

ANT1

ANT2

SCL SDA

OPT

D1 1N4148 (OPTIONAL)

C5 10pF50V

AI12061

2.6 Serial data (SDA)

The SDA signal is bi-directional. It is used to transfer I²C data in and out of the CR14. It is an

open drain output that may be wire-OR’ed with other open drain or open collector signals on

the bus. A pull-up resistor must be connected from Serial data (SDA) to V

. (Figure 5

indicates how the value of the pull-up resistor can be calculated).

2.7 Chip enable (E0, E1, E2)

The Chip Enable inputs E0, E1, E2 are used to set and reset the value on the three least

significant bits (b3, b2, b1) of the 7-bit I²C Device Select Code. They are used for hardwired

addressing, allowing up to eight CR14 devices to be addressed on the same I²C bus. These

inputs may be driven dynamically or tied to V

(note that the V

and VIH levels for the inputs are CMOS compatible, not TTL compatible).

or GND to establish the Device Select Code

When left open, E0, E1 and E2 are internally read at the logic level 0 due to the internal pull-

down resistors connected to each inputs.

2.8 Power supply (VCC, GND, GND_RF)

Power is supplied to the CR14 using the VCC, GND and GND_RF pins.

is the Power Supply pin that supplies the power (+5V) for all CR14 operations.

The GND and GND_RF pins are ground connections. They must be connected together.

Decoupling capacitors should be connected between the V

Supply Voltage pin, the GND

Ground pin and the GND_REF Ground pin to filter the power line, as shown in Figure 4.

Figure 4. CR14 application schematic

10/47 Doc ID 11922 Rev 2

1 2 3 4 5 6 7 8

4 3 2 1

16 15 14 13

11 10 9

CR14 Signal description

AI01665

BUS

SDA

MASTER

SCL

BUS

100

BUS

(pF)

Maximum RP value (kΩ)

1000

fc = 400kHz

fc = 100kHz

Figure 5. Maximum RL value versus bus capacitance (C

) for an I²C bus

BUS

Doc ID 11922 Rev 2 11/47

CR14 registers CR14

3 CR14 registers

The CR14 chip coupler contains six volatile registers. It is entirely controlled, at both digital

and analog level, using the three registers listed below and shown in Ta bl e 2 :

● Parameter Register

● Input/Output Frame Register

● Slot Marker Register

The other 3 registers are located at addresses 02h, 04h and 05h. They are “ST Reserved”,

and must not be used in end-user applications.

In the I²C protocol, all data Bytes are transmitted Most Significant Byte first, with each Byte

transmitted Most significant bit first.

Table 2. CR14 control registers

Address Length Access Purpose

00h Parameter Register 1 Byte

01h Input/output Frame Register 36 Bytes

02h ST Reserved NA

03h Slot Marker Register 1 Byte

04h ST Reserved NA R and W ST Reserved. Must not be used

05h ST Reserved NA R and W ST Reserved. Must not be used

W Set parameter register

R Read parameter register

R Transfer PICC answered frame data to Host

R Return data FFh

Store and send request frame to the PICC. Wait for PICC answer frame

ST Reserved, must not be used.

Launch the automated anti-collision process from Slot_0 to Slot_15

3.1 Parameter register (00h)

The Parameter Register is an 8-bit volatile register used to configure the CR14, and thus, to

customize the circuit behavior. The Parameter Register is located at the I²C address 00h

and it is accessible in I²C Read and Write modes. Its default value, 00h, puts the CR14 in

standard ISO14443 type-B configuration.

Table 3. Parameter register bits description

Bit Control Value Description

Frame Standard

RFU 0 Not used

12/47 Doc ID 11922 Rev 2

0 ISO14443 type-B frame management

RFU

(1)

CR14 CR14 registers

Table 3. Parameter register bits description (continued)

Bit Control Value Description

0 Answer PICC Frames are delimited by SOF and EOF

Answer Frame Format

ASK Modulation Depth

Carrier Frequency

0 10% ASK modulation depth mode

1RFU

0 13.56MHz carrier on RF OUT is OFF

1 13.56MHz carrier on RF OUT is ON

Answer PICC Frames do not provide SOF and EOF delimiters

WDG

Answer delay watchdog

RFU 0 Not used

1. RFU = Reserved for Future Use.

b5=0, b6=0: Watchdog time-out = 500µs to be used for read b5=0, b6=1: Watchdog time-out = 5ms to be used for read b5=1, b6=0: Watchdog time-out = 10ms to be used for write b5=1, b6=1: Watchdog time-out = 309ms to be used for MCU timings

3.2 Input/Output Frame Register (01h)

The Input/Output Frame Register is a 36-Byte buffer that is accessed serially from Byte 0

through to Byte 35 (see Ta b l e 4 ). It is located at the I²C address 01h.

The Input/Output Frame Register is the buffer in which the CR14 stores the data Bytes of

the request frame to be sent to the PICC. It automatically stores the data Bytes of the

answer frame received from the PICC. The first Byte (Byte 0) of the Input/Output Frame

When accessed in I²C Write mode , the register stores the request frame Bytes that are to

be transmitted to the PICC. Byte 0 must be set with the request frame length (in Bytes) and

the frame is stored from Byte 1 onwards. At the end of the transmission, the 16-bit CRC is

automatically added. After the transmission, the CR14 wait for the PICC to send back an

answer frame. When correctly decoded, the PICC answer frame Bytes are stored in the

Input/Output Frame Register from Byte 1 onwards. Byte 0 stores the number of Bytes

received from the PICC.

When accessed in I²C Read mode, the Input/Output Register sends back the last PICC

answer frame Bytes, if any, with Byte 0 transmitted first. The 16-bit CRC is not stored, and it

is not sent back on the I²C bus.

The Input/Output Frame Register is set to all 00h between transmission and reception. If

there is no answer from the PICC, Byte 0 is set to 00h. In the case of a CRC error, Byte 0 is

set to FFh, and the data Bytes are discarded and not appended in the register.

The CR14 Input/Output Frame Register is so designed as to generate all the ST short range

memory command frames. It can also generate all standardized ISO14443 type-B

command frames like REQB, SLOT-MARKER, ATTRIB, HALT, and get all the answers like

ATQB, or answer to ATTRIB. All ISO14443 type-B compliant PICCs can be accessed by the

CR14 provided that their data frame exchange is not longer than 35 Bytes in both request

and answer.

Doc ID 11922 Rev 2 13/47

CR14 registers CR14

Table 4. Input/output frame register description

Byte 0 Byte 1 Byte 2 Byte 3 ... Byte 34 Byte 35

Frame Length First data Byte Second data Byte Last data Byte

00h No Byte transmitted FFh CRC Error

xxh Number of transmitted Bytes

<------------- Request and Answer Frame Bytes exchanged on the RF ------------->

3.3 Slot marker register (03h)

The slot Marker Register is located at the I²C address 03h. It is used to trigger an automated

anti-collision sequence between the CR14 and any ST short range memory present in the

electromagnetic field. With one I²C access, the CR14 launches a complete stream of

commands starting from PCALL16(), SLOT_MARKER(1), SLOT_MARKER(2) up to

SLOT_MARKER(15), and stores all the identified Chip_IDs into the Input/Output Frame

This automated anti-collision sequence simplifies the host software development and

reduces the time needed to interrogate the 16 slots of the STMicroelectronics anti-collision

mechanism.

When accessed in I²C Write mode, the Slot Marker Register starts generating the sequence

of anti-collision commands. After each command, the CR14 wait for the ST short range

memory answer frame which contains the Chip_ID. The validity of the answer is checked

and stored into the corresponding Status Slot Bit (Byte 1 and Byte 2 as described in

Ta bl e 5 ). If the answer is correct, the Status Slot Bit is set to ‘1’ and the Chip_ID is stored

into the corresponding Slot_Register. If no answer is detected, the Status Slot Bit is set to

‘0’, and the corresponding Slot_Register is set to 00h. If a CRC error is detected, the Status

Slot Bit is set to ‘0’, and the corresponding Slot_Register is set to FFh.

Each time the Slot Marker Register is accessed in I²C Write mode, Byte 0 of the

Input/Output Frame Register is set to 18, Bytes 1 and 2 provide Status Bits Slot information,

and Bytes 3 to 18 store the corresponding Chip_ID or error code.

The Slot Marker Register cannot be accessed in I²C Read mode. All the anti-collision data

can be accessed by reading the Input/Output Frame Register at the I²C address 01h.

Table 5. Slot marker register description

Byte 0 Number of stored Bytes: fixed to 18

Byte 1

Byte 2

Byte 3 Slot_Register 0 = Chip_ID value detected in Slot 0

Byte 4 Slot_Register 1 = Chip_ID value detected in Slot 1

Byte 5 Slot_Register 2 = Chip_ID value detected in Slot 2

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Status Slot

Bit 7

Status Slot

Bit 15

Status Slot

Bit 6

Status Slot

Bit 14

Status Slot

Bit 5

Status Slot

Bit 13

Status Slot

Bit 4

Status Slot

Bit 12

Status Slot

Bit 3

Status Slot

Bit 11

Status Slot

Bit 10

Bit 2

Status Slot

Bit 1

Status Slot

Bit 9

Status Slot

Bit 0

Status Slot

Bit 8

CR14 CR14 registers

Table 5. Slot marker register description (continued)

Byte 6 Slot_Register 3 = Chip_ID value detected in Slot 3

Byte n .....

Byte 17 Slot_Register 14 = Chip_ID value detected in Slot 14

Byte 18 Slot_Register 15 = Chip_ID value detected in Slot 15

Status bit value description: 1: No error detected. The Chip_ID stored in the Slot register is valid. 0: Error detected – Slot register = 00h: No answer frame detected from ST short range memory – Slot register = FFh: Answer Frame detected with CRC error. Collision may have occurred

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