ST AN977 Application note
AN977
APPLICATION NOTE
GUIDELINES FOR UPGRADING FROM THE ST92F120
(0.50 µm) TO THE ST92F124/F150/F250 (0.35 µm)
by Microcontroller Division Applications
INTRODUCTION
Microcontroll ers for emb edd ed app licat ions tend to int egra te mo re a nd mo re p eriphe ral s as
well as larger memories. Providing the right products with the right features such as Flash, emulated EEPROM and a wide range of peripherals at the right cost is always a challenge. That
is why it is mandatory to shrink the microcontroll er die size regularly as soon as the technology
will allow it. This major step applies to the ST92F120.
The purpose of this document is to present the differences between the ST92F120 microcontroller in 0.50 micron technology versus the ST92F124/F150/F250 in 0.35 micron technology.
It provides some guidelines for upgrading applications for both its software and hardware aspects.
In the first part of this document, the differences between the ST92F120 and ST92F124/F150/
F250 devices are listed. In the second part, the modifications required for the application hardware and software are described.
AN977/0203 1/17
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GUIDELINES FOR UPGRADING FRO M THE ST92F120 (0.50 µm) TO TH E ST92F124...
1 UPGRADING FROM THE ST92F120 TO THE ST92F124/F150/F 250
ST92F124/F150/F250 microcontrollers using 0.35 micron technology are similar to ST92F120
microcon trollers using 0.50 mi cron tec hnolo gy, but s hrinki ng is used to add s ome ne w features and to improve th e p erforma nce s of ST 92F1 24/F15 0/F 250 d evic es. A lm ost a ll p eripherals keep the same features, which is why this document focuses only on the modified sections. If there is no difference between the 0.50 micron peripheral compared to the 0.35 one,
other than its technology and design methodology, the peripheral is not presented. The new
analog to digital converter (ADC) is the m ajor change. This ADC uses a single 16 channel A/
D converter with 10 bits resolution instead of two 8-channel A/D converters with 8-bit resolution. The new memory organization, ne w rese t and clock control unit, internal voltage regulators and new I/O buffers will almost be transparent changes for the application. The new peripherals are the Controller Area Network (CAN) and the asynchronous Serial Communication
Interface (SCI-A).
1.1 PINOUT
The ST92F124/F150/F250 was designed in order to be able to replace the ST92F120. Thus,
pinouts are nearly the same. The few differences are described below:
– Clock2 was remapped from port P9.6 to P4.1
– Analog input channels were remapped according to the table below.
Table 1. Analog Input Channel Mapping
PIN ST92F120 Pinout ST92F124/F150/F250 Pinout
P8.7 A1IN0 AIN7
... ... ...
P8.0 A1IN7 AIN0
P7.7 A0IN7 AIN15
... ... ...
P7.0 A0IN0 AIN8
– RXCLK1(P9.3), TXCLK1/ CLKOUT1 (P9.2), DCD1 (P9.3), RTS1 (P9.5) were removed be-
cause SCI1 was replaced by SCI-A.
– A21(P9.7) down to A16 (P9.2) were added in order to be able to address up to 22 bits exter-
nally.
– 2 new CAN peripheral devices are available: TX0 and RX0 (CAN0) on ports P5.0 and P5.1
and TX1 and RX1 (CAN1) on dedicated pins.
1.2 RW
Under Reset state, RW
RESET STATE
is held high with an internal weak pull-up wher eas it was not on the
ST92F120.
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GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
1.3 SCHMITT TRIGGERS
– I/O ports with Special Schmitt Triggers are no longer present on the ST92F124/F150/F250
but are replaced by I/O ports with High Hysteresis Schmitt Triggers. The related I/O pins are:
P6[5-4].
– Differences on the VIL and VIH. See Table 2.
Table 2. Input Level Schmitt Trigger DC Electrical Characteristics
(VDD = 5 V ± 10%, TA = –40° C to +125° C, unless otherwise specified)
Symbol Parameter Device
ST92F120 0.7 x V
ST92F124/F150/F250 0.6 x V
ST92F120 0.8 V
ST92F124/F150/F250 0.2 x V
ST92F120 0.3 x V
ST92F124/F150/F250 0.25 x V
ST92F120 600 mV
ST92F124/F150/F250 250 mV
ST92F120 800 mV
ST92F124/F150/F250 1000 mV
ST92F120 900 mV
ST92F124/F150/F250 1000 mV
V
V
V
HYS
Input High Level
Standard Schmitt Trigger
P2[5:4]-P2[1:0]-P3[7:4]-P3[2:0]-
IH
P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]P9[7:0]
Input Low Level
Standard Schmitt Trigger
P2[5:4]-P2[1:0]-P3[7:4] P3[2:0]P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]-
IL
P9[7:0]
Input Low Level
High Hyst.Schmitt Trigger
P4[7:6]-P6[5:4]
Input Hysteresis
Standard Schmitt Trigger
P2[5:4]-P2[1:0]-P3[7:4]-P3[2:0]-
P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]P9[7:0]
Input Hysteresis
High Hyst. Schmitt Trigger
P4[7:6]
Input Hysteresis
High Hyst. Schmitt Trigger
P6[5:4]
Value
Min Typ
DD
DD
(1)
Max
DD
DD
DD
Unit
V
V
V
V
V
(1)
Unless otherwise stated, typical data are based on TA= 25°C and VDD= 5V. They are only reported
for design guide lines not tested in production.
1.4 MEMORY ORGANIZATION
1.4.1 External memory
On the ST92F120, only 16 bits were externally available. Now, on the ST92F124/F150/F250
device, the 22 b its o f th e MM U are exter nally avai lable. This o rgani zation is used to mak e it
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GUIDELINES FOR UPGRADING FRO M THE ST92F120 (0.50 µm) TO TH E ST92F124...
easier to address up to 4 external Mbytes. But segments 0h to 3h and 20h to 23h are not externally available.
1.4.2 Flash Sector Organization
Sectors F 0 to F3 ha ve a ne w organi zatio n in the 12 8K and 60K Fl ash dev ices as s hown in
Table 5 and Table 6. Table 3. and Table 4 show the previous organization.
Table 3. Memory Structure for 128K Fla sh ST92F120 Flash Device
Sector Addresses Max Size
TestFlash (TF) (Reserved) 230000h to 231F7Fh 8064 bytes
OTP Area
Protection Registers (reserved)
Flash 0 (F0) 000000h to 00FFFFh 64 Kbytes
Flash 1 (F1) 010000h to 01BFFFh 48 Kbytes
Flash 2 (F2) 01C000h to 01DFFFh 8 Kbytes
Flash 3 (F3) 01E000h to 01FFFFh 8 Kbytes
EEPROM 0 (E0) 228000h to 228FFFh 4 Kbytes
EEPROM 1 (E1) 22C000h to 22CFFFh 4 Kbytes
Emulated EEPROM 220000h to 2203FFh 1 Kbyte
231F80h to 231FFBh
231FFCh to 231FFFh
124 bytes
4 bytes
Table 4. Memory Structure for 60K Flas h ST92F120 Flash Device
Sector Addresses Max Size
TestFlash (TF) (Reserved) 230000h to 231F7Fh 8064 bytes
OTP Area
Protection Registers (reserved)
Flash 0 (F0) 000000h to 000FFFh 4 Kbytes
Reserved 001000h to 00FFFFh 60 Kbytes
Flash 1 (F1) 010000h to 01BFFFh 48 Kbytes
Flash 2 (F2) 01C000h to 01DFFFh 8 Kbytes
EEPROM 0 (E0) 228000h to 228FFFh 4 Kbytes
EEPROM 1 (E1) 22C000h to 22CFFFh 4 Kbytes
Emulated EEPROM 220000h to 2203FFh 1Kbyte
231F80h to 231FFBh
231FFCh to 231FFFh
Table 5. Memory Structure for 128K ST 92F124/F150/F250 Flash device
Sector Addresses Max Size
TestFlash (TF) (Reserved) 230000h to 231F7Fh 8064 bytes
OTP Area
Protection Registers (reserved)
Flash 0 (F0) 000000h to 001FFFh 8 Kbytes
Flash 1 (F1) 002000h to 003FFFh 8 Kbytes
Flash 2 (F2) 004000h to 00FFFFh 48 Kbytes
Flash 3 (F3) 010000h to 01FFFFh 64 Kbytes
231F80h to 231FFBh
231FFCh to 231FFFh
124 bytes
4 bytes
124 bytes
4 bytes
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GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...
Sector Addresses Max Size
Hardware Emulated EEPROM sec-
tors
(reserved)
Emulated EEPROM 220000h to 2203FFh 1 Kbyte
228000h to 22CFFFh 8 Kbytes
Table 6. Memory Structure for 64K ST 92F124/F150/F250 Flash device
Sector Addresses Max Size
TestFlash (TF) (Reserved) 230000h to 231F7Fh 8064 bytes
OTP Area
Protection Registers (reserved)
Flash 0 (F0) 000000h to 001FFFh 8 Kbytes
Flash 1 (F1) 002000h to 003FFFh 8 Kbytes
Flash 2 (F2) 004000h to 00BFFFh 32 Kbytes
Flash 3 (F3) 010000h to 013FFFh 16 Kbytes
Hardware Emulated EEPROM sec-
tors
(reserved)
Emulated EEPROM 220000h to 2203FFh 1 Kbyte
231F80h to 231FFBh
231FFCh to 231FFFh
228000h to 22CFFFh 8 Kbytes
124 bytes
4 bytes
Since the user reset vector location is set at address 0x000000, the application can use sector
F0 as an 8-Kbyte user bootloader area, or sectors F0 and F1 as a 16-Kbyte area.
1.4.3 Flash & E
In order to save a data po inter register (DPR), the Flash and E
control registers are remapped from page 0x89 to page 0x88 where the E
cated. Thi s way, only one DPR is us ed to poi nt to both the E
2
E
PROM control registers. But the registers are still accessible at the previous address. The
3
PROM Control Register Location
3
PROM (Emulated E2PROM)
3
PROM area is lo-
3
PROM variabl es and Flas h &
new register addresses are:
– FCR 0x221000 & 0x224000
– ECR 0x221001 & 0x224001
– FESR0 0x221002 & 0x224002
– FESR1 0x221003 & 0x224003
In the application, these register locations are usually defined in the linker script file.
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GUIDELINES FOR UPGRADING FRO M THE ST92F120 (0.50 µm) TO TH E ST92F124...
Fi
ST92F120 I
ill
Fi
ST92F124/F150/F250 I
ill
1.5 RESET AND CLOC K CONTROL UNIT (RCCU)
1.5.1 Oscillator
A new low power oscillator is implemented with the following target specifications:
– Max. 200 µamp. consumption in Running mode,
– 0 amp. in Halt mode,
gure 1.
OSCOUT
OSCIN
nternal Osc
ator
HALT
CLOCK
BUFFER
REF
INPUT
gure 2.
R
POL
OSCIN
I
LOAD
nternal Osc
V
DD
ator
CLOCK1
VR02086A
OSCOUT
1.5.2 PLL
One bit (bit7 FREEN) has been added to the PLLCONF register (R246, page 55), this is to enable Fre e Runn ing mode . The r eset value for th is re gister is 0x0 7. Wh en th e FREE N b it is
reset, it has the same behaviour as in the ST92F120, meaning that the PLL is turned off when:
– entering stop mode,
– DX(2:0) = 111 in the PLLCONF register,
– entering low power modes (Wait For Interrupt or Low Power Wait for Interrupt) foll owing the
WFI instruction.
When the FREEN bit is set and any of the conditions listed above occur, the PLL enters Free
Running mode, and oscillates at a low frequency which is typically about 50 kHz.
In addition, when the PLL provides the internal clock, if the clock signal disappears (for instance du e to a bro ken or disc onnect ed res onat or...), a s afety c loc k sig nal is au tomat icall y
provided, allowing the ST9 to perform some rescue operations.
The frequency of this clock signal depends on the DX[0..2] bits of the PLLC ONF register
(R246, page55).
Refer to the ST92F124/F150/F250 datasheet for more details.
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