ST AN977 Application note

AN977

APPLICATION NOTE

GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124/F150/F250 (0.35 µm)

by Microcontroller Division Applications

INTRODUCTION

Microcontrollers for embedded applications tend to integrate more and more peripherals as well as larger memories. Providing the right products with the right features such as Flash, emulated EEPROM and a wide range of peripherals at the right cost is always a challenge. That is why it is mandatory to shrink the microcontroller die size regularly as soon as the technology will allow it. This major step applies to the ST92F120.

The purpose of this document is to present the differences between the ST92F120 microcontroller in 0.50 micron technology versus the ST92F124/F150/F250 in 0.35 micron technology. It provides some guidelines for upgrading applications for both its software and hardware aspects.

In the first part of this document, the differences between the ST92F120 and ST92F124/F150/ F250 devices are listed. In the second part, the modifications required for the application hardware and software are described.

AN977/0203

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1 UPGRADING FROM THE ST92F120 TO THE ST92F124/F150/F250

ST92F124/F150/F250 microcontrollers using 0.35 micron technology are similar to ST92F120 microcontrollers using 0.50 micron technology, but shrinking is used to add some new features and to improve the performances of ST92F124/F150/F250 devices. Almost all peripherals keep the same features, which is why this document focuses only on the modified sections. If there is no difference between the 0.50 micron peripheral compared to the 0.35 one, other than its technology and design methodology, the peripheral is not presented. The new analog to digital converter (ADC) is the major change. This ADC uses a single 16 channel A/ D converter with 10 bits resolution instead of two 8-channel A/D converters with 8-bit resolution. The new memory organization, new reset and clock control unit, internal voltage regulators and new I/O buffers will almost be transparent changes for the application. The new peripherals are the Controller Area Network (CAN) and the asynchronous Serial Communication Interface (SCI-A).

1.1 PINOUT

The ST92F124/F150/F250 was designed in order to be able to replace the ST92F120. Thus, pinouts are nearly the same. The few differences are described below:

–Clock2 was remapped from port P9.6 to P4.1

–Analog input channels were remapped according to the table below.

Table 1. Analog Input Channel Mapping

PIN	ST92F120 Pinout	ST92F124/F150/F250 Pinout
P8.7	A1IN0	AIN7
...	...	...
P8.0	A1IN7	AIN0
P7.7	A0IN7	AIN15
...	...	...
P7.0	A0IN0	AIN8

–RXCLK1(P9.3), TXCLK1/ CLKOUT1 (P9.2), DCD1 (P9.3), RTS1 (P9.5) were removed because SCI1 was replaced by SCI-A.

–A21(P9.7) down to A16 (P9.2) were added in order to be able to address up to 22 bits externally.

–2 new CAN peripheral devices are available: TX0 and RX0 (CAN0) on ports P5.0 and P5.1 and TX1 and RX1 (CAN1) on dedicated pins.

1.2 RW RESET STATE

Under Reset state, RW is held high with an internal weak pull-up whereas it was not on the ST92F120.

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1.3 SCHMITT TRIGGERS

–I/O ports with Special Schmitt Triggers are no longer present on the ST92F124/F150/F250 but are replaced by I/O ports with High Hysteresis Schmitt Triggers. The related I/O pins are: P6[5-4].

–Differences on the VIL and VIH. See Table 2.

Table 2. Input Level Schmitt Trigger DC Electrical Characteristics

(VDD = 5 V ± 10%, TA = –40° C to +125° C, unless otherwise specified)

	Symbol	Parameter	Device		Value		Unit
				Min	Typ(1)	Max
		Input High Level	ST92F120	0.7 x VDD			V
		Standard Schmitt Trigger
	VIH	P2[5:4]-P2[1:0]-P3[7:4]-P3[2:0]-
		P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]-	ST92F124/F150/F250	0.6 x VDD			V
		P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]-
		P9[7:0]
		Input Low Level	ST92F120			0.8	V
		Standard Schmitt Trigger
		P2[5:4]-P2[1:0]-P3[7:4] P3[2:0]-
		P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]-	ST92F124/F150/F250			0.2 x VDD	V
	VIL	P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]-
		P9[7:0]
		Input Low Level	ST92F120			0.3 x VDD	V
		High Hyst.Schmitt Trigger	ST92F124/F150/F250			0.25 x VDD	V
		P4[7:6]-P6[5:4]
		Input Hysteresis	ST92F120		600		mV
		Standard Schmitt Trigger
		P2[5:4]-P2[1:0]-P3[7:4]-P3[2:0]-
		P4[4:3]-P4[1:0]-P5[7:4]-P5[2:0]-	ST92F124/F150/F250		250		mV
		P6[3:0]-P6[7:6]-P7[7:0]-P8[7:0]-
	VHYS	P9[7:0]
		Input Hysteresis	ST92F120		800		mV
		High Hyst. Schmitt Trigger
			ST92F124/F150/F250		1000		mV
		P4[7:6]
		Input Hysteresis	ST92F120		900		mV
		High Hyst. Schmitt Trigger
			ST92F124/F150/F250		1000		mV
		P6[5:4]

(1)Unless otherwise stated, typical data are based on TA= 25°C and V DD= 5V. They are only reported for design guide lines not tested in production.

1.4 MEMORY ORGANIZATION

1.4.1 External memory

On the ST92F120, only 16 bits were externally available. Now, on the ST92F124/F150/F250 device, the 22 bits of the MMU are externally available. This organization is used to make it

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easier to address up to 4 external Mbytes. But segments 0h to 3h and 20h to 23h are not externally available.

1.4.2 Flash Sector Organization

Sectors F0 to F3 have a new organization in the 128K and 60K Flash devices as shown in Table 5 and Table 6. Table 3. and Table 4 show the previous organization.

Table 3. Memory Structure for 128K Flash ST92F120 Flash Device

Sector	Addresses	Max Size
TestFlash (TF) (Reserved)	230000h to 231F7Fh	8064 bytes
OTP Area	231F80h to 231FFBh	124 bytes
Protection Registers (reserved)	231FFCh to 231FFFh	4 bytes
Flash 0 (F0)	000000h to 00FFFFh	64 Kbytes
Flash 1 (F1)	010000h to 01BFFFh	48 Kbytes
Flash 2 (F2)	01C000h to 01DFFFh	8 Kbytes
Flash 3 (F3)	01E000h to 01FFFFh	8 Kbytes
EEPROM 0 (E0)	228000h to 228FFFh	4 Kbytes
EEPROM 1 (E1)	22C000h to 22CFFFh	4 Kbytes
Emulated EEPROM	220000h to 2203FFh	1 Kbyte
Table 4. Memory Structure for 60K Flash ST92F120 Flash Device

Sector	Addresses		Max Size
TestFlash (TF) (Reserved)	230000h to 231F7Fh		8064 bytes
OTP Area	231F80h to 231FFBh		124 bytes
Protection Registers (reserved)	231FFCh to 231FFFh		4 bytes
Flash 0 (F0)	000000h to 000FFFh		4 Kbytes
Reserved	001000h to 00FFFFh		60 Kbytes
Flash 1 (F1)	010000h to 01BFFFh		48 Kbytes
Flash 2 (F2)	01C000h to 01DFFFh		8 Kbytes
EEPROM 0 (E0)	228000h to 228FFFh		4 Kbytes
EEPROM 1 (E1)	22C000h to 22CFFFh		4 Kbytes
Emulated EEPROM	220000h to 2203FFh		1Kbyte
Table 5. Memory Structure for 128K ST92F124/F150/F250 Flash device

Sector	Addresses	Max Size
TestFlash (TF) (Reserved)	230000h to 231F7Fh	8064 bytes
OTP Area	231F80h to 231FFBh	124 bytes
Protection Registers (reserved)	231FFCh to 231FFFh	4 bytes
Flash 0 (F0)	000000h to 001FFFh	8 Kbytes
Flash 1 (F1)	002000h to 003FFFh	8 Kbytes
Flash 2 (F2)	004000h to 00FFFFh	48 Kbytes
Flash 3 (F3)	010000h to 01FFFFh	64 Kbytes

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Sector	Addresses	Max Size
Hardware Emulated EEPROM sec-
tors	228000h to 22CFFFh	8 Kbytes
(reserved)
Emulated EEPROM	220000h to 2203FFh	1 Kbyte

Table 6. Memory Structure for 64K ST92F124/F150/F250 Flash device

Sector	Addresses	Max Size
TestFlash (TF) (Reserved)	230000h to 231F7Fh	8064 bytes
OTP Area	231F80h to 231FFBh	124 bytes
Protection Registers (reserved)	231FFCh to 231FFFh	4 bytes
Flash 0 (F0)	000000h to 001FFFh	8 Kbytes
Flash 1 (F1)	002000h to 003FFFh	8 Kbytes
Flash 2 (F2)	004000h to 00BFFFh	32 Kbytes
Flash 3 (F3)	010000h to 013FFFh	16 Kbytes
Hardware Emulated EEPROM sec-
tors	228000h to 22CFFFh	8 Kbytes
(reserved)
Emulated EEPROM	220000h to 2203FFh	1 Kbyte

Since the user reset vector location is set at address 0x000000, the application can use sector F0 as an 8-Kbyte user bootloader area, or sectors F0 and F1 as a 16-Kbyte area.

1.4.3 Flash & E3PROM Control Register Location

In order to save a data pointer register (DPR), the Flash and E3PROM (Emulated E2PROM) control registers are remapped from page 0x89 to page 0x88 where the E3PROM area is located. This way, only one DPR is used to point to both the E3PROM variables and Flash & E2PROM control registers. But the registers are still accessible at the previous address. The new register addresses are:

– FCR	0x221000 & 0x224000
– ECR	0x221001 & 0x224001
– FESR0	0x221002 & 0x224002
– FESR1	0x221003 & 0x224003

In the application, these register locations are usually defined in the linker script file.

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1.5 RESET AND CLOCK CONTROL UNIT (RCCU)

1.5.1 Oscillator

A new low power oscillator is implemented with the following target specifications:

–Max. 200 µamp. consumption in Running mode,

–0 amp. in Halt mode,

Figure 1. ST92F120 Internal Oscillator

Figure 2. ST92F124/F150/F250 Internal Oscillator

	VDD
	HALT
	ILOAD
	REF
OSCOUT	CLOCK1
	RPOL
OSCIN	CLOCK
	INPUT
	BUFFER
	OSCIN
	VR02086A
	OSCOUT

1.5.2 PLL

One bit (bit7 FREEN) has been added to the PLLCONF register (R246, page 55), this is to enable Free Running mode. The reset value for this register is 0x07. When the FREEN bit is reset, it has the same behaviour as in the ST92F120, meaning that the PLL is turned off when:

–entering stop mode,

–DX(2:0) = 111 in the PLLCONF register,

–entering low power modes (Wait For Interrupt or Low Power Wait for Interrupt) following the WFI instruction.

When the FREEN bit is set and any of the conditions listed above occur, the PLL enters Free Running mode, and oscillates at a low frequency which is typically about 50 kHz.

In addition, when the PLL provides the internal clock, if the clock signal disappears (for instance due to a broken or disconnected resonator...), a safety clock signal is automatically provided, allowing the ST9 to perform some rescue operations.

The frequency of this clock signal depends on the DX[0..2] bits of the PLLCONF register (R246, page55).

Refer to the ST92F124/F150/F250 datasheet for more details.

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