ST AN970 Application note
AN970
APPLICATION NOTE
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
by 8-Bit Micro Application Team
INTRODUCTION
The goal of this application note is to present a practical example of communication using the
SPI peripheral of the ST7.
It shows an easy way of communicating between a ST7 microcontroller and a M95xxx SPI
EEPROM. The purpose is to perform, through SPI, a write in the m em ory, follow ed by a read
of the written data.
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1
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
1 ST7 / EEPROM SPI INTERFACE
This section summarizes the main features of the ST7/EEPROM SPI interface. Please refer to
the ST7 datasheet for more details.
The Serial Pe ripheral Int erface (S PI) allows full-duplex , synchr onous, se rial commu nicati on
between devices. A SPI system may consist of a master and several slaves, or of a system in
which devices may be either master or slave.
There is only one master at any one time.
The Bus signals are:
- The s erial cloc k (SCK).
- The MOSI (Master Out Slave In).
- The MISO (Master In Slave Out).
One more pin, the SS
pin (slave select), is needed to select the slave or the master mode for
each device. this can be done in hardware or software mode.
In this application the ST7 is always used as master (SS
pin = high level) and configures the
EEPROM mode through an output. The ST7 and SPI interface set-up is shown Figu re 1.
During SPI transfer, data is simultaneously transmitted (shifted out serially) and received
(shifted in serially). Data are transmitted MSB first. The serial clock is used to synchronize the
data transfer during a sequence of eight clock pulses.
Figure 1. ST7 and SPI Interface Set-Up
EEPROM
ST7
SPI Interface
I/O
SCK
MOSI
MISO
SS
VCC
S
C
D
Q
M95040
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SPI COMMU NICATION BETWEEN ST7 AND EEPR OM
2 ST72264 CONFIGURATION
2.1 I/O CONTROL
Four pins of the ST72264 are used:
- The 3 data and clock SPI pins (SCK, MOSI, MISO ).
- An output pin to select and deselect the M95xxx.
pin to select master or slave mode.
- SS
In our application, the output for selecting the M95xxx is pin 3 of Port B. It is configured as
output push-pull (refer to the datasheet for details).
2.2 SPI PERIPHERAL
2.2.1 General
This peripheral is configured with the SPI Control Register.
70
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
The output must be enabled (SPE = 1).
If the SS
pin is high (s ee SP ICSR) , the ST 722 64 can be declar ed as m aste r by sett ing the
MSTR bit.
The transmission speed, in master mode, is selected using the SPR0, SPR1 and SPR2 bi ts.
The CPOL and CPHA bits define the timing characteristics.
When the SPIE bit is set, SPI interrupts are enabled (not used in our case).
2.2.2 SS
The SS
software configuration
pin can be fixed by hardware, either connected to Vss (for a slave configuration) or to
Vdd (for a master configuration). But it can also be software driven through the SPICSR register (SSM and SSI bits) :
70
SPIF WCOL OVR MODF - SOD SSM SSI
To set the master configuration (as in our case) : SSM=1 and SSI=1
To set the slave configuration: SSM=1 and SSI=0
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