ST AN966 Application note

AN966

®

APPLICATION NOTE

L6561, ENHANCED TRANSITION MODE

POWER FACTO R CORR ECT O R

by Claudio Adragna

The TM (Transition Mode) technique is widely used for Power Factor Correction in low power appli­cations, such as lamp ballasts or low-end monitors. The L6561 is the latest ST’s proposal for this
market and the emerging ones that are supposed to require a low-cost Power Factor Correction.
Based on a well-established architecture, the L6561 offers excellent performance that enla rges its
field of application considerably.

Introduction

The front-end stage of conventional off -line converters, typically made up of a full wave rectifier bridge
with a capacitor filter, gets an unregulated DC bus from the AC mains. The filter capacitor must be large
enough to have a relat ively low ripple superimposed on the DC level. This means that the instantaneous
line voltage is below the voltage on the capacitor most of the time, thus the rectifiers conduct only for a
small portion of each line half-cycle. The current drawn from the mains is then a series of narrow pulses
whose amplitude is 5-10 times higher than the resulting DC value.

Lots of drawbacks result f r om that : much higher peak and RMS current drawn from the line, distortion of
the AC line voltage, overcurrents in the neutral line of the three-phase systems and, after all, a poor utili­sation of the power system’s energy capability.

This can be measured in terms of either harmonic contents, as norms EN61000-3-2 envisage, or Power
Factor (PF), intended as the rat io between the real power (the one transferred to the output) and the ap­parent power (RMS line voltage times RMS line current) drawn from the mains, which is more immedi­ate. A traditional input stage with capacitive filter has a low PF (0.5-0.7) and high harmonic contents.

Figure 1. Internal Block Diagram of the L6561.

1

INV

V

VOLTAGE

REGULATOR

8

CC

20V

R2

2.1V

1.6V

6

GND

INTERNAL

SUPPLY 7V

R1

V

REF2

+

-

-

2.5V
+

OVER-VOLTAGE

DETECTION

UVLO

ZERO CURRENT

+

-

5

ZCD

DETECTOR

COMP MULT CS
23 4

MULTIPLIER

+-

RSQ

DISABLE

40K

5pF

DRIVER

STARTER

D97IN547D

V

CC

7

GD

March 2003

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AN966 APPLICATION NOTE

By using switching techniques, a Power Factor Corrector (PFC) preregulator, located between the recti­fier bridge and the filter capacitor, allows drawing from the mains a quasi-sinusoidal current, in-phase
with the line voltage. The PF becomes very close to 1 (more than 0.99 is possible) and the aforesaid
drawbacks are eliminated.

Theoretically, any switching topology can be used to achieve a high PF but, in practice, the boost topol­ogy has become the most popular because of the advantages it offers:

1) mainly, the circuit requires the fewest external parts, thus it is the cheapest. Additionally:

2) the boost induct or located between the bridge and the switch causes the input di/dt t o be low, thus
minimizing the noise generated at the input and, therefore, the requirements on the input EMI filter;

3) the switch is source-grounded, therefore is easy to drive.

However, boost topology requires the DC output voltage to be higher than the maximum expected line
peak voltage (400VDC is a typical value for 220V or wide range mains applications). Besides, there is no
isolation between input and output, thus any line voltage surge will be passed on to the output.

Two methods of controlling a PFC preregulator are currently widely used: the fixed frequency average
current mode PWM and the Transition Mode (TM) PWM (fixed ON-time, variable frequency). The first
method needs a complex control that requires a sophisticated controller IC (ST’s L4981A, with the vari­ant of the frequency modulation of fered by the L4981B) and a consi derable component count. The sec­ond one requires a simpler control (implemented by ST’s L6561), much fewer external parts and is
therefore much less expensive.

With the first method the boost inductor works in continuous conduction mode, while TM makes the in­ductor work on the boundary between continuous and discontinuous mode, by definition. For a given
throughput power, TM operation then involves higher peak currents. This, also consistently with cost
considerations, suggests its use in a lower power range (typically below 150W), while t he former is rec­ommended for higher power levels.

L6561 PFC controller Integrated Circuit

The L6561, whose internal block diagram is shown in fig. 1, is an IC int ended to control PFC preregula­tors by using the Transition Mode technique. The device is available in Minidip and SO8 packages.

The most significant features of the L6561 concern the following points:
— undervoltage lockout with hysteresis;
— true micropower start-up current (50µA typ., 9 0µA guaranteed) for simple start-up circuits (just one re-

sistor) with very low power dissipation;
— internal reference with 1% precision guaranteed (@ Tj=25 °C);
— disable function to shut down the device and reduce its current consumption;
— two-level overvoltage protection;
— internal starter and Zero Current Detection circuit for TM operation;
— multiplier with extended dynamics for wide range mains applications, with excellent THD;
— on-chip RC filter on the current sense pin;
— high capability totem pole output for MOSFET or IGBT drive.
The IC is optimised for controlling PFC preregulators based on boost topology in elec tronic lamp bal-

lasts, AC-DC adapters and low power (<150 W) SMPS. However, its excellent performance along with
the extremely reduced external parts count allows also the use in unconventional topologies/applica­tions. Low power off-line AC-DC converters (using isolated flyback topology) with or without Power Fac­tor Correction are the most noticeable examples.

Device Blocks Description

SUPPLY BL O CK
As shown in fig. 1, a linear voltage regulator supplied by Vcc generates an internal 7V rail used to supply
the whole integrated circuit, except for the output s tage which is supplied directly from Vcc. In addition, a
bandgap circuit generates the precise internal reference (2.5V±1% @ 25°C) used by the control loop to
ensure a good regulation.
In fig.2 is shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the chip as
long as the Vcc voltage is high enough to ensure a reliable operation.

2/21

Figure 2. In ter na l Supply Block.

+Vi

REF.

AN966 APPLICATION NOTE

8

-

+

UVLO

D97IN673

ERROR AMPLIFIER AND OVERVOLTAGE DETECTOR BLOCK (see fig. 3 and 4):
The Error Amplifier (E/A) inverting input , through an external divider connected t o the output bus, com-

pares a partition of the boosted output DC voltage, Vo, with the internal reference, so as to maintain the
preregulator output DC voltage constant.

The E/A output is used for frequency compensation, usually realised with a feedback capacitor con­nected to the inverting input. The E/A bandwidth will be extremely low because the output of the E/A
must be constant over a line half-cycle to achieve high PF.

The dynamics of the E/A output is internally clamped so that it can swing between 2V and 5.8V in order
to speed up the recovery after the E/A saturates low due to an overvoltage or saturates high because of
an overcurrent.

The device is provided with a two-level overvoltage protection (OVP), realized by using the pin con­nected to the E/A output.

In case of overvoltage, the output of t he E/A will tend to saturate low but t he E/A response is very slow,
so it will take a long time to go into saturation. On the other hand, an overvoltage must be corrected im­mediately. Hence a fast OVP detector, based on a different concept, is necessary.

In steady state condition, the current through R1 is equal to the current in R2 because the compensation
capacitor does not allow DC current to flow (neither does the high-impedance inverting input of the E/A):

I

R1,R2

=

V

o

R1

=

2.5
R2

− 2.5

When the output voltage rises because of a step load change, the current in R1 builds up as well but the
current through R2, fixed by the internal 2.5V reference, does not because of the E/A slowness. The cur­rent in excess will then flow through the feedback capacitor and enter t he low-inpedance E/A output,
where it is sensed. In case, a two-step procedure can occur.

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AN966 APPLICATION NOTE

Figure 3. Error Amplifier and Overvoltage Detector Block.

Ccomp.

+Vo

R1

1

-

E/A

R2

D97IN591

2.5V

+

∆I

40µA

When the current in excess reaches about 37µA, the output voltage of the multiplier is forced to de­crease thus the energy drawn from the mains is reduced. This slows down the rate of rise of the output
voltage. In some cases, this "soft braking" action is able to prevent the output voltage from exceeding
the regulated value too much.

If the output voltage further increases despite the soft braking, so that the current entering the E/A
reaches 40µA, a "sharp braking" takes place. The output of the multiplier is pulled to ground, thus turn­ing off the output stage and the external MOSFET. Also the internal starter is switched off. The internal
current comparator is provided with hysteresis, t hus the pull-down will be released and the output stage
re-enabled as the current entering the E/A falls approximately below 10µA.

2.25V

∆I

2

X PWM

-

+

DRIVER

Figure 4. Dynamic and Static OVP operation.

V

OUT nominal

40µA
10µA

I

SC

E/A OUTPUT

2.25V

DYNAMIC OVP

STATIC OVP

OVER VOLTAGE

D97IN592A

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AN966 APPLICATION NOTE

This dynamic OVP, with its combination of soft and sharp braking, is effective to handle most of load
changes but does not provide a complete protection. In fact it is sensitive to output voltage v ariations
(whence the appellative "dynamic") and cannot reveal a steady overvoltage, which is likely to occur in
case of load disconnection.

The above mentioned concept of the E/A saturation is effective to achieve a "static" OVP. If the overvol­tage lasts so long that the output of E/A goes below 2.25V (the E/A is in linear dy namics up to 2.5V), the
protection is activated. Besides turning off the output s tage and t he external MOSFET, it disables some
internal blocks reducing the quiescent current of the chip to 1.4mA (typ). The operation of the device is
re-enabled as the E/A output goes back into its linear region.

Fig. 4 illustrates the combined action of dynamic and static OVP.

ZERO CURRENT DETECTION AND TRIGGERING BLOCK (see fig. 5)
The Zero Current Detection (ZCD) block switches on the external MOSFET as the voltage across the

boost inductor reverses, just after the current through the boost inductor has gone to zero. This feature
allows TM operation.

Figure 5. Zero Current Detection, Triggering and Disable Block.

+Vi

ZCD

5

DISABLE

200µA

-

++

5.7V

-

1.6V0.15V

STARTER

PWM

R
S

Q

DRIVER

D97IN674A

7

GD

As the circuit is running, the signal for ZCD is obtained with an auxiliary winding on the boost inductor.
Of course, a circuit is needed that turns on the external MOSFET at start-up since no signal is coming
from the ZCD. This is r ealized with an internal starter, which f orces the driver to deliver a pulse to the
gate of the MOSFET, producing also the signal for arming the ZCD circuit.

The repetition rate of the starter is greater than 70 µs (≅ 14 kHz) and this maximum frequency must be
taken into account at design time.

DISABLE BLOCK (see fig. 5)
The ZCD pin is used also to act ivate the Disable Block. I f the voltag e on the pin is taken below 150 mV

the device will be shut down. As a result, its current consumption will be reduced. To re-enable the de­vice operation, the pull-down on the pin must be released.

MULTIPLIER BLOCK (see fig. 6)
The multiplier has two inputs: the first one takes a partition of the instantaneous rectified line voltage and

the second one the output of the E/A. If this voltage is constant (over a given line half-cycle) the output
of the multiplier will be shaped as a rectified sinusoid too. This is the reference signal for the current
comparator, which sets the MOSFET peak current cycle by cycle.

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AN966 APPLICATION NOTE

Figure 6. Multiplier Block.

Rs

23

E/A

X

4

1.7V

-

CURR.CMP

+

D97IN675

CURRENT COMPARATOR AND PWM LATCH (see fig.7):
The current comparator senses the voltage across the current sense resistor (Rs) and, by comparing it

with the programming signal delivered by the multiplier, determines the exact time when the external
MOSFET is to be switched of f. The P WM latch avoids spurious switchings of the MOSFET which might
result from the noise generated.

The output of the multiplier is internally clamped to 1.7V, (typ.) thus current limiting oc curs if the voltage
across Rs reaches this value.

Figure 7. Current Comparator and PWM latch

Q

R

4

S

X

D97IN676

-

CMP

+

1.7V

R

Q

DRIVER

S

DRIVER (see fig.8)
A totem pole buffer, with 400mA source and sink capability, allows driving an external MOSFET. An in-

ternal pull-down circuit holds the output low when t he device is in UVLO conditions, to ensure that the
external MOSFET cannot be turned on accidentally.

6/21

Figure 8. Output Driver.

DRIVER

V

8

6

GND

CC

UVLO

AN966 APPLICATION NOTE

7

GD

D97IN677

Q

TM PFC Operation

(Boost Topology)

The operation of the PFC Transition Mode controlled boost convert er, can be summarized in the follow­ing description.

The AC mains voltage is rectified by a diode bridge and t he rectified voltage delivered to the boost con­verter. This, using a switching technique, boosts the rectified input v oltage t o a r egulated DC output volt­age (Vo).

The boost converter consists of a boost inductor (L), a controlled power switch (Q), a catch diode (D), an
output capacitor (Co) and, obviously, a control circuitry (see fig. 9).

The goal is to shape the input current in a sinusoidal fashion, in-phase with the input sinusoidal voltage.
To do this the L6561 uses the so-called Transition Mode technique.

Figure 9. Boost Converter Circuit.

L

D

~

I

L

~

C

in

I

Q

QCONTROLLER

I

D

I

C

D94IN119

I

O

C

O

LOAD

The error amplifier compares a partit ion of the output voltage of the boost converter with an internal ref­erence, generating a signal er ror propor tional to the difference between them. If the bandwidth of the er­ror amplifier is narrow enough (say, below 20 Hz), the error signal is a DC value over a given half-cycle.

The error signal is fed into the multiplier block and multiplied by a partition of the rectified mains voltage.
The result will be a rectified s inusoid whose peak amplitude depends on the mains peak volt age and the
value of the error signal.

The output of the multiplier is in turn fed into the (+) input of the current comparator, thus it represents a
sinusoidal reference for PWM. In fact, as the voltage on the current sense pin (istantaneous inductor
current times the sense resistor) equals the value on the (+) of the current comparator, the conduction of
the external MOSFET is terminated. As a consequence, the peak inductor current will be enveloped by a

7/21