ST AN937 Application note

AN937
Application Note
Designing with L4971, 1.5 A high efficiency DC-DC converter
Introduction
The L4971 is a 1.5 A monolithic dc-dc converter, step- down, operating at fix frequency continuous mode. It is designed in BCD60 II technology, and it is available in two plastic packages, DIP8 and SO16L.
The operating input supply voltage ranges from 8 V to 55 V, while the absolute value, with no load, is 60V. New internal design solutions and superior technology performance allow to generate a device with improved efficiency in all the operating conditions and with reduced EMI due to an innovative internal driving circuit, and reduced external component counts.
While internal limiting current and thermal shutdown are today considered standard protection functions, mandatory for a safe load supply, oscillator with voltage feed forward improves line regulation and overall control loop.
Soft-start avoids output over voltage at turn-on, while, shorting this pin to ground, the device is completely disabled, going into zero consumption state.

Figure 1. Demonstration board

May 2011 Doc ID 5655 Rev 15 1/29
www.st.com
Contents AN937
Contents
1 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Power supply, UVLO and voltage reference . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Oscillator and voltage feed forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Soft-start and inhibit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Output overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8 Turn - on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9 Turn - off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7 Error amplifier and compensation blocks . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8 LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9 PWM gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.10 Voltage divider and leading network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29 Doc ID 5655 Rev 15
AN937 Device description

1 Device description

For a better understanding of the device and it’s working principle, a short description of the main building blocks is given here below, with packaging options and complete block diagram.
Figure 2 show s the two packaging options, with the pin function assignments.

Figure 2. Pin Connections

GND
SS_INH
OSC
OUT
1
2
3
4 VCC
D97IN595
DIP8

Figure 3. Block diagram.

THERMAL
SHUTDOWN
COMP
2
INHIBIT SOFTSTART
7
8
FB
E/A
3.3V
OSCILLATOR
SS_INH
7
6
5
VOLTAGES
MONITOR
PWM
FB8
COMP
BOOT
3.3V
INTERNAL
REFERENCE
R
Q
S
N.C.
GND
SS_INH
OSC
OUT
OUT
N.C.
N.C. N.C.
2
3
4
5
6
7
8
D97IN596
16
15
14
13
12
11
10
9
SO16L
VCC
5
CBOOT
INTERNAL
SUPPLY
5.1V
DRIVE
CHARGE
CBOOT
CHARGE
AT LIGHT
LOADS
N.C.1
N.C.
FB
COMP
BOOT
VCC
N.C.
6
BOOT
3
OSC GND OUT
1
Doc ID 5655 Rev 15 3/29
4
D97IN594
Power supply, UVLO and voltage reference AN937

2 Power supply, UVLO and voltage reference

The device is provided with an internal stabilized power supply (of about 12 V typ.) that powers the analog and digital control blocks and the bootstrap section.
From this pre regulator, a 3.3V reference voltage ±2%, is internally available.

2.1 Oscillator and voltage feed forward

Just one pin is necessary to implement the oscillator function, with inherent voltage feedforward.

Figure 4. Oscillator internal circuit

V
CC
R
OSC
TO PWM
COMPARATOR
Osc
5R
-
+
CLOCK
Q
1
C
OSC
Q
2
R
1V
D97IN655A
A resistor Rosc and a capacitor Cosc connected as shown in Figure 4, allow the setting of the desired switching frequency in agreement with the below formula:
1
6
⎛⎞
---
⎝⎠
5
100 C
+
osc
dson
Where F
is in kHz, R
sw
osc
The oscillator capacitor, C
F
in kΩ and C
osc
-------------------------------------------------------------------------------------=
SW
()In
R
oascCosc
in nF.
osc
, is discharged by an internal MOS transistor of 100 Ω of R
(Q1) and during this period the internal threshold is set at 1 V by a second MOS, Q2. When the oscillator voltage capacitor reaches the 1V threshold the output comparator turn-off the MOS Q1 and turn-on the MOS Q2, restarting the C
charging.
osc
The oscillator block, shown in Figure 4, generates a sawtooth wave signal that sets the switching frequency of the system.
This signal, compared with the output of the error amplifier, generates the PWM signal that will modulate the conduction time of the power output stage.
The way the oscillator has been integrated, does not require additional external components to benefit of the voltage feed forward function.
4/29 Doc ID 5655 Rev 15
AN937 Power supply, UVLO and voltage reference
The oscillator peak-to-valley voltage is proportional to the supply voltage, and the voltage feed forward is operative from 8 V to 55 V of input supply.
VCC1
osc
--------------------=
6
ΔV
Also the ΔV/Δt of the sawtooth is directly proportional to the supply voltage. As Vcc increases, the Ton time of the power transistor decreases in such a way to provide to the choke, and finally also the load, the product Volt. sec constant.
Figure 6 show how the duty cycle varies as a result of the change on the ΔV/Δt of the
sawtooth with the Vcc. The output of the error amplifier doesn’t change to maintain the output voltage constant and in regulation. With this function on board, the output response time is greatly reduced in presence of an abrupt change on the supply voltage, and the output ripple voltage at the mains frequency is greatly reduced too.

Figure 5. Device switching frequency vs Rosc and Cosc

fsw
(KHz)
500
200
100
50
20
10
5
0 20 40 60 80 R2(KΩ)
0.82nF

Figure 6. Voltage feed forward function

V1
D97IN630
Tamb=25˚C
1.2nF
2.2nF
3.3nF
4.7nF
5.6nF
Vi=30V
Vi=15V
Vc
t
V2-3
Vi=30V
Vi=15V
t
D97IN684
Doc ID 5655 Rev 15 5/29
Power supply, UVLO and voltage reference AN937

Figure 7. Maximum duty cycle vs. Rosc and Cosc as parameter

D
max
0.90
0.80
0.70
0.60
5.3nF
4.7nF
2.2nF
1.2nF
0.8nF
0 4 8 121620242832R
D97IN685
OSC
(KΩ)
In fact, the slope of the ramp is modulated by the input ripple voltage, generally present in the order of some tents of Volt, for both off-line and dc-dc converters using mains transformers.
The charge and discharge time is approximately to:
6
⎛⎞
Tch R
In
oscCosc
---
=
⎝⎠
5
The maximum duty cycle is a function of Tch, Tdis and an internal delay and is represented by the equation:
and is represented in Figure 7:

2.2 Current protection

The L4971 has two current limit levels, pulse by pulse and hiccup modes.
Increasing the output current till the pulse by pulse limiting current threshold (Ith1 typ. value of 2.5 A) the controller reduces the on-time till the value of T time in which the current limit protection does not trigger. This minimum time is necessary to avoid undesirable intervention of the protection due to the spike current generated during the recovery time of the freewheeling diode.
Dmax
Tdis 100 C
R
oscCosc
----------------------------------------------------------------------------------=
R
oscCosc
In
=
In
⎛⎞ ⎝⎠
osc
6
⎛⎞
---
⎝⎠
5
6
---
5
80 109–⋅⋅⋅
100 C
+⋅⋅
osc
= 300 ns that is a blanking
B
6/29 Doc ID 5655 Rev 15
AN937 Power supply, UVLO and voltage reference
In this condition, because of this fixed blanking time, the output current is given by:
I
max
---------------------------------------------------------------------------------------------------------------------------------------------------=
R
O
VCCTBF
RDRL+()1TBFSW⋅()R
SWVf
1TBFSW⋅()⋅⋅[]
+()TBFSW⋅++[]
dsonRL
In Figure 8, the pulse by pulse protection is sufficient to limit the current.
In Figure 9 the pulse by pulse protection is no more effective to limit the current due to the minimum Ton fixed by the blanking time TB, and the hiccup protection intervenes because the output peak current reaches the relative threshold. At the pulse by pulse intervention (point A) the output voltage drops because of the Ton reduction, and the current is almost constant. Going versus the short circuit condition, the current is only limited by the series resistances RD and RL (see relation above) and could reach the hiccup threshold (point B), set 20% higher than the pulse by pulse. Once the hiccup limiting current is operating, in output short circuit condition, the delivered average output current decreases dramatically at very low values (point C).

Figure 8. Output characteristics

V
O
A
C
D98IN908A

Figure 9. Output characteristics

V
O
D97IN809
2.5A
A
2.5A
3A
3A
B
I
O
I
O
Doc ID 5655 Rev 15 7/29
Power supply, UVLO and voltage reference AN937

Figure 10. Current limiting internal schematic circuit

Q
S
OSC
R
V
Th1
+
-
V
Th2
+
-
V
CC
PWM
+-
OSC
VFB
THERMAL
+-
VREF
HICCUP
UNDERVOLTAGE
D97IN658

Figure 11. Output current and soft start voltage

5.4A
4.5A
SOFT START
LATCH
Q
S
R
+
-
OUT
12V
C
0.4
SS
Figure 10 shows the internal current limiting circuitry. Vth1 is the pulse by pulse while Vth2 is
the hiccup threshold.
The sense resistor is in series with a small MOS realized as a partition of the main DMOS.
The Vth2 comparator (20% higher than Vth1) sets the soft start latch, initializing the discharge of the soft start capacitor with a constant current (about 22 mA). Reaching about
0.4 V, the valley comparator resets the soft start latch, restarting a new recharge cycle.
Figure 11 shows the typical waveforms of the current in the output inductor and the soft start
voltage (pin 2).
During the recharging of the soft start capacitor, the Ton increases gradually and, if the short circuit is still present, when Ton>TB and the output peak current reaches the threshold, the hiccup protection intervenes again. So, the value of the soft start capacitor must not be too high (in this case the Ton increases slowly thus taking much time to reach the TB value) to avoid that during the soft start slope, the current exceeds the limit before the protection activation.
8/29 Doc ID 5655 Rev 15
AN937 Power supply, UVLO and voltage reference
The following diagrams of Figure 13 and Figure 14 show the maximum allowed soft-start capacitor as a function of the input voltage, inductor value and switching frequency. A minimum value of the soft start capacitance is necessary to guarantee, in short circuit condition, the functionality of the limiting current circuitry.
In fact, with a capacitor too small, the frequency of the current peaks (see Figure 11) is high and the mean current value in short circuit increases.
Example: for a maximum input voltage of 55 V at 100 kHz, with an inductor of 260 mH, it is possible to use a soft start capacitor lower than 470 µF. With such a value, the soft start time (see Figure 19) of about 10 ms for an output voltage of 5 V.
Figure 12. Maximum soft start capacitance with f
L
(μH)
fsw=100KHz
400
300
200
100
0
15 20 25 30 35 40 45 50 V
680nF
Figure 13. Maximum soft start capacitance with f
L
(μH)
300
200
fsw=200KHz
= 100 kHz
sw
D97IN745
470nF
330nF
220nF
100nF
CCmax
= 200 kHz
sw
D97IN746
56nF
47nF
33nF
(V)
22nF
100
0
15 20 25 30 35 40 45 50 VCCmax(V)
Doc ID 5655 Rev 15 9/29
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