ST AN925 Application note

AN925

Application note

Time update in ST’s TIMEKEEPER® devices

Introduction

Figure 1 shows how the non-volatile, static memory array and the quartz-controlled clock oscillator, of TIMEKEEPER® devices from STMicroelectronics, are interconnected through the clock registers. The clock registers are mapped into the memory array (please see the data sheet for the precise mapping) as 8 or 16 BYTEWIDE BIPORT memory cells. The time data in these memory cells are updated from the clock side (the system side) and are made available to the user side within the user’s finest time resolution.

However, the user’s finest time resolution is one second, so this leaves plenty of scope for variability (of the order of several milliseconds) between one update and the next. Since this variability might be noticeable to some applications (for example, those that poll the time registers regularly, or those that use an alarm function that is triggered once per second), this document sets out to explain the nature of the variability, to make it more predictable to the applications designer.

Figure 1. Internal architecture of an ST TIMEKEEPER® device

INTEGRATED BATTERY		WDI
CRYSTAL AND
SNAPHAT
OSCILLATOR AND			8, 16 x 8
CLOCK CHAIN
			TIMEKEEPER
32,768 Hz			REGISTERS
CRYSTAL
			POWER	A0-AX
			BATTERY LOW
			SRAM ARRAY	DQ0-DQ7
LITHIUM
CELL
VOLTAGE SENSE			VPFD	E
	AND			W
SWITCHING
	CIRCUITRY			G
VCC	IRQ/FT	RST	VSS	AI02482

July 2012

Doc ID 5228 Rev 2

1/5

www.st.com

AN925

A 1 Hz clock signal, from the clock chain, is used to update the seconds register. Each rising edge of the 1 Hz clock signal increments the system side of the seconds register. Having updated the seconds register, a ripple carry to other registers might be initiated (for example, incrementing the minutes register from 00 to 01, after the seconds register has been incremented from 59 to 00). The longest possible ripple carry extends through all seven registers: seconds, minutes, hours, day of the week, date of the month, month of the year and year.

Figure 2 shows two consecutive updates of the seconds register. The first update only updates the seconds register; the second update, though, ripples through all seven clock registers. When the system-side time registers have finished being updated, they are copied across to the user-side, thereby making the updated time available to the user. Thus, the spacing between successive System-to-User-Update-Pulse is one second plus a delta delay that can vary from 0.5 ms to 3.5 ms (1x0.5 ms to 7x0.5 ms). The older M48T58 (revision B), M48T59 (revision B), and M48T559 are examples of TIMEKEEPER® devices that operate in this way.

Figure 2. Time update waveform diagram (variable delay)

1 Hz clock frequency

Seconds register update

Minutes register update

Hours register update

Day of week register update

Date register update

Month register update

Year register update

Reference update pulse

1 second + 3.5ms

System to user update pulse

12/31/96 23:59:59 1/1/97 00:00:00 AI02483

2/5	Doc ID 5228 Rev 2