ST AN829 Application note

AN829

APPLICATION NOTE

SEMICONDUCTOR KIT FOR

POWER FACTOR CORRECTOR

by J.M. Borgeous

This paper present a new line of P.F.C. dedicated products. Both silicon and packaging have been op­timized to reduce system cost, including filtering. The products shown here are offered as a kit for power
factor correction.

BOOST CIRCUIT OPTIMIZATION PARAMETERS

Among the available topologies, a boost circuit operating in continuous current mode is the only topology which
enables the RFI noise across the input capacitor to be limited, and consequently a lower cost filter is required.
Also, the boost inductor stores only a part of the transferred energy, because the mains still supplies energy
during the demagnetization phase of the boost inductor - so the magnetic part required is smaller than needed
with any other topology. Therefore the boost topology leads to the cheapest solution. Figure 1 shows the general
topology of a boost PFC. Its optimization requires careful adjustment of the following parameters:

– the value of the input capacitor C
– the current ripple in the boost inductor L
– the parasitic capacitances of the boost inductor and power semiconductors, including those associ-

ated with the heatsink

– the operating frequency and also the frequency modulation techniqu e.

i

b

Figure 1. Sem ico nd uc tor Kit for PFC Sc he m ati c .

Lb

C1

STH80N05

89 10

ONE CHIP

L4981A/B

CONTROLLER

November 2003

any

compensation

7

6
13

4

1/KY

X

+-

14VREF

+

STE30NA50-DK

Lp3 Lp4

Lp1

Lp2

Lp5

FREQ. MODUL.(B)

SYNCHRON. (A)

5

+

-

FULL

PROTECTION

­+

A

+

20

1

D95IN252A

1/9

AN829 APPLICATION NO TE

SEMI-CONDUCTOR KIT

The semiconductor kit consist s of an L4981 controller, an S TE36N50-DK power module and an STH80N05
power sense (see figure 1).

L4981A/B controller:

The L4981 operates with an input voltage range of 85V to 270V and uses average current mode PW M control,
providing feed forward line and load compensation. Two versions are available: version (A) provides synchro­nization with the down stream converter, whereas version (B) provides linear frequency modulation, spreading
the RFI noise spectrum.

Both versions incorporate overvoltage and overcurrent protection, soft start and under voltage lockout with pro­grammable threshold.

Other features include an on chip voltage reference (2%) which is externally available, a typical starting current
of only 0.5mA and separate grounds for the power and signal stages.

L4981 use an optimum current control method. It is an average current control using feed forward line regulation
and variable or fixed switching frequency.

The oscillator simultaneously turns on the power switch and starts the ramp of the PWM current control. The
average inductor current is compared with the current reference by means of the current error amplifier. It op­erates as an integrator, allowing the circuit to accurately follow the current reference generated by the multiplier.
This current reference is obtained by sinewave modulating the error voltage of the voltage control loop.

A feed forward compensation of the mains voltage has been added to t he mult ipli er i n order t o keep constant
the voltage control loop bandwidth whatever the mains fluctuation. A fourth multiplier input allows external com­pensation to be applied to the current modulation.

The os cillator can operate at constant or modulated switching frequency. In applications where modulated fre­quency is used, the RFI noise spectrum can be spread adjusting the depth of modulation by means of an exter­nal resistor. Then the maximum inductor current occurs at the minimum operating frequency.

STE30NA50-DK Power Module:

Built in an isolated ISOTOPTM package, which can be m ounted directly on a PCB, this m odule integrates a low
R

DS(ON)

Power MOSFET and a TU RB O SWI TC H

TM

Diode. Putting these tw o components in a s i ngle i solat ed
package with very low parasitic inductance and capacitance reduces the component count, and significantly re­duces transient overvoltages, and EMI and RFI.

As a result, the design safety margin can be relaxed and the voltage rating of the power MOSFET can be just
500V

, meaning also that the R

(br)DSS

of the MOSFET can be l ower - in this case it is 0.14 Ohm. Both the

DS(on)

current and avalanche handling capabilities o f the po w er M O SF ET sec tio n a re s pe cif ied at 100° C junction tem­perature, allowing for maximum utilization of the device. The MOSFET is a low gate-charge type and so its drive
requirements are compatible with the 2A peak current capability of the L4981 controller.

The integrated TURBOSWITCH

TM

freewheeling diode is an ultra-fast, soft recovery device using planar epitax­ial technology, and is a part of the STTA series. Its low trr (30ns) keeps the MOSFET switching losses to a min­imum. Other ratings are 600V

and a maximum VF of 1.5V at the rated average forward current (I

RRM

Fav

= 20A).

STH80N05 Power sense:

Using a high density low voltage Power MOSFET for current sensing has many advantages:

– low resistance, typically 10m2

2/9

AN829 APPLICATION NOTE

– Can be mounted on the same heatsink as the ISOTOP
– intrinsic diode for controller input protection
– very low parasitic inductance improving signal/noise ratio.

However, the peak current limitation will be affected by the MOSFET thermal characteristic.

DESIGN RULE EXAMPLE
Taking the following operating conditions (see figure 2):
V

= 230Vac +10% -15% (f=50Hz)

in rms

I

= 16Arms

in rm s

P

= 3000W

out

V

= 400Vdc

out

or
V

= 120Vac +20% -20% (f=60Hz)

in rms

I

= 15Arms

in rm s

P

= 1400W

out

V

= 400Vdc

out

Figure 2. 1500W/3000W PFC Schematic.

J1

1

F1

D1

C1

1

J2

R16

+-

R71 R72

C72C71

R20

Dz

STH80N05

R4

IAC

VRMS

R73

S/FM

R2

IPK

2

4

7

16

Lb

+

-

R8 R9

MOUT

8

LFF VREF

R19

D2

Q1

VCC
19

611

TURBOSWITCH DIODE

ISOTOP

STE30NA50-DK

C19

R

CAOUT

20

GF

R

GN

D

GF

GDRV

C

P

R

Z

ISENSE

95

C

Z

L4981

C
C

SGNDPGND

1

10

14

13

3

1217 18

SSCCOSCROSC

C18R17 C12

O10

to

O14

1

1

VFEED

VAOUT

VP

J7

R141

R31

C

O2

to

C

O7

R142

R32

J8

R14

R13

C13

D95IN253A

3/9

AN829 APPLICATION NO TE

Component List

1 1 C1 10µF/250Vac
2 6 Co2,Co3,Co4,Co5,Co8,Co7 330µF/450V
3 5 Co10,Co11,Co12,Co13,Co14 0.33µF/450V
4 1 Cp tbd
5 1 Cz 150pF/100V
6 2 C12, C72 1µF/100V
7 1 C13 22nF/100V
8 1 C18 2.2nF/100V

9 1 C19 220µF/25V
10 1 C71 68nF/100V
11 1 DIODE TURBOSWITCH
12 1 DgF BYW100
13 1 D1 regular diode bridge or 2xMDS35
14 1 D2 4 x BYW100
15 1 F1 3AG FUSE
16 1 ISOTOP STE36N50DK
17 2 J2, J1 CON5
18 2 J7, J8 CON2
19 1 Laux Auxiliary winding
20 1 Lb BO OST INDU CTOR
21 1 Q1 STH80N05
22 1 Rgf 1 1/4W
23 1 Rhn 4.7 1/2W
24 2 R72, Rz 100k 1/4W
25 2 R142, R2 10k 1/4W
26 2 R31, R4 1M 1/4W
27 1 R8, R9 4k 1/4W
28 1 R13 390k 1/4W
29 1 R14 47k 1/4W100k
30 1 R16 no R16 with L4981A
31 1 R17 24k 1/4W
32 1 R19 47 1W
33 1 R20 100k 2W
34 1 R32 4.7k 1/4W
35 1 R71 820k 1/4W
36 1 R73 22k 1/4W
37 1 R141 750k 1/4W
38 1 U1 L4981A/B

4/9

AN829 APPLICATION NOTE

SWITCHING FREQUENC Y

fs is kept below 50kHz to maintain the RFI noise within the optimum frequency
range of the VFG 243 standard. Figure 3 shows that in the range of 10kH z/50kHz the switching frequency fun­damental spectrum requires less filtering. C18 = 2.2nF and R17 = 24k2 give a switching frequency of 46kHz.

BOOST INDUCTOR:

For applications in the range of 3kW, the boost inductor design is greatly determined by

material choice and core availability.
As mentioned the inductor parasitic capacitance determines the filter requirements in the range 1MHz-30MHz

(with regards to the switching noise). To keep this capacitance as low as possible, a single layer winding is the
best solution, but this requires the use of a toroidal core shape to balance winding turns and core section. In this
case a material with distributed air gaps, for example iron powder, is a good choice (see #2).

This is the cheapest core material available with an inherently high saturation flux density combined with a dis­tributed air gap. Test have been performed using two different cores:

– T300-26D core from MICROMETAL (Anaheim, CA) made of iron powder / 60 turns / 12 AWG.
– 2 x CO55866A2 core from MAGNETICS, made of nickel, iron and molybdenum / 46 turns / 12 AWG.

OUTPUT CAPA CITA NCE

value depends upon the expected output voltage drop during the specified holdup

time. Considering a value of 2000F, the voltage drop during a 10msec holdup can be calculated from:
Pout × 10msec = 1/2 Cout (Vout - Vmin)
then V
and V

= 382V at 1400W

min

= 360V at 3000W

min

FEED FORWARD COMPENSATION:

Pin 7 should be supplied with a voltage proportional to the rms mains voltage. This voltage must be in the range
of 1.5V to 5.5V.

The circuit shown in figure 4 gives a good compromise between response time and harmonic attenuation with

Ω

the following values: C71=68nF, C72 = 1mF, R71=820k

, R72 =1 00kΩ and R73 = 22kΩ.

Figure 3. VFG 243 LIMITS Figure 4. Feed Forward Compe nsati on Net-

work

100

90
80
70
60
50
40

10

KHz

50

KHz

150

KHz

APPROXIMATE
VFG243 LIMITS

500

KHz

D95IN254

30

MHz

RECTIFIED

MAINS VOLTAGE

R71

R72

7

C71 C72 R73

D95IN255

5/9

AN829 APPLICATION NO TE

VOLTAGE ERROR AMPLIFIER:

Operating with P
rent is defined by: I

Then the output voltage ripple V
V

= 7.5A / 2π × 100 × 3500 × E-6 = 6Vpeak

r

= 3000W and V

out

= (P

capa

out

= 400Vdc, the mean I

out

/ V

) cos 4!ft So the peak current is: P

out

can be evaluated as:

r

is 7.5A. The corresponding 100Hz capacitor cur-

out

= 7.5A

out/Vout

Voltage divider R141/R142 attenuates the output voltage ripple to:
V

= 6Vpeak x 5.1/400 = 0.0765Vpeak

ri

Assuming 3% peak voltage ripple at the voltage error amplifier output, ripple can be evaluated as:
Vro = (5.1V - 1.27V) 0.03 = 0.115Vpeak
where the first term is the output error amplifier voltage range.
Then the global voltage error amplifier gain at 100Hz must be:
G

= Vro/Vri = 0.115/0.0765 = 1.5

vea

as G
with R14 = 47k

# 1 / R14 2πf C13

vea

Ω

then C13=22nF

To maintain voltage loop stability requires the placement of a pole at a unity-gain frequency of about 18Hz (see
#5)

then R13C13 = 1/2
and R13 = 390k

.

π

18

Ω

LOAD COMPENSATION:

A voltage applied at pin 6 can be used to perform compensation, for example a load feed forward compensation.
With reference to the multiplier section, this input is equivalent to the voltage error amplifier output. If not used,
it should be connected to the reference voltage (pin 11).

MULTIPLIER

Imult = K

circuit has the following response:

mult

Iac (V

-1.27) (0.8LFF-1.27)/Vrms

vea

where:
K

is the multiplier constant (.37) V

mult

is the voltage error amplifier output. LFF is the voltage at pin 6.

vea

Iac is the current supplied into pin 4. Vrms is voltage at pin 7.
To keep the maximum multiplier output current below 300

from 95
The previous equation gives: I

µ

A to 270µArms.

# 60µArms with Vin=95Vrms and Pout=1400W, or Vin=195Vrms and

mult

µ

A, R4 should be set to 1MΩ, meaning I

rms varies

ac

Pout=3000W.

CURRENT AMPLIFIER SECTION:

Using a low R

Power MOSFET as current sense instead of a resistance leads to a reduction of the parasitic

DSon

inductance and allows the heat generated to be dissipated in the heatsink. Using the specifications of the
STH80N05, R

max is 11mW at 25°C and 15mW at 80°C.

sense

6/9

Then the maximum rms voltage across the sense is:

AN829 APPLICATION NOTE

RMS sense voltage = 15m
Then R8 = R9 = .24V / 60

Ω

16A = .24V

µ

A # 4k

Ω

Critical current amplifi er gain occurs when the current error ampli fier slope exceeds the oscillator slope. This
condition occurs when:

V

= (Vo/Lb) Rsense G

oca fs

ca

Gca = current amplifier gain
V

= current amplifier output voltage

oca

f

= switching frequency

s

L

= boost inductor value

b

Then G
Setting G
R

z

= V

ca

oca fs Lb

# 25 enables the calculation of Rz and Cz:

ca

# GcaR9 # 100k

/ (Vo R

Ω

) = 5 45E+3 0.8E-3 / 400 0.015 = 28

sense

Cz = 1 / 2pfcRz with a crossover frequency fc of 10kHz.
then C
Capacitor C

=150pF.

z

can eventually be added to reduce the phase lag of the amplifier.

p

IMPLEMENTATION AND SWITCHING BEHAVIOR

Using a double-sided PCB significantly reduces the parasitic inductances of the circuit:

– parasitic inductance Lp1 and Lp2 shown in figure 1 are intrinsic characteristics of the ISOTOP module

itself; these values are very low (less than 10nH).

– parasitic inductances Lp3 and Lp4 are due to the ISOTOP/capacitor loop. The proposed layout re-

sults in about 20 nH for Lp3+Lp4.

These values mean that the total voltage overshoot during the turn off of the MOSFET is limited to about 30V
with a di/dt of 1000A/sec with no snubber.

– parasitic inductance Lp5 is a few nH due to the use of an active current sense in a TO- 218 package.

This results in an excellent signal/ noise ratio at the current error amplifier input. The following mea­surements have been made with the iron powder inductor as described in paragraph 4.

Figure 5

shows the most important signals with an input voltage of 208Vac and an output power of 1600W. To
show the current ripple more clearly, one second persistence has been used. The slight overshoot of the current
error amplifier output during the mains zero voltage crossing is due to the rise of the inductor permeability at lo w
induction. Indeed, the inductor size optimisation requires operation with 50% saturation of the iron at maximum
peak current.

Figure 6
Figure 7
Figure 8

shows average values of the waveforms in figure 5.

shows the input current and voltage with 120Vac mains and 1600W output Power.

shows the drain voltage and source current during turn off. Note that the source current probing cre­ates a parasitic inductance, limiting the di/dt. Thus there is no significant turn off overvoltage.

Figure 9

R

shows the diode recovery current with a forward current of 20A and a di/dt of 700A/µsec. Note that the

gate drive resistance can be adjusted to tightly control the di/dt. This is still acting with high di/dt value due

gn

to the low parasitic inductance of the gate drive. Thermal measurements have been performed enabling the

7/9

AN829 APPLICATION NO TE

junction temperature to be accurately estimated:
with :

V

= 220Vac/Iin = 8Arms

in

V

= 400Vdc/Rgn = 0

out

Ω

MOSFET+DIODE conduction losses = 10W
MOSFET+DIOD E commutat. losses = .52W/kHz
with:

V

= 120Vac/Iin = 15Arms

in

V

= 400Vdc/Rgn = 0

out

Ω

MOSFET+DIODE conduction losses = 40W
MOSFET+DIOD E commutat. losses = .88W/kHz
with a gate drive resistance R

=102, 25% must be

gn

added to the commutation losses.

Figure 5. Current & Voltage Recorders-

D95IN256A

INSTANTANEOUS INDUCTOR

CURRENT (2A/DIV)

CURRENT AMPLIFIER

OUTPUT (1V/DIV)

RECTIFIED MAINS

VOLTAGE(50V/DIV)

Figure 7. Average Current & Voltage-

AVERAGE INDUCTOR

CURRENT 5A/DIV

RECTIFIED MAINS

VOLTAGE 50V/DIV

1msec DIV

Figure 8. Turn Of f Mo s fe t be havior-

TURN OFF DRAIN

VOLTAGE 50V/DIV(-100V offset)

D95IN265A

D95IN266A

VOLTAGE ERROR OUTPUT

(1V/DIV)

1msec DIV

Figure 6. Average Current & Voltage-

AVERAGE INDUCTOR

AVERAGE CURRENT

AMPLIFIER OUTPUT

8/9

(1VDIV)

CURRENT (2A/DIV)

VOLTAGE ERROR

OUTPUT (1V/DIV)

1msec DIV

RECTIFIED MAINS

VOLTAGE (50V/DIV)

D95IN257A

TURN OFF SOURCE

CURRENT (5A/DIV)

Figure 9. Diode Recovery Current

20nsec DIV

D95IN267A

5A/DIV

AN829 APPLICATION NOTE

CONCLUSIONS

This paper presents an optimized Power Factor C orrector built around a power module driven by the L4981 con­trol IC. This STE36N50-DK ISOTOP power module is mounted directly on the PCB providing both very low in­ductance layout and compact hardware.

Eliminating parasitic inductances enabl es tight control of switching di/dt and prevents turn off overvoltage.
Therefore faster switching speeds are allowed to reduce switching losses. The 2Amps current capability of the
controller is also a useful feature.

Combined with a single layer winding inductor, such a configuration results in very low EMI and RFI generation.
Finally, there is potential for further improvements using two features of the L4981:

– the possibility either to synchronize the IC with an external signal, or to modulate the PFC switching

frequency to spread the RFI noise.

– the extra multiplier input, which enables external compensation.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or o th erwise un der any pat ent or patent right s of STMi croelectr oni cs. Specifications menti oned in th i s publicati on are subj ect
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as c ritical components in li fe support devices or syst em s without express wri t ten approval of STMic roelectronics.

The ST logo is a registered tradem ark of STMicroelectronics.

All other n am es are the property of their respective owners

© 2003 STMi croelectronics - All ri ghts reserved

Australi a - B elgium - B razil - Canada - China - C zech Republi c - Finlan d - F rance - Germ any - Hong Kong - India - Is rael - Italy - Japan -

Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States

STMicroelectronics GROUP OF COMPANIES

www.st.com

9/9