ST AN628 Application note

AN628

APPLICATION NOTE

DESIGNING A HIGH POWER FACTOR SWITCHING PREREGULATOR WITH THE L4981 CONTINUOUS MODE

by Ugo Moriconi

INTRODUCTION

Conventional AC-DC converters usually employ a full wave rectifier bridge with a simple capacitor filter to draw power from the AC line. This "bulk" capacitor must be big enough to supply the total power during most of each half-cycle, while instantaneous line voltage is below the DC rectified voltage. Consequentely, the line current waveform is a narrow pulse, and the power factor is poor (0.5-0.6) due to the high harmonic distortion of the current waveform.

If a high power factor switching preregulator is interposed between the input rectifier bridge and the bulk filter capacitor, the power factor will be improved (up to 0.99). Increasing in addition, the RMS current capability from the mains, reducing the bulk capacitor peak current and the harmonic disturbances.

Switching at a frequency much higher than the line's one, the preregulator draws a sinusoidal input current, in phase with the input line voltage.

There are several way that this can be accomplished. When the output voltage is higher than the input voltage (Vo > Vin), BOOST topology and continuos inductor current control mode are well suited to produce a good quality input sine current waveform. The input di/dt is low because the inductor is located between the bridge and the switch. This minimizes line noise and the line spikes will be absorbed by the inductor.

Figure 1. L4981 Block Diagram

April 2004

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AN628 APPLICATION NOTE

THE L4981 PFC CONTROLLER IC

The L4981 integrated circuit is a continous mode average current controller with several specific functions for active power factor correction. It can operate in high quality, medium/high power conversion range and provides all the necessary features to achieve a very high power factor, up to 0.99. Thanks to the BCD technology used, operative switching frequency higher than 200kHz can be used.

The L4981 can be used in systems with universal input mains voltage without any line switch.

This new PFC offers the alternative of synchronization working at fixed frequency (L4981A), or working in modulated frequency (L4981B) to optimize the size of the input filter. Both devices control the conversion in average current mode PWM to maintain a sinusoidal line current without slope compensation.

MAIN FEATURES:

■Switching frequency higher than 200 kHz.

■Under Voltage Lockout with hysteresis and programmable turn-on threshold.

■Overvoltage and Overcurrent Protection.

■Precise (2%) on chip Reference externally available.

■Input/Output Synchronization (only for L4981A).

■Feed Forward Line and Load regulation.

■Universal input mains.

■Average current mode PWM.

■High Output Current totem pole driver.

■Low Start-up supply current.

■Soft Start.

P.F.C. BOOST TOPOLOGY OPERATION

The operation of the P.F.C. boost converter (see fig. 2) can be summarized in the following description.

The A.C. line voltage is rectified by a diode bridge and the rectified voltage delivered to the boost converter. The boost converter section, using a PWM switching technique, boosts the rectified input voltage to a D.C. controlled output voltage (VO). The section consists of a boost inductor (L), a controlled power switch (Q), a boost diode (D), an output capacitor (CO) and, obviously, a control circuitry.

Referring to the time-variable mains voltage (sine waveform), the converter produces a boost inductor average current like the rectified input voltage, changing continuosly the duty-cycle of the active switch (Q).

The boosted D.C. voltage is controlled to a programmed value, higher than the maximum input instantaneous voltage (VIpk).

Referring to the main currents shown in fig.2 schematic, the simplified formulae are (assuming: power efficiency = 1; output ripple voltage = 0; high frequency inductor ripple current = 0):

1) Peak inductor (L), switch (Q) and diode (D) currents

ILpk = IQpk =	IDpk	= 2	PO
			----------
			Vlpk
2) RMS inductor current
ILrms =	2	PO
		----------
		Vlpk
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AN628 APPLICATION NOTE

Figure 2.

~

L

D

IL

IQ

ID

IO

IC

LOAD

~

CONTROLLER

Q

CO

Cin

D94IN119

3) RMS switch current

IQrms =

PO

2 –

16 Vlpk

----------

----------------------

Vlpk

3

π VO

4) Average diode current

IDavg = IO

5) RMS diode current

IDrms

=

PO

16 Vlpk

----------

----------------------

Vlpk

3

π

VO

6) Total RMS capacitor (CO) current

I

=

I

16 VO

– 1

C

O

--------------------------

3

π

V

Ipk

7) RMS twice line frequency capacitor current

IC(2f)rms

=

IO

------

2

8) RMS high frequency capacitor current

I

=

I

16 VO

C(hf)rms

O

-------------------------- – 1.5

3

π V

lpk

The figure 3 shows the above mentioned quantities, normalized to the D.C. output current (IO), plotted versus VIpk / VO ratio. Moreover, the ILpk · ILrms normalized to IO2 value, related to the inductor energy (I2 · L), is plotted in the diagram (dotted line). This last plot gives an idea on the heavy increase of the inductor size operating with large input voltage range.

Obviously, in real application the efficiency is less than 100% (η < 1). The output voltage ripple, related to the output capacitor (CO) is a parameter to be considered. The inductor high frequency current ripple (∆IL) is another parameter affected by the inductor value (L), the switching frequency (fsw) and the delivered power (PO).

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Figure 3.

ILpk	ILrms
----------------------------
	Io2

Figure 4.

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AN628 APPLICATION NOTE

CONTROLLER FUNCTION DESCRIPTION.

The L4981 I.C. controls the conversion process with a continuous mode average current method, using two control loops (current loop and voltage loop) see fig. 5. Moreover, several internal functions ensure high quality conversion performance.

A description of the internal blocks will be detailed in the design criteria section and pin description. However, referring to fig. 4, here below a brief description of the main functions is done:

Multiplier block.

This block produces an output current (programming current) as a product result of four different input signals (see fig. 13 for details). The multiplier output current, through a resistor connected to the negative side of a sense resistor, determines the error signal to the current loop.

Figure 5.

VOLTAGE

CONTROL LOOP

		CURRENT		POWER
LINE		CONTROL LOOP		STAGE

LOAD

D94IN061

Figure 6.

L
	REF
	11 8.5V	OSC
Raux	Iaux	Iipk	S
			Q
	IPK
		-	R
Ripk		+
	I	1,10
	RS	GND
	Ipk		D94IN062A

Operational amplifier blocks.

Two amplifiers allow loop control. The first one (E/A), feeds back the output voltage (VO) and delivers its output to the multiplier block. The second (C/A), feeds back the line current and produces the reference for the PWM section.

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AN628 APPLICATION NOTE

PWM block.

This block, comparing the sawtooth produced by the oscillator, with the reference signal from the C/A output, modulates its output signal duty-cycle. Its output, by the logic and driver sections, allows the controlled switch

(Q) to modulate the inductor current.

Logic block.

Controls the flow from the PWM and the output with the Auxiliary function signals and soft start.

Driver block.

The driver supplies the gate current to turn on and off the power switch (Q). It delivers up to 1A peak current to allow high switching frequency applications.

Aux functions.

The Auxiliary functions allow to avoid overstress on power components of the application.

Power supply block.

This circuitry delivers the internal supply and references, recognizes the Undervoltage and Stand-by conditions to save consumption.

P.F.C. BOOST DESIGN CRITERIA

L4981 PIN DESCRIPTION AND BIASING CIRCUITRY.

Pin 1. P-GND (Power stage ground). This pin, on the pc-board, has to be connected close the external Mosfet source.

Pin 2. IPK (Overcurrent protection input). The current limitation is obtained with an internal comparator that holds down the output driver when the voltage at IPK input goes down to zero. In the L4981A, to preset the IPK input there is an internal current source (Iipk) of typically 85 A. The maximum peak current (Ipk) can be programmed connecting (see fig. 6) a single resistor (Ripk) between this pin and the sense resistor (RS):

Ripk	RS Ipk
	= -------------------
	Iipk

In the L4981B, to preset the IPK input, an auxiliary resistor (Raux), connected from the VREF pin to the IPK pin, is required. The maximum peak current (Ipk) can be programmed choosing (see fig. 6) the resistances Raux and

Ripk:

	Ripk	=	RS Ipk
			-------------------
			Iaux
	Where:		VVREF
	Iaux	=
			-----------------
			Raux

Note: If used with the L4981A, the auxiliary resistor avoids that the current source spread affects the precision of the protection simply getting an auxiliary current (Iaux) much higher than Iipk.

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Pin 3. OVP (Overvoltage protection input). A comparator with a precise 5.1V reference voltage and 250mV of hysteresis, detects the overvoltage condition and turns the controller in stand-by condition (with low power consumption) and discharges the soft start capacitor. This pin (see fig. 7) has to be externally connected with a resistive divider (Ra and Rb) to the D.C. output voltage. The divider ratio is defined by the relation:

Ra VO + ∆VOUT 1

------- = --------------------------------- –

Rb 5.1V

where: ∆VOUT is the output overvoltage limit.

Figure 7.

Pin 4. IAC (A.C. current input). This pin (see fig. 8) has to be connected through a resistor to the rectified line voltage to drive the multiplier with a current (IIAC) proportional to the instantaneous line voltage:

I VI

IAC = ---------

Rac

The relation between the input alternate current (IIAC) and the output current (programming signal Imult) of the multiplier is described at MULT-OUT section (pin8).

Figure 8.

Pin 5.CA-OUT (Current amplifier output). The CA_OUT deliveres its signal to the PWM comparator. An external network (see fig. 9) defines the suitable loop gain to process the multiplier output and the line current signals. To avoid oscillation problem (see fig. 10) the maximum inductor current downslope (VO/L) has to be lower than oscillator ramp-slope (Vsrp · fsw):

VO	R		G		≤ V		f
-------		s		ca		srp		sw
L

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where:

Vsrp is the oscillator ramp peak-peak voltage. Gca is the current amplifier gain.

fsw is the switching frequency.

and rewritten as:

	Gca	Vsrp fsw			L
		≤ -------------------------------
		VO		Rs
Figure 9.
					OSC
		+			PWM
		C/A
		-
	8	9			5
					CA OUT
		Rf		Cf
Ri'	Ri
	Rs				D94IN063
Figure 10.

Rf defines the high frequency C/A gain (1 + ----- ):

Ri

Rf	≤	Vsrp fsw	L
-----		-------------------------------	– 1
Ri		VO RS

To define the Cf value, it's useful to consider the current openloop gain, defined by the ratio between the voltage across Rs and the current amplifier output signal:

Gavg	vrs
	= --------
	vca

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Because, in worst condition is:

vrs =	Rs VO
	------------------s L

and the total variation of vca (the reference signal for PWM) is Vsrp:

Gavg	Rs VO
	= ------------------------------------	2π f L
	Vsrp

Multiplying this Gavg by Gca and solving for the crossover frequency (f = fc), follows:

fc =	fsw
	-------2π

To ensure a phase margin (higher than 45°), the zero frequency (fz) should be about

fz	fsw		=	1		Cf	=	2
	= ----------	π		π Cf	Rf			fsw
	4		2				Rf

fc

--- , than: 2

Figure 11.

Gain [dB]
100
80	Gca	Gloop
60
40
20	Gavg
0
-20
-40
-60	100	1000	10000	100000
10
		f [Hz]

Pin 6. LFF (Load feed-forward input). This voltage input pin allows to modify the multiplier output current proportionally to the load in order to improve the response time versus load transient. The control is working with VLFF between 1.5V and 5.1V. If this function is not used, the LFF pin has to be connected to VREF pin.See also appendix A.

Pin 7. VRMS. Input to the divider (1/V2RMS), it is especially useful in universal mains applications to compensate the gain variation related to the input voltage change. It will be connected to an external network (see fig. 12a) giving a voltage level proportional to the mains VRMS. The best control is reached using a VRMS voltage level in the range between 1.5V and 5.5V.

Figure 12a.

	RA	RB	VRMS
			1/V2
			7
~	CA		RC
			CB
			D94IN064

To avoid line current distorsion, the rectified mains ripple (2f) level has to be reduced. A two pole filter, with three resistors and two capacitors, setting the lowest pole at 2Hz and the highest one at 13Hz, is enough to get the useful voltage level reducing to - 80dB the 100Hz gain.

Figure 12b.

The signal (pin 7), with the network in fig. 12a is:

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VRMS = 85V (110V -20%)	VRM(7) = 1.6V
VRMS = 260V (220V +20%)	VRM(7) = 5V
Gain at 2f(100Hz)	-80dB

Pin 8. MULT-OUT (Output of the multiplier). This pin deliveres the programming current (Imult) according to the relation:

Imult = 0.37 IIAC	(Vva – out – 1.28V) (0.8 VLFF – 1.28V)
	----------------------------------------------------------------------------------------------------------VRM2
		S

where: VVA-OUT = E/A output voltage range VLFF = voltage input at pin 6

VRMS = voltage input at pin 7

IIAC = input current at pin 4

To optimize the multiplier biasing for each application, the relation between Imult and the other input signals to the multiplier are here reported (refer to figure 13 and see figures 13a to 13h).

Figure 13.

Figure 13a. MULTI-OUT vs. IAC (VRMS = 1.7V;	Figure 13b. MULTI-OUT vs. IAC (VRMS = 2.2V;
VLFF = 5.1V)	VLFF = 5.1V)

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Figure 13c. MULTI-OUT vs. IAC (VRMS = 4.4V; VLFF = 5.1V)

Figure 13d. MULTI-OUT vs. IAC (VRMS = 5.3V; VLFF = 5.1V)

Figure 13e. MULTI-OUT vs. IAC (VRMS = 1.7V; VLFF = 2.5V)

Figure 13f. MULTI-OUT vs. IAC (VRMS = 2.2V; VLFF = 2.5V)

Figure 13g. MULTI-OUT vs. IAC (VRMS = 4.4V; VLFF = 2.5V)

Figure 13h. MULTI-OUT vs. IAC (VRMS = 5.3V; VLFF = 2.5V)

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