ST AN628 Application note

AN628

APPLICATION NOTE

DESIGNING A HIGH POWER FACTOR SWITCHING

PREREGULATOR WITH THE L4981 CONTINUOUS MODE

by Ugo Moriconi

INTRODUCTION

Conventional AC-DC converters usually employ a full wave rectifier bridge with a simple capacitor filter to draw
power from the AC line. This "bulk" capacitor must be big enough to supply the total power during most of each
half-cycle, while instantaneous line voltage is below the DC rectified voltage. Consequentely, the line current
waveform is a narrow pulse, and the power factor is poor (0.5-0.6) due to the high harmonic distortion of the
current waveform.

If a high power factor switching preregulator is interposed between the input rectifier bridge and the bulk filter
capacitor, the power factor will be improved (up to 0.99). Increasing in addition, the RMS current capability from
the mains, reducing the bulk capacitor peak current and the harmonic disturbances.

Switching at a frequency much higher than the line's one, the preregulator draws a sinusoidal input current, in
phase with the input line voltage.

There are several way that this can be accomplished. When the output voltage is higher than the input voltage
(Vo > Vin), BOOST topology and continuos inductor current control mode are well suited to produce a good
quality input sine current waveform. The input di/dt is low because the inductor is located between the bridge
and the switch. This minimizes line noise and the line spikes will be absorbed by the inductor.

Figure 1. L4981 Block Diagram

April 2004

1/35

AN628 APPLICATION NOTE

THE L4981 PFC CONTROLLER IC

The L4981 integrated circuit is a continous mode average current controller with several specific functions for
active power factor correction. It can operate in high quality, medium/high power conversion range and provides
all the necessary features to achieve a very high power factor, up to 0.99. Thanks to the BCD technology used,
operative switching frequency higher than 200kHz can be used.

The L4981 can be used in systems with universal input mains voltage without any line switch.

This new PFC offers the alternative of synchronization working at fixed frequency (L4981A), or working in mod­ulated frequency (L4981B) to optimize the size of the input filter. Both devices control the conversion in average
current mode PWM to maintain a sinusoidal line current without slope compensation.

MAIN FEATURES:

■ Switching frequency higher than 200 kHz.

■ Under Voltage Lockout with hysteresis and programmable turn-on threshold.

■ Overvoltage and Overcurrent Protection.

■ Precise (2%) on chip Reference externally available.

■ Input/Output Synchronization (only for L4981A).

■ Feed Forward Line and Load regulation.

■ Universal input mains.

■ Average current mode PWM.

■ High Output Current totem pole driver.

■ Low Start-up supply current.

■ Soft Start.

P.F.C. BOOST TOPOLOGY OPERATION

The operation of the P.F.C. boost converter (see fig. 2) can be summarized in the following description.

The A.C. line voltage is rectified by a diode bridge and the rectified voltage delivered to the boost converter. The
boost converter section, using a PWM switching technique, boosts the rectified input voltage to a D.C. controlled
output voltage (V

). The section consists of a boost inductor (L), a controlled power switch (Q), a boost diode

O

(D), an output capacitor (CO) and, obviously, a control circuitry.

Referring to the time-variable mains voltage (sine waveform), the converter produces a boost inductor average
current like the rectified input voltage, changing continuosly the duty-cycle of the active switch (Q).

The boosted D.C. voltage is controlled to a programmed value, higher than the maximum input instantaneous
voltage (V

Ipk

).

Referring to the main currents shown in fig.2 schematic, the simplified formulae are (assuming: power efficiency
= 1; output ripple voltage = 0; high frequency inductor ripple current = 0):

1) Peak inductor (L), switch (Q) and diode (D) currents

P

O

---------- -

I

LpkIQpkIDpk

2

⋅===

V

lpk

2) RMS inductor current

P

O

I

Lrms

---------- -

2

⋅=

V

lpk

2/35

Figure 2.

AN628 APPLICATION NOTE

~

~

3) RMS switch current

4) Average diode current

5) RMS diode current

6) Total RMS capacitor (CO) current

L

O

lpk

= I

I

Q

16 V

2

-----------------------–⋅=

3 π V

O

16 V

---------------------- -⋅=
⋅⋅

3 π V

⋅⋅

⋅

I

L

C

in

P

O

I

Qrms

---------- -

V

lpk

I

Davg

P

I

Drms

---------- -

V

⋅

lpk

QCONTROLLER

lpk

O

D

I

D

D94IN119

O

I

O

I

C

C

O

LOAD

16 VO⋅

I

CIO

-------------------------- - 1–=
3 π V

⋅⋅

Ipk

7) RMS twice line frequency capacitor current

I

I

C2f()rms

O

-------=

2

8) RMS high frequency capacitor current

16 VO⋅

I

Chf()rmsIO

The figure 3 shows the above mentioned quantities, normalized to the D.C. output current (I
V

/ VO ratio. Moreover, the I

Ipk

Lpk

· I

normalized to I

Lrms

-------------------------- 1.5–=
3 π V

⋅⋅

lpk

), plotted versus

2

value, related to the inductor energy (I2 · L), is plotted

O

O

in the diagram (dotted line). This last plot gives an idea on the heavy increase of the inductor size operating
with large input voltage range.

Obviously, in real application the efficiency is less than 100% (
output capacitor (C

) is a parameter to be considered. The inductor high frequency current ripple (∆IL) is anoth-

O

er parameter affected by the inductor value (L), the switching frequency (f

η

< 1). The output voltage ripple, related to the

) and the delivered power (PO).

sw

3/35

AN628 APPLICATION NOTE

Figure 3.

I

⋅

LpkILrms

----------------------------

2

I

o

Figure 4.

4/35

AN628 APPLICATION NOTE

CONTROLLER FUNCTION DESCRIPTION.

The L4981 I.C. controls the conversion process with a continuous mode average current method, using two con­trol loops (current loop and voltage loop) see fig. 5. Moreover, several internal functions ensure high quality con­version performance.

A description of the internal blocks will be detailed in the design criteria section and pin description. However,
referring to fig. 4, here below a brief description of the main functions is done:

Multiplier block.

This block produces an output current (programming current) as a product result of four different input signals
(see fig. 13 for details). The multiplier output current, through a resistor connected to the negative side of a
sense resistor, determines the error signal to the current loop.

Figure 5.

VOLTAGE

CONTROL LOOP

Figure 6.

LINE

CURRENT

CONTROL LOOP

L

REF

Raux

Ripk

Iaux

IPK

I

D94IN061

11 8.5V

R

Ipk

POWER

STAGE

S

LOAD

OSC

I

ipk

-

+

1,10

GND

S

Q

R

D94IN062A

Operational amplifier blocks.

Two amplifiers allow loop control. The first one (E/A), feeds back the output voltage (VO) and delivers its output
to the multiplier block. The second (C/A), feeds back the line current and produces the reference for the PWM
section.

5/35

AN628 APPLICATION NOTE

PWM block.

This block, comparing the sawtooth produced by the oscillator, with the reference signal from the C/A output,
modulates its output signal duty-cycle. Its output, by the logic and driver sections, allows the controlled switch
(Q) to modulate the inductor current.

Logic block.

Controls the flow from the PWM and the output with the Auxiliary function signals and soft start.

Driver block.

The driver supplies the gate current to turn on and off the power switch (Q). It delivers up to 1A peak current to
allow high switching frequency applications.

Aux functions.

The Auxiliary functions allow to avoid overstress on power components of the application.

Power supply block.

This circuitry delivers the internal supply and references, recognizes the Undervoltage and Stand-by conditions
to save consumption.

P.F.C. BOOST DESIGN CRITERIA

L4981 PIN DESCRIPTION AND BIASING CIRCUITRY.

Pin 1.

P-GND (Power stage ground). This pin, on the pc-board, has to be connected close the external Mosfet

source.

Pin 2.

IPK (Overcurrent protection input). The current limitation is obtained with an internal comparator that holds
down the output driver when the voltage at IPK input goes down to zero. In the L4981A, to preset the IPK input
there is an internal current source (I
connecting (see fig. 6) a single resistor (R

) of typically 85µA. The maximum peak current (Ipk) can be programmed

ipk

) between this pin and the sense resistor (RS):

ipk

RSIpk⋅

R

In the L4981B, to preset the IPK input, an auxiliary resistor (R
is required. The maximum peak current (I
R

:

ipk

) can be programmed choosing (see fig. 6) the resistances R

pk

ipk

-------------------=

I

ipk

), connected from the VREF pin to the IPK pin,

aux

and

aux

RSIpk⋅

Where:

R

I

aux

ipk

-------------------=

V

VREF

----------------- -=

R

I

aux

aux

Note: If used with the L4981A, the auxiliary resistor avoids that the current source spread affects the precision
of the protection simply getting an auxiliary current (I

) much higher than I

aux

ipk

.

6/35

AN628 APPLICATION NOTE

Pin 3. OVP (Overvoltage protection input). A comparator with a precise 5.1V reference voltage and 250mV of
hysteresis, detects the overvoltage condition and turns the controller in stand-by condition (with low power con­sumption) and discharges the soft start capacitor. This pin (see fig. 7) has to be externally connected with a
resistive divider (Ra and Rb) to the D.C. output voltage. The divider ratio is defined by the relation:

∆V

+

V

where:

∆

Figure 7.

V

is the output overvoltage limit.

OUT

Ra

------- -

Rb

O

--------------------------------- 1–=

OUT

5.1V

Pin 4.

IAC (A.C. current input). This pin (see fig. 8) has to be connected through a resistor to the rectified line
voltage to drive the multiplier with a current (II

The relation between the input alternate current (I

) proportional to the instantaneous line voltage:

AC

V

I

IAC

IAC

I

--------- -=

R

ac

) and the output current (programming signal Imult) of the

multiplier is described at MULT-OUT section (pin8).

Figure 8.

Pin 5.CA-OUT (Current amplifier output). The CA_OUT deliveres its signal to the PWM comparator. An external
network (see fig. 9) defines the suitable loop gain to process the multiplier output and the line current signals.
To avoid oscillation problem (see fig. 10) the maximum inductor current downslope (VO/L) has to be lower than
oscillator ramp-slope (V

srp

· fsw):

V

O

------- -

R

sGcaVsrpfsw

L

⋅≤⋅⋅

7/35

AN628 APPLICATION NOTE

where:

V

is the oscillator ramp peak-peak voltage.

srp

G

is the current amplifier gain.

ca

is the switching frequency.

f

sw

and rewritten as:

Figure 9.

G

ca

V

srpfsw

------------------------------- -

≤

V

⋅

ORs

L⋅⋅

OSC

Figure 10.

Ri' Ri

Rs

Rf

+
C/A

-

PWM

598

CA OUT

Cf

D94IN063

R

f

defines the high frequency C/A gain (1 + ):

-----

R

i

R

-----

R

f

i

V

srpfsw

------------------------------- - 1–≤

V

ORS

L⋅⋅

⋅

To define the Cf value, it's useful to consider the current openloop gain, defined by the ratio between the voltage
across Rs and the current amplifier output signal:

v

rs

--------=

v

ca

8/35

G

avg

Because, in worst condition is:

AN628 APPLICATION NOTE

RsVO⋅

------------------ -=

v

rs

sL⋅

and the total variation of v

(the reference signal for PWM) is V

ca

srp

RsVO⋅

Multiplying this G

G

avg

by Gca and solving for the crossover frequency (f = fc), follows:

avg

------------------------------------ -=

2π fL⋅⋅⋅

V

srp

f

sw

------- -=

f

c

2π

To ensure a phase margin (higher than 45°), the zero frequency (f

f

---------- -

z

4 π⋅

Figure 11.

Gain [dB]
100

80

Gca

60

40

20

Gavg

0

-20

-40

-60
10 100 1000 10000 100000

Gloop

f [Hz]

f

sw

1

-------------------------------

2 π C

⋅⋅ ⋅

fRf

C

⇒

Figure 12a.

~

To avoid line current distorsion, the rectified mains
ripple (2f) level has to be reduced. A two pole filter,
with three resistors and two capacitors, setting the
lowest pole at 2Hz and the highest one at 13Hz, is
enough to get the useful voltage level reducing to ­80dB the 100Hz gain.

:

f

c

) should be about , than:

z

2

------------------== =

f

R

⋅

ffsw

R

R

A

B

C

C

A

B

--- -

2

VRMS

7

R

C

D94IN064

2

1/V

Pin 6.

LFF (Load feed-forward input). This voltage in­put pin allows to modify the multiplier output current
proportionally to the load in order to improve the re­sponse time versus load transient. The control is
working with V

between 1.5V and 5.1V. If this

LFF

function is not used, the LFF pin has to be connected
to VREF pin.See also appendix A.

Pin 7.

VRMS. Input to the divider (1/V

2

RMS

), it is es­pecially useful in universal mains applications to
compensate the gain variation related to the input
voltage change. It will be connected to an external
network (see fig. 12a) giving a voltage level propor­tional to the mains V
using a V

voltage level in the range between 1.5V

RMS

. The best control is reached

RMS

and 5.5V.

Figure 12b.

The signal (pin 7), with the network in fig. 12a is:

9/35

AN628 APPLICATION NOTE

V

= 85V (110V -20%) VRM(7) = 1.6V

RMS

V

= 260V (220V +20%) VRM(7) = 5V

RMS

Gain at 2f(100Hz) -80dB

Pin 8.

MULT-OUT (Output of the multiplier). This pin deliveres the programming current (Imult) according to the

relation:

V

va out–

---------------------------------------------------------------------------------------------------------- -

IAC

where: V

V

V

I

I

mult

= E/A output voltage range

VA-OUT

= voltage input at pin 6

LFF

= voltage input at pin 7

RMS

= input current at pin 4

IAC

0.37 I

⋅⋅=

To optimize the multiplier biasing for each application, the relation between Imult and the other input signals to
the multiplier are here reported (refer to figure 13 and see figures 13a to 13h).

Figure 13.

1.28V–()0.8 V

2

V

RMS

LFF

1.28V–⋅()⋅

Figure 13a. MULTI-OUT vs. IAC (V

V

= 5.1V)

LFF

10/35

RMS

= 1.7V;

Figure 13b. MULTI-OUT vs. I

V

= 5.1V)

LFF

AC

(V

RMS

= 2.2V;

AN628 APPLICATION NOTE

Figure 13c. MULTI-OUT vs. IAC (V

= 5.1V)

V

LFF

Figure 13d. MULTI-OUT vs. I

V

= 5.1V)

LFF

AC

(V

RMS

RMS

= 4.4V;

= 5.3V;

Figure 13f. MULTI-OUT vs. I

= 2.5V)

V

LFF

Figure 13g. MULTI-OUT vs. I

V

= 2.5V)

LFF

AC

AC

(V

(V

RMS

RMS

= 2.2V;

= 4.4V;

Figure 13e. MULTI-OUT vs. I

= 2.5V)

V

LFF

AC

(V

RMS

= 1.7V;

Figure 13h. MULTI-OUT vs. I

V

= 2.5V)

LFF

AC

(V

RMS

= 5.3V;

11/35

AN628 APPLICATION NOTE

Pin 8 has to be connected through a resistor (Ri') to the negative side of Rs (see fig. 9) to sum the (IL · RS) and
the (I

Pin 9.

scribed at CA-OUT (pin 5). To be noted that Ri and Ri' have the same value because of the high impedance
feedback network.

· Ri') signals. The sum result is the error signal voltage to the current amplifier non inverting input.

mult

R

' · I

= Rs · IL

i

mult

ISENSE (Current Amplifier inverting input). This pin, is externally connected to the external network de-

Pin 10.

SGND (Signal ground). It has to be connected, to the pc-board GND, close the filtering reference ca-

pacitor.

Pin 11.

VREF (Voltage reference). An internal bandgap circuitry, allows an accurate voltage reference. An ex-

ternal capacitor filter (from 100nF to some

µ

F) connected to the signal ground is recommanded (see fig. 14).

This pin can deliver up to 10mA and can be used for external needs (e.g. enable for other circuits).

Figure 14.

Pin 12.

SS (Soft start). This feature avoids current overload on the external Mosfet (Q) during the ramp-up of
the output boosted voltage. An internal switch discharges the capacitor if output overvoltage or VCC undervolt­age are detected. An internal current generator of 100

µ

with the external capacitor define the soft start time
costant (see fig. 15). Because the voltage at the softstart pin acts on the E/A output (driving the multiplier with
V

= 5.1V typical voltage swing), the softstart time is defined by:

VAOUT

t

SS

C

ss

V

VA-OUT

---------------------- -

⋅=

I

SS

Figure 15.

12/35

AN628 APPLICATION NOTE

This time (tSS) depends on the application parameters (output voltage, input voltage, output capacitor value,
boost inductor size, etc.) and normally the value amounts at some tens of msec.

Pin 13.

V

voltage (V

Figure 16. Figure 16a.

First of all, the system does not have to attempt to regulate the twice mains frequency output voltage ripple
(

∆

VO) to avoid the line current distorsion. Moreover the system stability has to be ensured. The voltage open

loop gain can be splitt in two separated blocks.

(Error amplifier output). Output of the E/A that determinates the control of the boosted regulated

VA-OUT

). This pin has to be connected with a compensation network to the pin 14 (see fig.16).

O

The first block small signal gain, is given by the ratio between the E/A output voltage (vea) and output voltage
variation (vo) and is defined by the E/A network:

Where Gea` is the E/A gain without R

Gea'

ref. fig. 16. R2 has no effect on the error amplifier gain because the in-

r

vea

----------

vo

1

------------------------- -==

⋅⋅

sR1C

r

verting input potential is fixed to VREF. The Gea can be seen also as the ratio between the error amplifier output
ripple and the imposed output voltage ripple (
value less than 2.5% of the effective E/A output swing voltage (V
So, the Gea defined at the output voltage ripple frequency, determinates the C

∆

VO). The E/A output signal can swing between 1.28V to 5.1V. A

= 3.82V) could be chosen to fix the Cr.

VAOUT

value to ensure the 100/120 Hz

r

(2f) attenuation.

0.095V

------------------ -

≤

--------------------------------------------------

C

r

2 π 2f R1 Gea⋅⋅ ⋅ ⋅

Gea

V

∆

O

∆

1

Ka

⋅≥=

V

-----------

R1

O

where: Ka = 1/60 for 50Hz and 1/72 for 60Hz mains frequency.

Lower C
filter capacitor (C
load variation through the E/A output response (

value could increase harmonic distortion.The second block (Power block) is represented by the output

r

) with its own reactance (XCO), the system has to be able to compensate the total external

O

∆

Vea). The power gain transfer function (Gpw), for large varia-

tions can be written:

X

CO

G

pwIO

-------------

⋅=

Vea∆

The total load variation (I

) to be considered is: P

O

O(max)/VO

:

13/35

AN628 APPLICATION NOTE

POXCO⋅

pw

------------------------- -

V

Vea∆⋅

O

G

⇒

G

pw

P

O

------------------------- -

V

Vea∆⋅

O

1

---------------

⋅==

sCO⋅

The voltage open loop gain contains two poles in the origin, then stability problem can arise. Connecting the
resistor (R

) in parallel to the capacitor Cr to shift the E/A pole from the origin to 1/(Rr · Cr), the stability is en-

r

sured.

The crossover frequency fc can be calculated by G



f

c

--------------------------------------------------



V

⋅⋅⋅



O

To allow the highest DC gain maintaining a phase margin of at least 22°, the R

The output filter capacitor value (C

Pin 14.

VFEED (Error amplifier input). This pin (see fig. 16), connected to the boosted output voltage through a

) is related to the output voltage filtering (see Power section design).

O

divider, allows the output D.C. voltage regulation. Neglecting the contribution of the E/A feedback resistor (R
the 5.1V reference and the output DC voltage (V

· G

pw

P

O

Vea∆ 2 π C

------------------------- -

≤

R

r

2π f

) define the ratio between R1 and R2:

O

R1

------- -

R2

= 1 and therefore:

ea`



----------------------------- -

⋅=



2π R1 C

O

2.75

⋅⋅

cCr

V

O

------------ 1–=

5.1V

1

⋅⋅

r

maximum value is imposed as:

r

r

To be considered that the R1, togheter with the feedback network(see pin 13 description) define the E/A gain.
The R1/Rr ratio affects the load regulation (lower output current increases the output voltage) with the following
relation:

∆ R1⋅

V

ea

------------------------- -=

R

r

where: V

V

∆

Omax

is the maximum output voltage variation due to the E/A gain reduction and load variation.

Omax

The R1 and R2 will be chosen in the high precision class:

),

Pin 15.

P-UVLO (Programmable supply undervoltage threshold). An internal divider (between pin 19, pin 15 and
ground) and an internal comparator with a threshold voltage of 1.28V fixes the default turn-on and turn-off 15.5V
and 10V levels of the supply section (see fig. 17). Using an external divider (R
the supply thresholds: R

fixes the hysteresis, RL fixes the turn-on threshold. To design a divider for a given

H

and RL) it's possible to change

H

supply threshold, is useful know (see fig. 17), the typical resistor value, useful to design the external divider, are:
R1 = 394k, R2 = 88k and R3 = 58k. Anyway, in fig. 17a/b a diagram with threshold values and a table, useful
for a fast choice of R

and RL are shown.

H

For DISABLE function see Appendix B.

14/35

Figure 17.

AN628 APPLICATION NOTE

Programmable Under Voltage

V

CCON

and V

RH = RL * 6.8

UVLO

CCOFF

+

-

vs. R

1.28V

L

R

1

R

R

2

3

19

15

10

V

CC ON

11V 10V 82kΩ 12kΩ

12V 10.1V 220kΩ 33kΩ

13V 10.5V 430kΩ 62kΩ

14V 10.8V 909kΩ 133kΩ

14.5V 10.9V 1.36MΩ 200kΩ

15V 11V 2.7MΩ 390kΩ

V

P-UVLO

D94IN066A

CC OFF

R

H

R

L

RH RL

b)

Pin 16.

a)

SYNC (In/Out synchronization). Only for L4981A, this function allows the device to be synchronized with
other circuits of a system (see fig.18a). When the device is externally synchronized, the external clock has to
satisfy these conditions: the signal amplitude must cross the threshold value (3.5V), the frequency has to be
slightly higher than that programmed by the R-C constant (see pin 18) and the pulse width has to be at least
800 nsec.
If the device has to synchronize other circuits, the signal delivered by this pin is a positive pulse of 4.6V (0.5mA)
and the pulse duration is equal to the sawtooth falltime.

The L4981B uses this pin to perform another function. If the application does not use the SYNC function, it is
preferrable to focus the EMI filtering problem using the B version. Pin 16, named FREQ-MOD in B version, al­lows to change the switching frequency in order to spread the energy content over a wider spectrum range.

To perform the frequency modulation (see fig.18b), the pin must be connected, through a resistor (R
rectified line voltage. This allows to change dinamically (cycle by cycle) the (C

) charge and the discharge

OSC

), to the

fm

currents that define the ramp slopes of the oscillator sawtooth. The effect of the resistor produces the frequency
change (see fig.18c) between the nominal value (f
age reaches the peak value (V

). The total frequency variation (see also pin 17 and 18) can be estimated by

Ipk

) and its minimum value which occurs when the input volt-

sw

the formula:

⋅

fsw∆

----------- K
f

sw

V

IPKRosc

----------------------------- -

⋅=

V

⋅

RMSRfm

15/35

AN628 APPLICATION NOTE

where: Rfm is the programming current resistor.

K is a constant value = 0.1157 for R value in K

∆

f

sw

A typical 20% can be a good compromise.

Figure 18.

-----------

f

sw

Ω

and fSW in KHz.

a)

1.28V

8.5V

16

Rfm

10I

COSC

200I

18

C

OSC

D94IN065A

I

Ifm

MRS

7

1

FREQ-MOD

2 POLES

FILTER

+

-

1/V

17

ROSC

R

OSC

VRMS

Modulation Frequency Normalzed in an Half Cycle of the Mains Voltage

fsw

1

0.8

0.4

0.2

0.8

0.4

0.2

Vl

1

-

+

b)

c)

16/35

0

0

45

90

135

Electrical degrees

180

0

AN628 APPLICATION NOTE

Pin 17.

ROSC (Oscillator resistor). An external resistor connected to ground, programs the charge and the dis-

charge currents that pin 18 (C

) forces to the external capacitor. The reference voltage at pin 17 is 1.28V

OSC

(see fig.18a/b)

To set the charge current, the relation is:

1.28V

Ic10

--------------- -

⋅≈

R

OSC

The discharge current is defined by:

I

c

The maximum discharge current of Id = 12mA, this means a minimum R

Pin 18.

ground, fixes the rise and fall time (t

COSC (Oscillator capacitor). An external capacitor (see fig 18a/b), connected between this pin and

and tf) of the sawtooth oscillator according to the previous relations (pin

r

⋅≈

R

OSC

value of 22KΩ.

osc

1.28V

--------------- -

200

17) and therefore the switching frequency. The typical ramp valley-peak voltage (V

The period T is defined by:

1

1

Tt

+ V

rtf

⋅==

srpCOSC



---- -

----+



I

I

C

d

the switching frequency is:

f

sw

1

---

T

2.44

----------------------------------- -

≈=

R

⋅

OSCCOSC

) is fixed to 5V.

srp

See also Fig. 19

Figure 19. Oscillator Diagram

Pin 19.

VCC (Supply voltage input). The very low cur­rent consumption feature before the turn-on thresh­old is reached. The undervoltage circuitry, with the
threshold hysteresis of 5.5V typ. (see also pin 15)
and an internal clamp at 25V (typ.) ensure the IC
safety operation.

Pin 20.

GDRV (Gate driver output). This output is in­ternally clamped to 15V (see Fig. 20), to avoid ageing
problems of the gate oxide. The output driver is nor­mally connected to the gate of the power device
through a resistor (say 5 to 50 Ohm) to avoid over­shoot and to control the dI/dt of the switch.

POWER SECTION DESIGN

Booster Inductor

The Boost Inductor design involves various parame­ters to be handled and there are different approaches
to define them.

In continuous mode operation, the energy stored in
the boost inductor in each switching cycle, is not
completely transferred to the output (bulk) capacitor.
A quantity of energy is stored in the magnetic circuit,
reducing in this way the input current ripple. This min­imizes the line noise and reduces the input filter size
(see fig.21).

17/35

AN628 APPLICATION NOTE

Figure 20.

Figure 21.

The energy transferred from the boost inductor to the bulk capacitor in each cycle is:

2

E/cycle

1

-- -

LI

2

2

I

–()⋅ LILtIL∆⋅⋅==

Lp

Lv

where:

L = Boost Inductance
I

= Inductor Peak Current (ILt + ∆IL/2)

Lp

I

= Inductor Valley Current (ILt - ∆IL/2)

Lv

I

= Instantaneous Line Current (ILp + ILv)/2

Lt

∆

IL = Twice Inductor Current Ripple (ILp - ILV)

Because the instantaneous line current (

) that corresponds to the average inductor current in the cycle, draws

ILt

a full rectified (half- sinusoidal) waveform, it is useful to refer to the AC line RMS and peak parameters:

I

Lpk

2I

⋅=

Lrms

where:

I

= I

rms

P

= PO/η

I

η

is the power yeld.

18/35

= PI/V

Lrms

is the input power

is the line current

Irms

The power transferred by the inductor in each cycle

P

t

where: t

For a given L, the twice ripple current
lated as a certain percentage of the I

If the maximum V

I

∆

Lmax()

= δ / fsw and δ = (VO - VIt) / VO

on

value is higher than the VO/2, the maximum ∆IL occours when VIt = and its value is

lpk

V

O

-----------------------=

4fswL⋅⋅

∆

IL is the quantity associated to the transferred energy and can be calcu-

inductor current.

Lpk

I

∆

L

LILtIL∆⋅⋅

--------------------------=

t

on

V

ltVOVlt

------------------------------------ -=

V

Ofsw

AN628 APPLICATION NOTE

–()⋅

L⋅⋅

V

O

------- -

2

If the V

In continuous mode operation, an acceptable curent ripple level (K

maximum value does not reach VO/2 voltage value, the maximum ∆IL is reduced and its value is :

lpk

I

∆

Lmax()

V

lpkVOVlpk

---------------------------------------- -=

–()

V

Ofsw

.

L⋅⋅

) can be considered between 10% to 35%.

r

IL∆

K

----------------- -=

r

⋅

2I

Lpk

Smaller current ripple on the inductor involves smaller noise on the rectified main bus reducing the input filter
size; but the ripple reduction will impose an increase of the boost inductor.

The high voltage, the flux density and the frequency range make the standard high frequency ferrite the most
useful material in P.F.C. applications. To avoid the core saturation, related to the high permeability materials, it
is necessary built an air-gap in order to allow an adequate magnetic force range (H+Hgap).

An easy approach, is to have an approximated minimum value of core size that could be used to perform the
conversion:

Volume

≥

KLI

⋅⋅ ⋅



LpkILpk



IL∆

------- -+

2

where : K = specific energy constant.

L = Boost inductor value in H.

The specific energy constant (K), mainly depends on the ratio between the gap length (l
length (l

can be used to get the minimum volume of the core set in cm

) of the magnetic core set and on the maximum ∆B swing. Practically

eff

I

eff

----------

K14

⋅≈

I

gap

3

. After the minimum core-set size is estimated,

) and the effective

gap

the suitable type will be selected with technical and economic evaluations.

Next step will be the design of the coil parameters.

LILtIL∆⋅⋅

The above mentioned formula

P

Ot

--------------------------=

t

on

19/35

AN628 APPLICATION NOTE

if referred to the magnetic path, can be rewritten :

B∆

P

Ot

Ae I

⋅⋅⋅=

eff

where :

Ae = effective area of the core section.
l

= effective magnetic path length.

eff

∆

B = deviated magnetic flux density.

H = magnetic field strength.

The ratio between the ferrite and the air path magnetic permeability, depends on the ferrite materials. Core ma­terials for power application (such as B50/51), have a initial permeability value about 2500 times that of air. This
means that, above a certain air-gap length percentage, it is possible to neglect the leff (length of the core) sim­plifing the calculation e.g. if a 1% of air-gap length, respect to the core lenght value is used, the error introduced
is about 4%.

Rewriting




Ae I

P

Ot

⋅⋅⋅=

eff

B∆

-------

H

t

on

⋅⋅ ⋅≈

Ae I

P

Ot

gapHgap

-------

H

t

on

B∆

-------

t

on

equating to and simplifing

Because:

I

⋅ NILt and B ∆⋅≈µ

gapHgap

P

Ot

--------------------------=

t

on

Ae I

gapHgap

H∆⋅=

0

Ae N µ

H∆ N

B∆⋅⋅ ⋅ LILtIL∆⋅⋅≈

H∆⋅⋅ ⋅ II

0

∆

----------

⋅≈

I

gap

∆⋅≈

L

I

L

and finally:

LILtIL∆⋅⋅

LI

⋅

N

gap

------------------≈
µ

Ae⋅

0

This simplified relation is much easier to use than the complete one:

L

----- -

N

µ

o

I

Ae

gap

π

-- -

4

2

I

⋅+

gap

---------------------------------------------




------------------+⋅≈
µ0Ae⋅

I

eff

After N has been defined, it's necessary to check the core for saturation of the magnetic path (rated N · I

max

vs.
Air-gap on ferrites databook). If the check is too close the rated limit, an increase of the lgap (gap lengh) and a
new calculation will be necessary. Copper losses R

· I

L

and former's winding space available will be con-

Lrms

2

sidered for the wire selection.

20/35

AN628 APPLICATION NOTE

An auxiliary winding can be used just to get a low cost supply for the I.C. It will be a low cost thin wire coil will
be used and the number of turns is the only parameter to define.

Input Bridge

The input diodes bridge can be standard off-line, slow-recovery and low cost devices. The device selection con­siders just the input current (Irms) and the thermal data.

Input Capacitor

The input filter capacitor (CIN) has to sustain the input instantaneous voltage (VIt), with an imposed voltage rip­ple, during the turn-on (t

The worst conditions will be found at the minimum rated input voltage V

The maximum high frequency voltage ripple (r =

) time of the Mosfet.

on

CINK

∆

VI / VI) has to be imposed:

I

-------------------------------------------------

≥

r

2 π fswrV

rms

⋅⋅ ⋅⋅

lrms

Irms(min)

.

Where: K

is the current ripple coefficient.

r

r = 0.02 to 0.08.

The C

maximum value is limited to avoid current distortion.

IN

Output Bulk Capacitor

The choice of the output bulk capacitor (CO), mainly depends on the electrical parameters that affect the filter
performances and also on the subsequent application.

The D.C. output voltage and overvoltage, the output power and voltage ripple are the first parameters to con­sider in all applications. The RMS capacitor ripple current I
(

∆

VO) will be:

VO∆ I

O

1

------------------------------------ - ESR()
2π 2f C

⋅⋅()

O

= Io/ and so, the output voltage ripple

C(2f)rms

+=

2

2

2

With a low ESR capacitor can be simplify:

C

O

I

O

-------------------------------- -+

2π 2f VO∆⋅⋅

-------------------------------------------- -=

2π 2f VO∆ V

P

O

⋅⋅ ⋅

.

O

Although the ESR, normally does not affect the output ripple parameter, it has to be considered in power losses
account both for the rectified mains frequency and the switching frequency.

If the application (i.e. computer supply) has to guarantee a specified Hold-Up time (t
ing criteria will change:

The C

has to deliver the supply energy for a certain time and a specific dropout voltage.

O

2POt

⋅

C

---------------------------------------------------=

O

V

O_min

2

HOLD

V

–

2

op_min

where:

= minimum output voltage value (normally at the maximum load conditions)

V

O_min

), the capacitance size-

HOLD

21/35

AN628 APPLICATION NOTE

V

= minimum output operative voltage before the 'power fail' detection.

op_min

Power Switch

A power MOSFET is the active switch used in most application for its frequency features. It will be selected ac­cording with the output boosted voltage and the delivered power. There are two contributions for power losses
in the mosfet: conduction losses and switching losses. The on-state power losses can be calculated using the
formula:

P

on-MOS

= I

Qrms

2

R

dson

One extimation of the switching losses can be done considering two separated quantities:

P

capacitive

ossVo

rms

1.5

1

-- -

C

2

· tcr · fsw + P

10



------

C



3

P

crossover

≈ VO · I

⋅+⋅⋅

extVo

rec

2

.

fsw⋅≈

where:

is the Drain capacitance at VDS = 25V.

C

oss

t

is the crossover time.

cr

C

is the external layout stray capacitance.

ext

P

is the contribution due to the diode recovery.

rec

To reduce the crossover losses a snubber network can be used.

Booster diode

The booster diode will be selected to withstand the output voltage and current. Moreover, it has to be as fast as
possible in order to reduce the power switch losses.The STMicroelectronics Turboswitch™ diode series match
this specifications, and are expecially suitable for this application.

The diode power losses can be split in two contributions: conduction losses and switching losses. The conduc­tion losses can be estimated by:

Drms

2

where: V

R

= threshold voltage

to

= differential resistance

d

P

= Vto · IO + Rd · I

Don

Sense Resistor

The sense resistor produces the signal for the current feedback loop and for the overcurrent protection circuit.
An easy criterion to choose the sense resistance is to minimize the power dissipated assuring a sufficient signal to
noise ratio. In much high power applications, it could be considered the magnetic sensing approach (see fig. 22).

Figure 22. Magnetic Sense

Rs

iD

-Vrs

Co

Load

L

iQ

22/35

AN628 APPLICATION NOTE

DESIGN PROCEDURE.

In order to fix the described concepts, here follows a brief description of a possible design flowchart referred to
a typical "low-medium range power" PFC application.

Design target specification:

– Wide range mains; V

– Pre-Regulated DC output voltage; V

– Rated output power; P

The design starts fixing the operating conditions.

– The switching frequency 100kHz ///

– The 100Hz voltage ripple imposed at full load is ± 8V; this is satisfied selecting C

– The Over Voltage limit is set at V

– The maximum current ripple at nominal load has been chosen = 35%

The circuit in fig. 23 can be proposed as reference for medium range power PFC application.

= 88 Vac to 264 Vac.

INrms

= 200W.

O

+50V

out

= 400 V.

O

= 100µF

out

Figure 23. Low-medium Power Typical Application (

220nF

L4981A

18

C4

1nF

C7

100V

R16
24K

620K

1%

R6

5%

2N2222

D3

12

C6

1µF
16V

FUSE

Vi

88VAC to 254V

BRIDGE

4 x BY214

AC

NTC

C1

220nF

400V

R11

560 1%

R21

5.1K

R17

806K

1%

R17

806K

1%

7

4

2

1%

58

27K 5%

R3

2.7K
5%

C8

220nF

100V

R5

R

S

0.07 2W

R7 360K 5% R6 620K 5%

R8

33K

5%

R20

10K 5%

9

C3

1nF

R4

2.7K
5%

VO = 400V; PO = 200W)

R14

0.5W

D3 1N4150

C11

100µF

25V

R12

220K

D2 1N4150

56

5%

R13

15 5%

L 0.9mH

C10
15nF
100V

D4

1N4150

330nF

R19

1.1M
5%

R19

1.1M
5%

R23

R22

1117

DZ

22V

0.5W

1915

61

C5

1µF
16V

R15
10K

0.5W
Q2

STK2N50

14

13

3

20

C9

D1 5TTA5060

412K

412K

STH/STW15NB50

Q1

D5

BYT

11600

R1

1%

R1

1%

270pF

630V

R18

1.8K
4W

C12

R2

11K

1%

D93IN029C

R9

910K

1%

R9

910K

1%

C2

100µF

450V

R10
21K

1%

+

Vo

-

23/35

AN628 APPLICATION NOTE

Input capacitor

The input capacitor, placed across the rectified mains, must be considered as part of the EMI filter. The advan­tage, in placing this part after the mains rectification, is the shunt effect for the high frequency current in order
to avoid it to flow throws the diodes of the bridge due to the poor recovery characteristic.

On the other side, the value of this capacitor must to be held as low as possible because the inherent DC voltage
content affects the harmonic distortion.

With 220nF, the high frequency is filter enough and the introduced DC level can be considered not significant
at reasonable load.

Output capacitor

For the output capacitor selection, it can be consider just the output voltage ripple.

Choosing 100

µ

F/450Vthr 100/120Hz ripple is ± 8Vac

Instead, if the pre regulated voltage bus must ensure enough energy for Hold-up requirements (i.e. the energy
is delivered to a power supply system), the Coot value will be increased to around 180

µ

F.

Sense resistor

The sense resistance (Rest) is selected considering both, the signal level and the power dissipation parameters.

Ω

Using ±70m

, the sense signal is good enough to be managed by the current loop. On the other side, the max-

imum power dissipation will be:

P

ros

= RS · (I

lrms

2

+ I

2

) ≤ 0.5W

lhfrms

Where Alarms max. = 2.50A

Power Mos

The Mosfet breakdown voltage is imposed; Bvdss ≥ V

out

+ Dv

+ margin = 500V. The R

out

is selected taking

dson

in to account the conduction power dissipation.

The formula for calculation is: P

i.e. considering R

= 0.7Ω the P

on(t)

on_max

on_max

2

= I

qrms

· R

don

= 2.15 · 0.7 = 3.3W.

Adding the switching (and the capacitive) losses we can estimate 8W to 10W total power dissipation.

Boost Diode

The continuous current mode of operation, suggest using an Ultra-fast reverse recovery diode. The STMicro­electronics TURBOSWITCH™ family offers a good solution for this kind of application.

Boost Inductor

The inductor design starts defining the L value that is a function of the switching frequency and the accepted
current ripple. In this design, we suggest an inductor value L = 0.75mH that can be realized using an ET3411
gapped set-core ferrite.

24/35

AN628 APPLICATION NOTE

The results, concerning the described circuit, have been tested. And the result are shortly here reported:

V

i

(V

rms

110 60 220 0.999 1.79 1.40 0.40 0.31 0.28 392 8 201 91.6

220 50 217 0.997 2.25 1.68 0.83 0.57 0.48 398 8 204 94.2

f

)

(Hz) (W) (%) (%) (%) (%) (%) (V) (V) (W) (%)

P

i

A-THDH3H5H7H9

PF

V

∆V

O

P

O

O

η

DEMO-BOARD:

Design process and Evaluation results

In order to provide a powerful tool for the complete evaluation of the L4981, It is available a populated Demo­Board. The design process and the description for the demo, is here described.

The demo has been designed to operate in wide range mains and the size and is finalized for a "medium-high"
output power range.

Let us start fixing the overall target of the application.

Electrical target specification:

– Wide range mains; V

– Regulated DC output voltage; V

– Rated output power; P

= 88 to 264 Vac.

INrms

= 400 V.

O

= 360W in any mains condition.

O

– Target efficiency ≥ 90% in nominal load conditions.

Chosen operation conditions of the application

– The rectified mains (100/120Hz) full load voltage ripple is ± 7-8 V (peak to peak) this is achieved using

an output capacitor C

= 220Uf/450V

out

– The maximum current ripple, in nominal load condition, is selected to be about 20%. This can be ob-

tained using the boost inductor L = 0.55mH and setting the switching frequency at 100kHz. ##

– The Over Voltage Protection has been set at V

out

+ 58V

The demo is capable to deliver around 400W output power; anyway in order to limit the temperature, the rated
power is limited to 360W.

The schematic is shown in fig 24.

25/35

AN628 APPLICATION NOTE

Figure 24. Demo Board Circuit (

C2
330n

C3
330n

F1

T15A250V

88 to 264 Vac

BRIDGE
B1 8A

Cf
.22uF
600V

RAux1

**

RAux2

C1
330nF
400V

TP1

15

16

R1
460

VO = 400V; PO = 360W)

B2= D1+D2
+D8+D9

L1=0.5mE42*21*15
gap=1.9 58/6 turns

R11

20*.2mm

56k

R12

VCC

56k

C8
100n

1

19

L4981A/ B**

C6

3.3n
R13

2.2k

C91nR15

R2
33k

R4

1.2M
R6

500k

R5
220k

R7
500k

74

R10
5k

R8

R3

17k

2.2k

R9 (RS)
50m
// 3*0.15)

R14
68

24k

D5­STTA106

D6
DZW06-48

14

12

C12
1u

20

11

C10
150uF

3

6

VCC

D4-STTH8 R06
to220 (/40CW)

L2
3u

D3

R17
15

Q1+Q2#

C13
1u

C14
100n

D7-STTA406

Cs
330pF

Q4
4007

NTC

2.5

R18

6.8
2W

R25
1k
2W

R19
750k

R20
750k

R21

19.6k

V+ BUS=400V

R22
750k

R23
750k

C15
220uF
450V

R24

16.9k

Dz1
18V

C11
220n

R16
220k

13

1710189582

-

# // Q1&Q2
TO220*2
STM12NM50
/ 7C/W

Some design peculiarities

A

magnetic snubber

solution has been adopted in order to limit/control the ramp rate of the current at the turn-

on edge of the Power Mos, referring to the schematic, the parts involved in this function are:

L2, D5, D6, D7, C14 and R18.

The function of the auxiliary inductor L2 is to reduce the ramp rate of the current reducing in this way the peak
current, due to the recovery of the boost diode (D4), and the associate noise emission.

The additional benefit of this magnetic snubber is also the reduction of the switching power dissipated in the
Mos. D5 and D6 needs to provide a path that allows the demagnetization of the inductor L2, clipping the neg­ative spike thus avoiding the Breakdown activation of the booster diode D4.

D7, C14 and R18 will clamp the energy of L2 at the turn off edge of the Mos.

The

inrush current

limiter NTC is placed between the cathode of the boost diode and the bulk capacitor C15.
In this way, the current flowing in to the NTC limiter is the same of the boost diode well below the mains current
especially at minimum mains value.

The demo is provided with "

self-supply

" circuit. The proposed supply circuit, using a Graetz bridge is much

efficient anyway; it can be inadequate when the output power is reduced down to less than 5W.

On board, it has been recovered place for the Raux1 and Raux2. The two resistors will be connected in case of

L4981B

Here follows some comment concerning the design and the selection of the

version evaluation.

power parts

of the demo.

26/35

AN628 APPLICATION NOTE

Input capacitor selection

The demo is not provided with complete dedicated EMI filter. At the input side, two parts compose the capacitor;
the first (Cf.) is placed across the AC input of the bridge and the second one (C1) is tied to the rectified mains.
The advantage, of this configuration is the minimization of the DC content in placing a low value after the mains
rectification (C1), just to filter the high frequency. The capacitor Cf placed in the AC side must be considered as
part of the EMI filter.

Output capacitor selection

For the output capacitor selection, it can be consider just the output voltage ripple.

µ

Choosing Co = 220

Sense resistor selection

The sense resistance is set at 50mOhm (Rs = 3 · 0.15Ohm//) maximum power dissipation (@ 88Vac mains and
360W) will be:

P
Where: I

Rs(max)

= RS · (I

lrms max.

F (450V), the maximum rectified mains ripple is:

π

o

⋅⋅ ⋅

lrms

2

+ I

lhfrms

2

) = 1.04W

---------------------------------------- - 7.3V==

V∆

200 π VoC

= 4.55A

o

Power Mos

In the selection of the power switch, it has been preferred to share the thermal dissipation in two separate
TO220 packages. This is a good solution because the size of the heath sinkers can be limited.

The breakdown voltage is imposed = 500V.

Considering the On resistance (@ T

Conductive losses P_On

(max)

= 100°C) = 320 mΩ the formula for the dissipated power calculation are:

j

Q(max)

2

· R

= 3.9 · 0.32 = 4.9W.

don

= I

Adding the capacitive (about 2.5W) and the switching losses (as low as 2-3 W, thanks to the snubber) we can
estimate

10 to 12W

total power dissipation at lower mains value.

Boost Diode

The 8A 600V chosen Turbuswitch fits well with the application. The power dissipated in the boost diode is about 1.4W.

Boost Inductor

The 0.55mH chosen inductor value allows a low ripple (23%) of its current; moreover, there is enough room (in
the industrialization phase) to reduce the switching frequency holding an acceptable current ripple (e.g. reduc­ing the frequency to 75 kHz the current ripple will be held within 30%.

In this design, the coil has been realized with a gapped set-core ferrite E42*12*15.

The results that can expect, realizing the described circuit, has been tested. And the result are shortly reported
from Table 1 to Table 6.

The PCB and component Layout can be seen in figgs 25, 26 and 27 (The Gerber files of the PCB are available
on request).

27/35

AN628 APPLICATION NOTE

Figure 25. Component Layout (Dimensions 88 x 150mm)

Figure 26. P.C.B. Component Side (Dimensions 88 x 150mm)

28/35

Figure 27. P.C.B. Solder Side (Dimensions 88 x 150mm)

AN628 APPLICATION NOTE

DEMO BOARD TEST RESULTS

Table 1. Maximum power range at 110Vac

V

mains

88Vac 403W 401Vdc 433W 5.1% 0.998 .93

110Vac (*) 407W 403Vdc 431W 2.2% 0.999 .945

132Vac 409W 404Vdc 430W 2.7% 0.999 .95

P

out

V

out

P

in

THD PF Eff.

(*) Most significant losses balance at maximum power (110Vmains):

– Power-mos (Q1+Q2) dissipated power = 9.6W.

– Bridge (B1) dissipated power = 6.3W.

– Boost turbo-diode (D4) dissipated power = 1.6W.

– Boost inductor L1 = 2W

– Aux. Inductor L2 = 1.6W.

– NTC dissipated power = 1.1W.

– Snubber = 1.4W

29/35

AN628 APPLICATION NOTE

Table 2. Maximum power range at 220Vac

V

mains

176Vac 415W 407Vdc 430W 4.2% 0.997 .965

220Vac (*) 417W 408Vdc 431W 5.8% 0.994 .967

264Vac 419W 409Vdc 431W 7.4% 0.989 .972

(*) Most significant losses balance at maximum power (220Vmains):

– Power-mos (Q1+Q2) dissipated power = 7.1W.
– Bridge (B1) dissipated power = 4W.
– Boost turbo-diode (D4) dissipated power = 1.3W.
– Boost inductor L1 = .6W
– Aux. Inductor L2 = 0.9W.
– NTC dissipated power = 0.8W.
– Snubber = 0.9W

Table 3. Nominal power range at 110Vac

V

mains

88Vac 366W 404Vdc 397W 5% 0.998 .92

110Vac (*) 370W 406Vdc 395W 2.2% 0.999 .94

132Vac 372W 407Vdc 394W 3% 0.999 .945

P

out

P

out

V

out

V

out

P

in

P

in

THD PF Eff.

THD PF Eff.

(*) Most significant losses balance at nominal power (110Vmains):

– Power-mos (Q1+Q2) dissipated power = 9.3W.
– Bridge (B1) dissipated power = 5.7W.
– Boost turbo-diode (D4) dissipated power = 1.5W.
– Boost inductor L1 = 1.8W
– Aux. Inductor L2 = 1.35W.
– NTC dissipated power = 1W.
– Snubber = 1.2W

Table 4. Nominal power range at 220Vac

V

mains

176Vac 378W 410Vdc 394W 4.7% 0.997 .959

220Vac (*) 381W 412Vdc 395W 6.4% 0.993 .964

264Vac 381W 412Vdc 395W 8.1% 0.987 .964

P

out

V

out

P

in

THD PF Eff.

(*) Most significant losses balance at nominal power (220Vmains):

– Power-mos (Q1+Q2) dissipated power = 6.9W.
– Bridge (B1) dissipated power = 3.5W.
– Boost turbo-diode (D4) dissipated power = 1.3W.
– Boost inductor L1 = 0.5W
– Aux. Inductor L2 = 0.83W.
– NTC dissipated power = 0.8W.
– Snubber = .8W

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AN628 APPLICATION NOTE

Table 5. Half power range at 110Vac

V

mains

88Vac 219W 420Vdc 239W 2.4% 0.999 .916

110Vac (*) 220W 421Vdc 238W 3.6% 0.999 .925

132Vac 222W 423Vdc 237W 2.7% 0.999 .937

(*) Most significant losses balance at half power (110Vmains):

– Power-mos (Q1+Q2) dissipated power = 7.5W.
– Bridge (B1) dissipated power = 3.7W.
– Boost turbo-diode (D4) dissipated power = 1.1W.
– Boost inductor L1 = 1.3W
– Aux. Inductor L2 = 0.95W.
– NTC dissipated power = 0.7W.
– Snubber = 1W

Table 6. Half power range at 220Vac

V

mains

176Vac 223W 424Vdc 236W 8% 0.993 .945

220Vac (*) 223W 424Vdc 235W 10.5% 0.994 .949

264Vac 223W 424Vdc 235W 15% 0.978 .95

P

out

P

out

V

out

V

out

P

in

P

in

THD PF Eff.

THD PF Eff.

(*) Most significant losses balance at half power (220Vmains):

– Power-mos (Q1+Q2) dissipated power = 5.64W.
– Bridge (B1) dissipated power = 1.9W.
– Boost turbo-diode (D4) dissipated power = 0.88W.
– Boost inductor L1 = .5W
– Aux. Inductor L2 = 0.6W.
– NTC dissipated power = 0.52W.
– Snubber = 0.7W

Significant waveforms

Since the described application is provided with a "magnetic snubber circuitry", it is of some interest to have a
look at some switching waveform.

In figure 28, it is depicted the power drain voltage and the current measured in L2 (aux. Inductor) .

To be observed the "delay effect" of the current and the control of its slope. In fact, this circuitry allows to hardly
reducing the Voltage-Current power crossing and the ramp rate of the drain current, reducing in this way the
power dissipated inside the switch and the high frequency contents of the switching.

In figure 29, it is shown both the switching edge and pointed the recovery charge due to the boost diode and the
effect of the Voltage Clamp (D7, C14, R18).

In figure 30, the switch-off edge is magnified and pointed out the effect of the RCD snubber to ground (Cs, Q4
R25) limiting the dV/dt and the above-mentioned Voltage Clamp.

Finally, in figure 31, it is shown and pointed, in the reverse recovery region, the demagnetization effect of the
D5+D6 and its control on the second slope of the recovery itself.

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AN628 APPLICATION NOTE

Figure 28.

IL2-VDS waveforms at SWITCH-ON
"Magnethic snubber effect"

Figure 29.

IL2-VDS waveforms at SWITCH-OFF

VDS = 100V/div.

Drain voltage snubber RCD effect

Drain current slope control

IL2 = 2A/div.

Figure 30.

IL2-VDS waveforms at SWITCH-OFF and ON

Drain voltage

Current flowing
in the Voltage Clamp

Figure 31.

Boost diode Anode voltage and IL2 Current

Recovery Peak current

Drain voltage

Current flowing in the voltage Clamp

Negative Voltage
for L2 demagnetization

0V

Miscellaneous:

The 360W Demo Board is replacing a previous 200W version. It is possible to order this tool quoting the order
code EVAL4981A. The board comes with a CDROM containing the inherent documentation and a special pro­gram dedicated to the ST PFC controllers (L4981 and L6561) that make it easy the design of these applications.

32/35

AN628 APPLICATION NOTE

APPENDIX A

LFF (pin 6) Function.

Since in Power Factor applications the Error Amp. compensation network has to filter the mains frequency con­tents, in order to reduce harmonic distortions, the crossover frequency of the loop gain must be low. This in­volves a poor load transient response.

An additional function (LFF) is available in L4981A/B devices. It is expecially suitable to modify the multiplier
output current, proportionally to the load, in order to improve the system response bypassing the E/A.The control
is working with VLFF voltage between 2V and 5.1V.

In fig. 32 is shown an application example to explain this function. An external OP-AMP has been used to get
the suitable signal voltage avoiding sense resistor (R1) power dissipation.

In the real application the sense resistor is often replaced by sense transformer.

Figure 32. Application example

~

L

I

L

I

Q

L4981

~

D95IN206B

pin6

(VLFF)

VREF=5.1V

3.6K

R3

D

I

D

I

C

Q

LM258

V

O

I

O

LOAD

C

O

R1

V

CC

+

-

R2

10K

10K

Design criteria:

It is avisable to ensure a minimum VLFF ≅ 2V at the minimum output current.Since the OP-AMP (LM258) Vol =

0.7V (@ 1mA), to get the minimum voltage at VLFF, 1.3V has to be added. A resistor devider tied to the refer­ence voltage (pin 11 of the controller) shifts the output of the OP-AMP.

5.1V 0.7V–()

therefore

1.3V

----------------------------------- -

R3 3.6kΩ+

R3 R3⇒⋅ 1.3kΩ==

The OP-AMP supply voltage is the same used for PFC controller (V
V

= 5.1V at the maximum load (I

O

E.g. for I

= 3A. R1 = 0.1Ω - 1W R2 is roughly 160KΩ.

Omax

O max

V

O

).

R2

⋅⋅ 5.1V==

R1 I

Omax



1

--------- -+



10k

) and its gain if fixed in order to produce

CC

33/35

AN628 APPLICATION NOTE

APPENDIX B

Disable

Sometimes it is useful to disable the controller. For example, in a complete system in which a PWM regulator
follows the PFC stage, at low output power it is advantageous to shutdown the PFC section to improve the over­all system efficiency (stand-by / sleep mode). Likewise most of controllers, one way to do this (using L4981A/
B), is pulling down either the Soft-Start or the E/A output pin . In addition the L4981A/B can be disabled ground­ing the P-UVLO (pin 15) see fig 33.The P-UVLO function has been designed to program the supply thresholds
by means of an external divider (see application note for details) but it can be effectively used for this purpose
forcing a voltage below the internal reference (1.28V).Besides turning off the driver output stage this method
puts the controller in "before start-up" condition and gives the advantage of minimizing the supply consumption
of the IC.

Figure 33.

UVLO

1.28V

+

R

1

R

H

-

19

15

P-UVLO

I ≥ 1mA

R

R

2

3

R

L

DISABLE

10

D95IN281B

34/35

AN628 APPLICATION NOTE

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

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