ST AN592 Application note
Rev 2 1/5
AN592
Application note
June 2008
PLL generation using ST62 auto-reload timer
Figure 1. Auto-reload Timer Block Diagram
INTRODUCTION
This note describes how to generate a digital signal locked in phase and frequency (PLL) with a
calibrated delay starting from an active edge on the Auto-reload timer input pin.
Auto-reload timer description
This timer is an 8 bit timer/counter with prescaler. It includes auto-reload PWM, capture and
compare capability with one input and one output pins. It can be controlled by the following reg-
isters (8 bit):
-
Mode Control Register (MC)
-
Status registers (SC0, SC1)
-
Load register (LR)
-
Incremental counter register (TC)
-
Compare register (CP)
-
Reload/Capture register (RC)
It can also wake-up the MCU from wait mode and exit from stop mode if an external event is
present on the input pin. The prescaler ratio can be programmed to choose the timer input fre-
quency F
IN
(see Table 1).
Example:
The TIMIN input receives a 15 kHz digital signal. We want to generate a phase-locked 15 kHz
digital signal with a falling edge delayed 19μs from the input rising edge, and a duty cycle of
75%. The CPU quartz frequency is 8 MHz.
PLL Generation using ARTimer
2/5
Bit 0
Reg. SC1
PS2 PS1 PS0
PRESCALER
Ratio
0 000 1
0 001 2
0 010 4
0 011 8
0 100 16
0 101 32
0 110 64
0 111 128
1 000 3
1 001 6
1 010 12
1 011 24
1 100 48
1 101 96
1 110 192
1 111 384
Table 1. Prescaler Programming Ratio
The Figure 2 shows the TIMOUT signal gen-
erated in “load on external edge” mode,
given the above TIMIN signal: on TIMIN ris-
ing edge, the TC count register is loaded with
the value contained in RC register (160 in
this example). The timer will resume count-
ing from value 160. When the compare value
(210 in this example) is reached, the
TIMOUT signal goes down. The timer keeps
counting until the overflow (255) is reached.
At this point, signal TIMOUT rises again. The
timer keeps counting from 0 until next active
edge on TIMIN. At this time, TC is loaded
again with the RC value (160) and so on...
The delay from TIMIN edge to TIMOUT fall-
ing edge is given by CP-RC (multiplied by the
TC register clock period Fin). The low level
duration on TIMOUT is given by 255 - CP.
The remaining of the TIMOUT period is vari-
able, and will adjust to the TIMIN period:
small variations of TIMIN period will be ab-
sorbed by a variation of T
VAR
. The following
rule must be respected in order to get the
proper output signal:
The variable time Tvar must stay smaller
than CP, (otherwise the falling edge on
TIMOUT occurs before rising edge on
TIMIN) and larger than 0 (otherwise the ris-
ing edge on TIMOUT never occurs).
In other words, the period of input TIMIN
(TOT in terms of TC clock cycles) must meet
the following requirement:
255-RC<TOT<255-RC+CP
Figure 2. TIMOUT signal
Note: All numbers are decimal
Coming back to our example, let’s calculate
the timer settings:
The input period is Tin = 1/15 kHz = 66.7μs
Calculation of the prescaler ratio:
We want the best possible resolution, e.g.
the smaller possible prescaler ratio: we
would like the TC counter to count up to the
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