ST AN576 Application note

AN576

APPLICATION NOTE

PCB LAYOUT OPTIMISATION

INTRODUCTION

Protection requirements are becoming more and more well known and are often defined by rules or standards. To satisfy these requirements, there is, in the majority of cases, a standard solution or a dedicated product.

However, knowledge of the disturbances and the use of suitable protection devices are not sufficient in themselves to solve the problem. In many applications, the correct design of the PCB layout is essential for success.

Figure 1. Classical protection circuit

Track B

Track A

I

DEVICE

TO BE

DISTURBANCE

P

PROTECTED

SOURCE

VCL

INFLUENCE OF THE PROTECTION LOCATION

The circuit presented in Figure 1 shows the classical approach for the protection location. Here the protection device (see Note 1) is located close to the module to be protected. When a disturbance occurs on the track A the TRANSIL P clamps the surge at a maximum voltage VCL and thus protects the sensitive part.

During this clamping action there is a current through P and also in the track A. This phenomenon induces a voltage on track B, where it is close to A. To avoid this undesirable parasitic overvoltage on track B, the circuit of Figure 2 is recommended.

Note: 1. TRANSIL devices are used as examples throughout this document, but the same arguments are valid for TRISILS.

	REV. 2A - 3588
May 2004	1/6

AN576

Figure 2. Recommended protection location

Track B

Track A

I

DEVICE

TO BE

PROTECTED

VCL

DISTURBANCE P

SOURCE

In this case the current due to the clamping phase of P remains located in the disturbance area and the track B is not affected.

To summarize, it is recommended that the protection device is located as close as possible the disturbance source. For example, all the lines coming into the board ought to be protected close to the connector.

INFLUENCE OF THE PCB LAYOUT ON THE ESD PROTECTION

These days, printed circuit boards are often auto-routed by computer aided design and the track lengths are not optimized.

Figure 3. Non-optimized LAYOUT for ESD

A

P		DEVICE
	U	TO BE
		PROTECTED

DISTURBANCE

SOURCE

B

Figure 3 shows the classical non-optimized layout. When a surge occurs the protection device P acts and there is a clamping voltage VCL across it. Due to the fast rise time of the ESD overvoltage there is a high di/dt between the points A and B. This di/dt generates, in the parasitic inductances located between A and P and between B and P, overvoltages up to several hundred volts. So the applied voltage V across the device to be protected is the sum of the clamping voltage and the voltage across the parasitic inductance: thus the sensitive module is not protected.

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