ST AN557 Application note

AN557

APPLICATION NOTE

EASY APPLICATION DESIGN WITH THE L4970A,

MONOLITHIC DC-DC CONVERTERS FAMILY

The L497XA series of high current switching regulator ICs exploit Multipower-BCD technology to
achieve very high output currents with low power dissipation – up to 10A in the Multiwatt power package
and 3.5A in a DIP package .

THE TECHNOLOGY

The technology architecture is bas ed on the vertical DMOS sil icon gate process that allows a chan nel
length of 1.5 micron ; using a junction isolation technique it has be en possible to mix on the same chip
Bipolar and CMOS transistors along with the DMOS power components (Fig. 2). Figure 1 shows how this
process brings a rapid increase in power IC complexity compared to conventional bipolar technology. In
the 70’s class B circuits and DC circuits allowed out put power in the range of 70W . By 1980, with the in­troduction of switching techniques in power ICs, output powers up to 200W were reached ; with BCD tech­nology the output power increased up to 400W.

November 2003

1/52

AN557 APPLICATION NO TE

Figure 1. BCD process and increase in power ICs complexity.

Figure 2. Cross Section of the BCD Mixed Technology.

THE STEP-DOWN CONFIGURATION

Fig. 3 shows the simp lified block di agram of the c i rcuit realizin g the s t ep-down c onfiguration. T his circuit
operates as follows : Q1 acts as a switch at the frequency f and the ON and OFF ti mes are suitably c on­trolled by the pulse width modulator circuit. When Q1 is saturated, energy is absorbed from the input which
is transferred to the output through L. The emitter voltage of Q1, V

, is Vi-Vsat when Q is ON and -VF (with

E

VF the forward voltage across the D dio de as indicated) when Q1 is OFF. During t his sec ond phase the
current circulates again through L and D. Consequently a rectangular shaped voltage appears on the emit­ter of Q1 and this is then filtered by the L-C-D network and converted into a continuous mean value across
the capacitor C and therefore across the load. The current through L consists of a continuous component,
I

, and a triangular-shaped component super-imposed on it, ∆IL, due to the voltage across L.

LOAD

2/52

AN557 APPLICATION NOTE

Figure 3. The Basic Step-down Switching Regulator Configuration

Fig. 4 shows the behaviour of the most significant waveforms, in different points of the circuit, which help
to understand better the operation of the power section of the switching regulator. For the sake of simplic­ity, the series resistance of the coil has been neglected. Fig. 2a shows the behaviour of the emitter voltage
(which is practically the voltage across the recirculation diode), where the power saturation and the for­ward VF drop across the diode era taken into account.

The ON and OFF times are established by the following expression :

T

ON

------------------------------- -

V

ViV

o

–()

sat

⋅=

T

+

ONTOFF

Fig. 4b shows the current across the switching tran sistor. The current shape is t rapezoida l and t he oper­ation is in continuous mode . At this stage, the phenom ena due to the c atch diode, that we consider as
dynamically ideal, are neglected. Fig. 4c shows the current circulating in the recirculation diode. The sum
of the currents circulating in the power and in th e diode is the current circul ating in the c oil as s hown in
Fig. 4e. In balanced conditions the ∆
decrease occurring during T

OFF

+

current increase occ uring du ring TON has to be equal to the ∆ I

IL

L

. The mean value of IL corresponds to the charge current. The current rip-

ple is given by the following formula :

+

I

∆ I

L

It is a good rule to respect to I

-

∆

== =

L

oMIN

iVsat

----------------------------------------

≥ IL/2 relationship, that implies go od operation in co ntinuous mode.

–()V

V

–

o

L

T

ON

VoVF+

------------------- -

L

T

OFF

When this is not done, the regulator starts operating in discontinuous mode. This operation is still safe but
variations of the switching frequency may occur and the output regulation decreases.

Fig. 4d shows the behaviour of t he voltage ac ross coil L. In b alanced conditions, the mean value of the
voltage across the coil is zero. Fig. 4f shows the current flowing through the capacitor, which is the differ­ence between I

In balanced conditions, the m ean current is equ al to zero, and ∆I

and I

L

LOAD

.

= ∆IL. The current IC through the ca-

C

pacitor gives rise to the voltage ripple.
This ripple consists of two components : a capacitive component, ∆V

, and a resistive component, ∆V

C

ESR

due to the ESR equivalent series resistance of the capacitor. Fig. 4g shows the capacitive component ∆V
of the voltage ripple, which i s t he i nteg ral of a triangular-shaped curren t as a function of time . Moreo ve r,
it should be observed that v
of charge ∆Q

+

supplied to the capacitor is given by the area enclosed by the ABC triangle in Fig. 4f :

(t) is in quadrature with iC(t) and therefore with the voltage V

C

. The quantity

ESR

–

,

C

3/52

AN557 APPLICATION NO TE

Figure 4. Principal Circuit Waveforms of the figure 1 Circuit.

4/52

Which therefore gives:

Q∆

∆

V

C

1

-- -

2

Q

----

C

AN557 APPLICATION NOTE

∆

I

T

L

------- -

---

⋅⋅=

2

2

∆

I

L

--------==

8fc

Fig. 4h shows the voltage ripple V
V

(t) = iC (t) × ESR. Fi g. 4i sh ows t he o vera ll ripple Vo, which is t he sum of the two pre vious com po-

ESR

due to the resistive component of the capacitor. This component is

ESR

nents. As the frequency increases (> 20kHz), which is required to reduce both the cost and the sizes of L
and C, the VESR component becomes dominant. Often it is necessary to use capacitors with greater ca­pacitance (or more capacitors connected in parallel to limit the value of ESR within the required level.

We will now examine the stepdown configuration in more detail, referring to fig. 1 and taking the be-haviour
shown in Fig. 4 into account.

Starting from the initial conditions, where Q = ON, v

= Vo and iL = iD = 0, using Kirckoff second principle

C

we may write the following expression:
V

= vL + vC (V

i

is neglected against Vi).

sat

d

IL

i

------- -

L

dt

v

+ L

C

V

(1)

d

IL

+⋅==

------- - V

dt

o

which gives :

d

------- -

dt

V

IL

–()

iVo

---------------------- -=

L

(2)

The current through the inductance is given by :

ViVo–()

I

---------------------- -=

L

(3)

L

When Vi, Vo, and L are constant, IL varies linearly with t. Therefore, it follows that :

V

+

∆

I

L

–()T

iVo

---------------------------------- -=

L

ON

(4)

When Q is OFF the current through the coil has reached its maximum value, Ipeak and because it cannot
very instantaneously, the voltage across the ased to allow the recirculation of the current through the load.

When Q switches OFF, the following situation is present:

vC(t) = Vo, iL (t) = iD (t) = I

peak

And the equation associated to the following loop may be written :

d

IL

------- -

where : vC = V

V

L

++ 0=

F

o

dI

L

------- -

dt

dt

V

------------------------ -–=

v

FVo

C

(5)

+()

(6)

L

It follows therefore that :

+

V

FVo

t()

------------------- -

T

t–=

(7)

5/52

i

L

AN557 APPLICATION NO TE

The negative sign may be interpretated with the fact that the current is now decreasing. Assuming that VF
may be neglected against V

therefore :

But, because ∆I

L

+

= ∆I

, during the OFF time the following behaviour occurs :

o

V

o

------

t=

V

------

L

ON

(8)

L

o

T

(9)

OFF

V

oTOFF

---------------------=

L

–

if follows that :

L

I

L

+

I

∆

=

L

–()T

V

iVo

---------------------------------- -

L

which allows us to calculate V

:

o

T

ON

V

------------------------- -

==

V

o

i

TONT

OFF

V

where T is the switching period.
Expression (10) links the output voltage V

to the input voltage Vi and to the duty cycle. The relat ion -sh i p

o

between the currents is the following :

T

ON

---------- -

I

iDCIoDC

⋅=

T

EFFICIENCY

The system efficiency is expressed by the following formula :

P

o

------

100⋅=

P

i

where Po = VoIo (with Io = I
system. P

is g ive n by Po, plus all t he other syst em losses. Th e expression of the effic iency becomes th ere-

i

η %

) is the output power to the load and Pi is the input power absorbed by the

LOAD

fore the following :

P

---------------------------------------------------------------------------------=

η

PoP

+ ++++

satPDPLPqpsw

o

T

ON

-----------

i

T

(11)

(10)

(12)

DC LOSSES

Psat :saturation losses of the power transistor Q. These losses increase as Vi decreases.

T

ON

P

ON

T

V

o

------=

V

i

is the power transistor saturation at current Io.

sat

T

where and V

P

---------- -

: losses due to the recirculatio n diode . These loss es incr ease as Vi increases, as in this case the ON

D

sat

V

satIo

---------- -

T

+⋅=

V

satIo

V

------

V

o

i

(13)

time of the diode is greater.

6/52

ViVo–

VFI

----------------- -

o

V

i

P

==

D



V

1



FIo



V

o

(14)

------–

V

i

where VF is the forward voltage of the recirculation diode at current Io.
P

: losses due to the series resistance RS of the coil

L

AN557 APPLICATION NOTE

PL = RS I

o

2

(15)

Pq: losses due to the stand-by current and to the power driving current:

Pq = Vi Iq, (16)

in which Iq is the operat ing supply current at the operating swi tchin g frequency. Iq includes the oscillator
current.

SWITCHING LOSSES

P

: switching losses of the power transistor :

sw

trtf+

------------ -

=

P

sw

ViI

o

2T

The switching losses of the recirculation diode are neglected (which are anyway negligible) as it is as­sumed that diode is used with recovery time much smaller than the rise time of the power transistor.

We can neglect losses in the coil (it is assum ed that ∆ IL is very small comp ared to I

) and in the output

o

capacitor, which is assumed to show a low ESR.

Calculation of the inductance value, L

Calculation T

ON

and T

through (4) and (9) respectively it follows that :

OFF

T

ON

+

I

∆ L⋅

L

----------------- -= T
V

–

iVo

OFF

∆ L⋅

--------------- -=

-

I

L

V

o

But because :

+

T

ON

+ T

= T and ∆I

OFF

L

–

= ∆I

= ∆IL, it follows tha t :

L

T

ON

IL∆ L⋅

----------------- ­–

V

iVo

I

∆ L⋅

L

--------------- -+ T==
V

o

(17)

Calculating L, the previous relation becomes :

V

–()V

V

i

o

------------------------------

L

V

o

I

∆

i

L

T=

(18)

Fixing the current ripple in the coil required by the design (for instance 30% of Io), and introducing the fre­quency instead of the period, it follows that :

V

–()V

L

iVo

-------------------------------- -=

V

0.3 Iof⋅⋅⋅

i

o

where L is in Henry and f in Hz Vi × 0.3 × Io × f

Calculation of the output capacitor C

From the output node in fig. 3 it may be seen that the current through the output capacitor is given by:

ic (t) = iL (t) – I

o

7/52

AN557 APPLICATION NO TE

Figure 5. Equivalent Circuit Showing Recirculation when Q1 is Turned Off.

From the behaviour shown in Fig. 4 it may be calculated that the charge curren t of the output capacitor,
within a period, is ∆I

but, remembering expression (4) :

therefore equation (19) becomes :

Finally, calculating C it follows that :

where :
L is in Henrys

C is in Farads
f is in Hz

Finally, the following expression should be true :

It may happen that to satisfy relation (21) a capacitance value much great er than the value calculated
through (20) must be used.

/4, which is supplied for a time T/2. It follows therefore that :

L

∆

------- -

VC∆

4C

V

+

∆

I

L

–()T

i

---------------------------------- -= T

∆

V

I

L

V

L

C

T

---

2

o

ON

V

----------------------------- -=

I

T∆

L

----------- -

8C

and

–()V

iVo

IL∆

--------===

8fc

ON

o

(19)

V

------

V

o

T=

i

8 Vif2LC

V

–()V

C

ESR

------------------------------------- -=

8 Vi VC f∆

max

iVo

∆

---------------------=

V

Cmax

∆

o

2

L

I

L

(20)

(21)

TRANSIENT RESPONSE

Sudden variations of the load current give rise to overvoltages an d und ervo ltages on th e output v oltage.
Since i

= C (dvc/dt) (22), where dvc = ∆Vo, the instantaneous variation of the load current ∆Io is supplied

c

during the transient by the output capacitor. During the transient, also current through the coil tends to
change its value. Moreover, the following is true :

di

L

------- -

=

v

L

(23)

L

dt

where diL = ∆Io
v

= Vi – Vo for a load increase

L

= Vo for a load decrease

v

L

8/52

Calculating dt from (22) and (23) and equalizing, it follows that :

di

------- -

L

dt

dv

L

=

C

----------

C

i

C

AN557 APPLICATION NOTE

Calculating dv

and equalizing it to ∆Vo, it follows that :

C

V

∆

o

V

∆

o

LI

---------------------------=

CV

LI

-------------=

C V

∆

iVo

∆

2
o

–()

2
o

o

(24) for + ∆Io

(25) for -

∆

Io

From these two expressions the dependence of overshoots and undershoots on the L and C values may
be observed. To minimize ∆V

it is therefore necessary to reduce the inductance value L and to increase

o

the capacitance value C. Should other auxiliary functions be required in the circuit like reset or crowbar
protections and very variable loads may be p resent, it is worthwhile to t ake special care for minimi zing
these overshoots, which could cause spurious operation of the crowbar, and the under-shoot, which could
trigger the reset function.

DEVICE DESCRIPTION

For a better understanding of how the dev ice f unc tions , a description will be given of the prin ciple blocks
that compose the device. The block diagram of the device is shown in fig.6

POWE R SU PPLY

The device contains a stabil ized regulator (Vstart = 12V ) that provides powe r to the a nalogic and digit al
control blocks as well as the section of the bootstrap. The Vstart voltage also powers the bl ocks that op­erates the internal reference voltage of 5.1V, with a precision of ±2%, necessary for the feedback.

OSCILLATOR, SYNC. AND VOLTAGE FEED-FORWARD FUNCTIONS

The oscillator block generates a sawtooh wave signal that sets the switching frequency of the system. This
signal, compared with the output voltage of the error amplifier, generates the PWM signal that will then
sent to the power output stag e. The oscillator also c ontains the voltage feedforward f unction that, be ing
completely integrated, does not require additional external components to function. The VFF function op­erates with supply voltages from 15V to 45V. The ∆V/∆t of the sawtooh is directly proportional to the supply
voltage Vi.

As Vi increases, the conduction time (ton) of the power transistor decreases in such way as to provide to
the coil, and therefore to the load, the product Volt x Sec constant.

Figure 6. Block Diagram of the 10A Monolithic Regulator L4970A.

9/52

AN557 APPLICATION NO TE

Figure 7. Volta ge Feeforward Wa veform.

V2

V7

D93IN006

Vi=30V
Vi=15V

Vc

t

Vi=30V

Vi=15V

t

Fig. 7 shows the duty-cycle varies as a result of the changes in slope of the ramp with the input voltage
Vi. The output of the error amplifier shou ld not chang e to maintain the out put voltage i n regulation. This
function allows for the increas e of s peed in response to the rapid ch ange o f the supply voltage and for a
greatly reduced ouput ripple at the mains frequency.

In fact, the slope of the ramp is modulated by the ripple, generally present in the order of several volts on
the input of the regulator, particularly when the solution with a mains transformer is used.

Fig. 8 shows the simplified electrical diagram of the oscillator.
A resistor, connected between the Rosc pin and GND, sets the current that is internally reflected in the pin

Cosc, in order to charge the external capacitor to which it is connected. The voltage to the Rosc pin is not
fixed, but is tied to the instantaneous value of Vi; this is needed t o achieve th e feedforward voltage func­tion, in which the slope of the ramp is directly proportional t o the supply voltage. A comparator senses the
voltage at the Cosc capacitor. Wh en the voltage reaches the val ue present at the inverting input o f the
comparator, the output from the comparator goes high and is sent to the two transistors Q1 and Q2. Q1
is responsible for discharging the external Cosc capacitor with a current of approx. 20mA, while Q2 im­poses at the inverted input of the comparator a voltage of 2Vbe (approx. 1.3V) that is the low-threshold of
the ramp. Some useful formulas for calculating the various parameters of the oscillator block are:

Figure 8. Osc illator Circuit.

Rosc

Cosc

PWM

COMP.

10/52

Vi

2R

13 2RR

Q1

-

+

Q2

R

CLOCK

D93IN007

AN557 APPLICATION NOTE

1) Oscillator charge current:
Vi9V

–

I

CHARGE

-------------------------=

2) Oscillator discharge current:

3) Peak voltage ramp:

V

th H–

This formula is obtained in the following way: indicating with Ve the voltage of the emitter of the NPN tran­sistor connected to Vcc, and V- the voltage at the inverted input of the comparator, one has:

V

V



V

------------------------- -



by substituting (a) into (b), one obtains:

V

i



---- - V

–



3

------------------------------- --------------- 2V

V

be

–

3

be

R

osc

I

= 20mA

DISCH

Vi9V

–

------------------------ - 2V

Rosc

V

i

–=

---- - V

e

3

2V

–

e

be

3R

2V

be

+=–

(For 15V < Vi < 45V)

be

+=

be

(a)

be

R⋅

+=–

be

2V

(b)

be

V

9V

–

i

be

------------------------- 2V

+=

9

be

4) Valley voltage ramp:

V

= 2V

th-L

be

5) Switching frequency:

SW

------------------------- -=

R

oscCosc

f

9

It should be noted that formula (5) does not take into account the discharge time of Cosc which cannot be
neglected when one is working at frequencies equ al or highe r than 20 0KHz. The d ischarge tim e is also
tied to the value of Cosc itsel f.

Analitycally one has:

6)

T

DISCH

V

th H–

-------------------------------------- -

–

20 mA

V

th L–

C

⋅=

osc

from which is obta ined the mor e clo se ly ap p ro x im a te ex pr e ss io n o f the o s c illat o r fr equency:

7)

f

SW

---------------------------------------- -----------------=

R

oscCosc

----------------------------- - T

1

⋅

+

9

DISCH

During the discharge time of Cosc, a clock pulse is generated internally that is made sub sequent ly avail­able on the Sync. pin and that can be used to synchronize other regulators. (3 devices of the same family
maximum). The Sync. pulse generated has a typical range of 4.5V and the current availabi lity is 4.5mA.
In general, it is better that the Sync pulse is at least 300-400ns in order to be able to synchronize a range
of existing regulators; to obtain this result, values of suggested capacitors, in different test circuits, have

11/52

AN557 APPLICATION NO TE

been selected. The typical duration of th e synchronizing pu lse with the suggest ed values of C

osc

are as

follo ws :

L497X Family (MULTIWATT PACKAGE)

C

(nf) - R

osc

L497X Family (POWERDIP PACKAGE)

C

(nf) - R

osc

= 16KΩ

osc

0.68 140
1230

1.2 270

1.5 330

2.2 450

3.3 680

4.7 1100

= 30KΩ

osc

1.2 230

1.5 280

2.2 420

3.3 600

4.7 900

Sync (ns)

Sync (ns)

Obviously, synchronize pulses of eccessive duration can greatly reduce the max duty-cycle and produce
distortions in the sawtooth of the synchronized regulator working as slave.

P.W.M.

Comparing the sawtooth signal generated by the oscillator and the output of the error amplifier, generates
the PWM signal which is sent to the driver of the output power stage. The PWM signal, in the path towards
the output stage, also encounters a latch block to prevent other pulses from being sent at same period to
the output, possibly damaging the power stage. In the PWM bl ock, a dut y-cycle limiter has al so been in­troduced. Such a limiter is obtained by taking advantage of the synchronizing pulse generated, the power
output stage is inhibited. Even if the error amplifier gives a large signal to the peak of the ramp, the power
stage will not b e able to op er ate in DC , but w ill be s wit ched of f at ea ch clock puls e. The max . obt ainable
duty-cycle is higher than 90%; this, however depends on the working frequency and the value of Cosc.
Using the formulas 6) and 7) a precise calculation can be done.

SOFT START

The Soft Start function is essential for a correct startup of the device and for an output voltage that, at the
switch on, increases in a monotonous mode without dangerous output overvoltages and without over­stress for the power stage.

Soft Start operates at the startup of the system and after an intervention of the th ermal prot ection. Fig. 9
shows the simplified diagram of the startup functions. The function is carried out by means of an external
capacitor connected to the Soft Start pin, which is charged with a constant current of about 100µA to a
value of around 7V. During the charging time, the output of the error transcon-ductance amplifier, because
of Q1, is forced to increase at the same rising edge time of the external softstart capacitor Css.

12/52

Figure 9. Soft Start Circuit.

Figure 10. Soft Start Waveforms.

Vc

AN557 APPLICATION NOTE

CLAMPED

ERROR AMPLIFIER

OUTPUT

t

OUTPUT

CURRENT

SOFT START TIME

D93IN011

t

The PWM signal begins to be generated as soon as the output voltage of the error amplifier crosses the
ramp; at this point the output stage begins to commutate, slowly increasing its ON time (see fig. 10).

The charge of the Css capacitor, as already mentioned, begins each time the device is supplied with pow­er and after which an anomalou s condition is creat ed, as the intervent ion of thermal prot ection or of the
undervoltage lockout.

CALCULATING THE DUTY-CYCLE AND SOFT-START TIME

Let us suppose that the discharge tim e o f the osc illator capac itor, Cos c, is neglected. This is an approx.
valid for switching frequencies up to 200KHz. Let us indicate with Vr the output voltage of the error ampli­fier, and with Vc the voltage of the oscillator ramp.

Figure 11. Soft Sart Time Waveform.

13/52

AN557 APPLICATION NO TE

The PWM comparator block commutates when Vr = Vc. Therefore:

i

9

t⋅

9V

–()⋅⋅

V

9V

–

i

------------------------ -

be

be

9T⋅

t⋅== =

8)

from which is obtained

9)

V

r

V

t

V

pp

--------- -

c

T

Vr T V

------------------------------------------------ -=

The time t obtained from this equation is equal to the ON time of the power transistor. The corresponding
duty-cycle is given by:

10)

Vr T V

t

on

-------

D

------------------------------------------------ -

T

9T

9V

–()⋅⋅

i

be

VrVi9V

--------------------------------------- -

–()⋅

be

9

V

o

------== = =

V

i

Consequently, after leaving the discharged capacitor of Soft Start, the output of the regulator will reach its
value when the voltage across the Css capacitor, charged w ith constant current, has reached the value
Vr - 0.5V.

The time necessary in order that the output rises from zero to the nominal value is given by:

Vr0.5V–()

11)

in which C

is the Soft Start capacitor and Iss the Soft Start current. Considering Soft Start time as tss,

ss

t

start up–

C

ss

---------------------------- -

⋅=

I

ss

the required time for the Soft Start capacitor to change itself approx from (2Vbe - 0.5V) = (1.2V - 0.5V) to
Vr - 0.5V, is:

Vr1.2V–()

12)

t

ss

C

ss

---------------------------- -

⋅=

I

ss

By taking Vr from (10):

13)

V

o

------

V

r

V

i

9

------------------------ -

⋅=

9V

–

V

i

be

and substituting it in (12), we obtain:

14)

o

---------

t

=

ss

------



I

V



ss

i

9

------------------------ - 1.2V–⋅
9V

–

V

i

be

V

C



ss

UNDERVOLTAGE LOCKOUT

The device contains the protection block of under-voltage lockout which keeps the power stage turned-off
as long as the supply voltage does not reach at least 12V. At this point the device starts up with Soft Start.

The function of undervoltage is also provided with an hysteresis of 1V to make it better immune to the rip­ple present on the supply voltage.

ERROR AMPLIFIER

The error amplifier is a transconductance type and deliver an output current proportional to the voltage in­balance of the two inputs . The s i mplified diagram is presented in f i g 12. Th e pri ncipal characteristics of t hi s
uncompensated operational ampl ifier are the following: Gm = 4mA/V, Ro = 2.5Mohm, Avo = 80dB, Isource­sink = 200

µ

A, Input Bias Current = 0.3µA. The frequency response of the op. amp. is given in fig. 13.

Ignoring the high frequency response and hypothesizing that the second pole is below the 0 dB axis in the
all the conditions of loop compensation, it is possible to make a first approximation with the equivalent cir­cuit of fig. 14

14/52

Figure 12. Error Amplifier Circuit.

Figure 13. Ope n l oop gai n ( error amplifier onl y )

AN557 APPLICATION NOTE

Figure 14. Error amplifier equivalent circuit.

In whic h :

15) where C

Av s() Gm

R

c

--------------------------- -

⋅=

1sRoC

+

o

= 3pF

o

The error amplifier can be easily compensated thanks to the high output impe dance (see fig. 14) The re­sulting transfer function is as in the following:

R

1sRcC

+()⋅

(16)

Av s() Gm

---------------------------------------------------------------------------------------------------------------------

⋅=

2

s

R

C

R

o

o

o

C

sRoCcRoCoRcC

c

c

c

++()1++

c

15/52

AN557 APPLICATION NO TE

Figure 15. Compensation network of the error ampli fier

The Bode diagram is shown in fig.16.

Figure 16. Bode plot showing gain and phase of compens ated erro r ampl ifier

The compensation circuit introduces a pole at low frequency and a zero that is generally calculated to be
put in the proximity of the resonance frequency of the output LC filter.

The second pole at high frequency generally falls in a zone of no interest (for the system stability, one must
consider the zero introduced by ESR characteristic of the output capacitor. Not all the designers agree on
this solution).

If necessary, however, one c an turn t o m ore sophisticated compensation circuitry. An ex am ple is s hown
in fig. 17.

Figure 17. One pol e, tw o ze ro com p e nsation netw ork

Such a circuit introduces a pole at low-frequency and two zeros.

17

16/52

Z1

1

-----------------------------

2Π R1 C1

Z2

1

-----------------------------==

2Π R2 C2