ST AN5225, STM32 Application note

AN5225

Application note

USB Type-C Power Delivery using STM32 MCUs and MPUs

Introduction

This application note is a guideline for using USB Type-C® Power delivery with STM32 MCUs and STM32 MPUs, also referring to the TCPP01-M12 protection circuit. The document introduces some basics of the two new USB Type-C® and USB Power

Delivery standards.

The USB Type-C® technology offers a single platform connector carrying all the necessary data. This new reversible connector makes plug insertion more user friendly. Using the Power Delivery protocol, it allows negotiation of up to 100 W power delivery to supply or charge equipment connected to a USB port. The objective is to save cables and connectors, as well as universal chargers.

The USB Type-C® connector provides native support of up to 15 W (up to 3 A at 5 V), extendable to 100 W (up to 5 A at 20 V) with the optional USB Power Delivery feature.

AN5225 - Rev 3 - September 2020 For further information contact your local STMicroelectronics sales office.

www.st.com

1 General information

This document applies to STM32 MCUs and MPUs, based on Arm® Cortex®-M processor.

Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

1.1 Acronyms and abbreviations

AMS Atomic message sequence

APDO Augmented power delivery object

BMC Bi-phase mark coding

BSP Board support package

CAD Cable detection module

DFP Downstream facing port

DPM Device policy manager

DRP Dual-role power

DRS Data role swap

GP General purpose

GUI Graphical user interface

HAL Hardware abstraction layer

HW Hardware

LL Low layer

MSC Message sequence chart

OVP Over-voltage protection

PDO Power delivery object

PE Policy engine

PRL Physical protocol layer

PRS Power role swap

SNK Power sink

SRC Power source

UCPD USB Type-C power delivery

UFP Upstream facing port

VDM Vendor defined messages

FWUP Firmware update

PPS Programmable power supply

TCPM Type-C port manager

TCPC Type-C port controller

TVS Transient voltage suppression

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General information

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1.2 Reference documents

STMicroelectronics ecosystem documents

[1] Managing USB power delivery systems with STM32 microcontrollers, UM2552

[2] STM32CubeMonitor-UCPD software tool for USB Type-C Power Delivery port management, UM2468

[3] TCPP01-M12 USB Type-C port protection, DS12900

[4] USB Type-C protection and filtering, AN4871

[5] STM32CubeMonitor-UCPD software tool for USB Type-C Power Delivery port management, DB3747

[6] USB Type-C and Power Delivery DisplayPort Alternate Mode, TA0356

[7] Overview of USB Type-C and Power Delivery technologies, TA0357

[8] STM32MP151/153/157 MPU lines and STPMIC1B integration on a battery powered application, AN5260

USB specification documents

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Reference documents

[9] USB2.0 Universal Serial Bus Revision 2.0 Specification

[10] USB3.1 Universal Serial Bus Revision 3.2 Specification

[11] USB BC Battery Charging Specification Revision 1.2

[12] USB BB USB Device Class Definition for Billboard Devices

[13] Universal Serial Bus Power Delivery Specification, Revision 2.0, Version 1.3, January 12, 2017

[14] Universal Serial Bus Power Delivery Specification, Revision 3.0, Version 2.0, August 29 2019

[15] Universal Serial Bus Type-C Cable and Connector Specification 2.0, August 2019

[16] USB Billboard Device Class Specification, Revision 1.0, August 11, 2014, http://www.usb.org/developers/docs

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2 USB Type-C in a nutshell

The USB Implementers Forum (USB-IF) introduces two complementary specifications:

• The USB Type-C® cable and connector specification release 1.3 details a reversible, slim connector system based on high-speed USB2.0 signals and two super-speed lanes at up to 10 Gbit/s, which can also be used to support alternate modes.

• The USB Power Delivery (PD) specification revisions 2.0 and 3.0 detail how a link can be transformed from a 4.5 W power source (900 mA at 5 V on VBUS), to a 100 W power or consumer source (up to 5 A at 20 V).

The new 24-pin USB Type-C® plug is designed to be non-polarized and fully reversible, no matter which way it is inserted.

It supports all the advanced features proposed by Power Delivery:

• negotiating power roles

• negotiating power sourcing and consumption levels

• performing active cable identification

• exchanging vendor-specific sideband messaging

• performing alternate mode negotiation, allowing third-party communication protocols to be routed onto the reconfigurable pins of the USB Type-C® cable

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USB Type-C in a nutshell

Figure 1. USB connectors

Mini AB Micro AB

2.0 2.0

Multiple connectors to support

all kind of USB data

3.0

Unique

reversible

connector for all

specifications

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The following points should also be noted:

• USB Type-C® cables use the same plug on both ends.

• USB Type-C® supports all prior protocols from USB2.0 onward, including the driver stack and power capability.

• The new connector is quite small (it is 8.4 mm wide and 2.6 mm high).

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USB Type-C® vocabulary

As shown in Figure 1. USB connectors, the new USB Type-C® plug covers all features provided by previous plugs, which ensure flexibility and siplifies application.

A USB Type-C® port can act as host only, device only, or have dual function. Both data and power roles can independently and dynamically be swapped using USB Power Delivery commands.

2.1

USB Type-C® vocabulary

The terminology commonly used for USB Type-C® system is:

• Source: A port power role. Port exposing Rp (pull-up resistor, see Figure 3. Pull up/down CC detection) on CC pins (command control pins, see Section 4 CC pins), and providing power over VBUS (5 V to 20 V and up to 5 A), most commonly a Host or Hub downstream-facing port (such as legacy Type-A port).

• Sink: A port power role. Port exposing Rd (Pull down resistor. See Figure 3. Pull up/down CC detection) on CC pins and consuming power from VBUS (5 V to 20 V and up to 5 A), most commonly a device (such as a legacy Type-B port)

• Dual-role power (DRP) port: A port that can play source or sink power roles, reversible dynamically.

• Downstream-facing port (DFP): A port data role. A USB port at higher level of USB tree, such as a USB host or a hub expansion.

• Upstream-facing port (UFP): A port data role. A USB port at lower level of USB tree, such as a USB device or a hub master port.

2.2 Minimum mandatory feature set

It is not mandatory to implement and support all of the advanced features that are defined within Type-C and Power Delivery specifications.

The mandatory functions to support are:

• cable attach and detach detection

• plug orientation/cable twist detection

• USB2.0 connection

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3 Connector pin mapping

The 24-pin USB Type-C® connector includes:

• symmetric connections:

– USB2.0 differential pairs (D+/D-)

– power pins: VBUS/GND

• asymmetric connections

– two sets of TX/RX signal paths which support USB3.1 data speed

– configuration channels (CC lines) which handle discovery, configuration and management of USB

Type-C® power delivery features

– two side-band use signals (SBU lines) for analog audio modes or alternate mode

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Connector pin mapping

Figure 2. Receptacle pinout

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

GND RX2+ RX2-

GND TX2+ TX2-

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

A1 GND Ground return up to 5 A split into 4 pins

A2 TX1+

A3 TX1-

A4 VBUS Bus power 100 W max power split into 4 pins

A5 CC1 or VCONN

A6 D+

A7 D-

A8 SBU1 Side band use Alternate mode only

A9 VBUS Bus power 100 W max power split into 4 pins

A10 RX2-

A11 RX2+

A12 GND Ground return up to 5 A split into 4 pins

B1 GND Ground return up to 5 A split into 4 pins

B2 TX2+

B3 TX2-

Name Description Comment

VBUS

Table 1. USB Type-C receptacle pin descriptions

SBU1 D- D+

CC2

Configuration channel or power for

active or electronically marked cable

D+ D-

USB3.0 datalines or alternate 10 Gbit/s TX differential pair in USB3.1

USB2.0 data lines -

USB3.0 datalines or alternate 10 Gbit/s RX differential pair USB3.1

USB3.0 datalines or alternate 10 Gbit/s TX differential pair in USB3.1

CC1

SBU2

VBUS

TX1- TX1+ GND

RX1- RX1+ GND

In VCONN configuration, min power is

1 W

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Pin Name Description Comment

B4 VBUS Bus power 100 W max power split into 4 pins

B5 CC2 or VCONN

B6 D+

B7 D- -

B8 SBU2 Side band use Alternate mode only

B9 VBUS Bus power 100 W ma power split into 4 pins

B10 RX1-

B11 RX1+

B12 GND Ground return Up to 5 A split into 4 pins

3.1 VBUS power options

VBUS provides a path to deliver power between a host and a device, and between a charger and a host or device.

Power options available from the perspective of a device with a USB Type-C® connector are listed below.

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VBUS power options

Configuration channel or power for

active or electronically marked cable

USB2.0 datalines

USB3.0 datalines or alternate 10 Gbit/s RX differential pair in USB3.1

In VCONN configuration, min power is

1 W

Note:

Table 2. Power supply options

Mode of operation Nominal voltage Maximum current Note

USB2.0 5 V 500 mA

USB3.1 5 V 900 mA

USB BC1.2 5 V 1.5 A Legacy charging

Current @1.5 A 5 V 1.5 A

Current @3 A 5 V 3 A

USB PD 5 V to 20 V 5 A Directional control and power level management

Default current based on specification

Support high-power devices

USB Type-C® to Type-C™ cable assembly needs VBUS to be protected against 20 V DC at the rated cable current (3 A or 5 A).

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4 CC pins

There are two CC pins (CC1 and CC2) in the Type-C connector, but only one CC pin is present on the cable plug at each end of the cable (they are connected in common through the cable). On both CC1 and CC2, a source must expose Rp pull up resistors, whereas a sink must expose Rd pull down resistors. Electronic cables need to provide a resistor, Ra, to ground on V

From a source point of view, the state of attached devices can be determined by referring to Table 3.

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CC pins

CONN

Table 3. Attached device states - source perspective

CC1 CC2 State

Open Open Nothing attached

Rd Open

Open Rd

Open Ra

Ra Open

Rd Ra Powered cable with sink, VCONN-

Ra Rd

Rd Rd Debug accessory mode attached

Ra Ra Audio adapter accessory mode attached

Sink attached

Powered cable without sink attached

powered accessory (VPA), or VCONNpowered USB device (VPD) attached.

4.1 Plug orientation/cable twist detection

As a USB Type-C® cable plug can be inserted in the receptacle in either orientation, it is mandatory to first detect the orientation. The detection is done through the CC lines using the Rp/Rd resistors.

Initially a DFP presents Rp terminations on its CC pins and a UFP presents Rd terminations on its CC pins.

To detect the connection, the DFP monitors both CC pins (see figure 4-30 in [15]).

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Figure 3. Pull up/down CC detection

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Plug orientation/cable twist detection

DFP monitors for connection

CC1

CC2

Cable

UFP monitors for orientation

CC1

CC2

UFP monitors for orientation

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4.2 Power capability detection and usage

Type-C offers increased current capabilities of 1.5 A and 3 A in addition to the default USB standard.

The current supply capability of the port to the device depends on the Rp pull up resistor value on the DFP.

High current (5 A) capability is negotiated using the USB Power Delivery protocol.

Table 4 shows the possible values, as per [15].

Table 4. DFP CC termination (Rp) requirements

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Power capability detection and usage

BUS

power

Current source to

1.7 V - 5.5 V

Default USB power 80 mA ± 20%

Rp pull up to

4.75 V - 5.5 V

56 kΩ ± 20%

Rp pull up to

3.3 V +/-5%

(1)

36 kΩ ± 20%

1.5 A @5 V 180 mA ± 8% 22 kΩ ± 5% 12 kΩ ± 5%

3.0 A @5 V 330 mA ± 8% 10 kΩ ± 5% 4.7 kΩ ± 5%

1. For Rp when implemented in the USB Type-C plug on a USB Type-C to USB 3.1 Standard-A Cable Assembly, a USB Type-

C to USB 2.0 Standard-A Cable Assembly, a USB Type-C to USB 2.0 Micro-B Receptacle Adapter Assembly or a USB Type-C captive cable connected to a USB host, a value of 56 kΩ ± 5% shall be used, in order to provide tolerance to IR drop on V

and GND in the cable assembly.

BUS

The UFP must expose Rd-pull down resistors on both CC1 and CC2 to bias the detection system and to be identified as the power sink, as per [15].

Table 5. UFP CC termination (Rd) requirements

Rd implementation Nominal value

± 20% voltage clamp 1.1 V No 1.32 V

± 20% resistor to GND 5.1 kΩ No 2.18 V

± 10% resistor to GND 5.1 kΩ Yes 2.04 V

Can detect power

capability?

max voltage on CC pin

The UFP, in order to determine the DFP power capability, monitors the CC line voltages accurately, as per [15].

Table 6. Voltage on sink CC pins (multiple source current advertisements)

Detection

vRa -0.25 0.15 0.2

vRd-Connect 0.25 2.04 -

vRd-USB 0.25 0.61 0.66

vRd-1.5 0.70 1.16 1.23

vRd-3.0 1.31 2.04 -

Min voltage (V) Max voltage (V) Threshold (V)

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5 Power profiles

The USB Power Delivery protocol enables advanced voltage and current negotiation, to deliver up to 100 W of power, as defined in [14] and reported in the following figure:

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Power profiles

Figure 4. Power profile

Table 7 shows the permitted voltage source and programmable power supply (PPS) selections, as a function of

the cable current rating.

Table 7. Fixed and programmable power supply current and cabling requirements

Fixed voltage source Programmable power supply (PPS)

Power range

5 V 9 V 15 V 20 V

With 3 A cable

0 W < PDP <= 15 W PDP / 5 - - - PDP / 5 - - -

15 W < PDP <= 27 W 3.0 A PDP / 9 - - 3.0 A PDP / 9 - -

27 W < PDP <= 45 W 3.0 A 3.0 A PDP / 15 - 3.0 A 3.0 A PDP / 15 -

45 W < PDP <= 60 W 3.0 A 3.0 A 3.0 A PDP / 20 3.0 A 3.0 A 3.0 A PDP / 20

With 5 A cable

60 W < PDP <= 100 W 3.0 A 3.0 A 3.0 A PDP / 20 3.0 A 3.0 A 3.0 A PDP / 20

5 V (3.3 to

5.9 V)

9 V (3.3 to

11 V)

15 V (3.3

to 16 V)

20 V (3.3

to 21 V)

Further information is available in [14] and [15].

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6 USB power delivery 2.0

In USB power delivery, pairs of directly attached ports negotiate voltage, current and/or the direction of power, and data flow over the USB cable. The CC wire is used as a BMC-coded communication channel.

The mechanisms used operate independently of other USB power negotiation methods.

6.1 Power delivery signaling

All communications are done through a CC line in half-duplex mode at 300 Kbit/s.

Communication uses BMC encoded 32-bit 4b/5b words over CC lines.

6.1.1 Packet structure

The packet format is:

• Preamble: 64-bit sequence of alternating 0s and 1s to synchronize with the transmitter.

• SOP*: start of packet. Can be SOP, SOP’ (start of packet sequence prime) or SOP” (start of packet sequence double prime), see Figure 5. SOP* signaling.

– SOP packets are limited to PD capable DFP and UFP only

– SOP’ packets are used for communication with a cable plug attached to the DFP

– SOP” packets are used for communication with a cable plug attached to the UFP.

A cable plug capable of SOP’ or SOP” communication must only detect and communicate with packets starting with SOP’ or SOP”.

• Message data including message header which identifies type of packet and amount of data

• CRC: error checking

• EOP: end of packet, unique identifier.

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USB power delivery 2.0

6.1.2 K-codes

K-codes are special symbols provided by the 4b/5b coding. They signal hard reset, cable reset, and delineate packet boundaries.

DFP

SOP’

Figure 5. SOP* signaling

Cable

Plug

Electronically Marked

Cable

(SOP’)

SOP’’

SOP

Cable

Plug

(SOP ‘’)

UFP

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6.2 Negotiating power

The DFP is initially considered as a bus master.

The protocol layer allows the power configuration to be dynamically modified.

The power role, data role and VCONN swap are possible independently if both ports support dual power role functionality.

The default voltage on VBUS is always 5 V and can be reconfigured as up to 20 V.

The default current capability is initially defined by the Rp value, and can be reconfigured as up to 5 A for an electronically marked USB PD Type-C cable.

The protocol uses start-of-packet (SOP) communications, each of which begins with an encoded symbol (Kcode).

SOP communication contains a control or data message.

The control message has a 16-bit fixed size manages data flow.

The data message size varies depending on its contents. It provides information on data objects.

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Negotiating power

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7 USB power delivery 3.0

From the power point of view, there are no differences between USB PD 2.0 and USB PD 3.0. All USB PD 3.0 devices are able to negotiate power contracts with USB PD 2.0 devices, and vice-versa. USB PD 3.0 adds the following key features:

• Fast role swap

• Authentication

• Firmware update

• Programmable power supply (PPS) to support sink directed charging

The following is a summary of the major changes between the USB PD 3.0 and USB PD 2.0 specifications:

• Support for both Revision 2.0 and Revision 3.0 operation is mandated to ensure backward compatibility with existing products.

• Profiles are deprecated and replaced with PD power rules.

• BFSK support deprecated including legacy cables, legacy connectors, legacy dead battery operation and related test modes.

• Extended messages with a data payload of up to 260 bytes are defined.

• Only the VCONN source is allowed to communicate with the cable plugs.

• Source coordinated collision avoidance scheme to enable either the source or sink to initiate an atomic message sequence (AMS).

• Fast role swap defined to enable externally powered docks and hubs to rapidly switch to bus power when their external power supply is removed.

• Additional status and discovery of:

– Power supply extended capabilities and status

– Battery capabilities and status

– Manufacturer defined information

• Changes to fields in the passive cable, active cable and AMA VDOs indicated by a change in the structured VDM version to 2.0.

• Support for USB security-related requests and responses.

• Support for USB PD firmware update requests and responses.

System policy now references USBTypeCBridge 1.0.

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USB power delivery 3.0

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8 Alternate modes

All the hosts and devices (except chargers) using a USB Type-C® receptacle shall expose a USB interface.

If the host or device optionally supports alternate modes:

• The host and device shall use USB power delivery structured vendor defined messages (structured VDMs) to discover, configure and enter/exit modes to enable alternate modes.

• It is strongly encouraged that the device provide equivalent USB functionality where such exists for the best user experience.

• Where no equivalent USB functionality is implemented, the device must provide a USB interface exposing a USB billboard device class to provide information needed to identify the device. A device is not required to provide a USB interface exposing a USB billboard device class for non-user facing modes (for exmple diagnostic modes).

As alternate modes do not traverse the USB hub topology, they must only be used between a directly connected host and device.

8.1 Alternate pin re-assignments

In Figure 6, pins highlighted in yellow are the only pins that may be reconfigured in a full-feature cable

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Alternate modes

Figure 6. Pins available for reconfiguration over the Full Featured Cable

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

GND RX2+ RX2-

GND TX2+ TX2-

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

VBUS

SBU1 D- D+

VCONN

SBU2

VBUS

TX1- TX1+ GND

RX1- RX1+ GND

Reconfigurable pin

Figure 7 shows pins available for reconfiguration for direct connect applications. There are three more pins than in Figure 6 because this configuration is not limited by the cable wiring.

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Figure 7. Pins available for reconfiguration for direct connect applications

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1

GND RX2+ RX2-

VBUS

SBU1 D- D+

VBUS

TX1- TX1+ GND

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Billboard

GND TX2+ TX2-

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

8.2 Billboard

The USB Billboard Device Class definition describes the methods used to communicate the alternate modes supported by a device container to a host system.

This includes string descriptors to provide support details in a human-readable format.

For more details, refer to [16].

VBUS

VCONN

SBU2

VBUS

RX1- RX1+ GND

Reconfigurable pin

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9 Product offer

STM32 MCUs and STM32 MPUs handle USB Type-C / USB Power Delivery interfacing by using the STM32 integrated UCPD (USB Type-C Power Delivery) peripheral, or a set of general-purpose (GP) peripherals. See

USB Type-C and Power Delivery application page.

Secure element

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Product offer

Figure 8. USB Type-C Power Delivery block diagram

One chip

Dp/Dn

USB Power

Delivery

controller

Power

management

USB Type-C

interface (PHY)

VBus

Load switch

Protection

CC lines

Figure 9. STM32G0 Discovery kit USB Type-C analyser

USB

Type-C

receptacle

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Product offer

STM32 MPU product specificities

For the STM32 MPU products, take into the consideration the following:

• USB is only supported on Cortex-A7 core. No support on Cortex-M4 core.

• For compatibility with Linux framework, USB Type-C is managed by external devices. Refer to MB1272DK2-C01 board schematics on , CN7 implementation with STUSB1600 chipset (as opposed to CN6 implementation with ADC).

For more information, refer to section USB port using USB Type-C® receptacle in [8].

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Type-C with no power delivery

10 Type-C with no power delivery

This chapter may not fully apply to STM32 MPU products. Refer to Section 9 Product offer for their specificities.

10.1 STM32 USB2.0-only device conversion for USB Type-C platforms

A USB2.0 legacy device needs to present itself as a UFP by means of an Rd pull-down resistor between the CC line and ground. It is assumed here that the maximum legacy USB 2.0 device current is needed, and it is therefore not necessary to monitor the CC lines.

Since the plug is reversible, the two DP/DN pairs need to be connected to each other as close as possible to the receptacle, before being routed to the STM32 device.

Figure 10. Legacy device using USB Type-C receptacle

Connector

Receptacle

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10.2

CC1

CC2

Rd2

5.1k +/-20%

DP1

DP2

DN1

DN2

GND

Rd1

5.1k +/-20%

STM32 USB2.0 host conversion for USB Type-C platforms

STM32x

USB_DP

USB_DN

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This use case describes how to exchange a USB2.0 standard A receptacle for a USB Type-C® receptacle.

As the platform is designed for USB2.0, the maximum current capacity is 500 mA. If a higher supply current is available in the application, the Rp resistors can be adjusted to give 1.5 A or 3 A capability.

A USB2.0 legacy host needs to be configured as a DFP by means of a Rp pull up resistor between the CC line and the 5 V supply.

As the plug is reversible, the two DP/DN couples need to be connected in pairs as close as possible to the receptacle, before being routed to the STM32 device.

Monitoring CC lines through the ADC_IN inputs allow device-attachment detection and enabling of VBUS on the connector.

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Connector receptacle

BUS

STM32 legacy USB2.0 OTG conversion for USB Type-C platforms

Figure 11. Legacy host using USB Type-C receptacle

5V supply

STMPS2151

OUT

BUS

Rp1

56k +/-5%

GND

Rp2

56k +/-5%

BUS

_enable

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STM32x

GPIO

CC1

CC2

DP1

DP2

DN1

DN2

GND

ADC_IN1

ADC_IN2

USB_DP

USB_DN

10.3 STM32 legacy USB2.0 OTG conversion for USB Type-C platforms

This use case explains how to exchange USB2.0 micro-AB receptacle for a USB Type-C® receptacle.

In this use case the platform is designed for USB2.0, so the maximum current capacity is 500 mA. If a higher supply current is available in the application, the Rp resistors can be adjusted to give 1.5 A or 3 A capability.

A legacy OTG platform starts to work as host or device depending on the USB_ID pin impedance to ground provided by the cable.

USB Type-C® is fully reversible, so the cable does not provide any role information. The role needs to be detected by sensing the CC lines (for example by using the ADC through its ADC_IN1 and ADC_IN2 inputs to detect the CC line level).

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STM32 legacy USB2.0 OTG conversion for USB Type-C platforms

Figure 12. Legacy OTG using USB Type-C receptacle

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-A4-B9-A9-B4

BUS

Connector

CC1-A5

CC2-B5

Pmos

Nmos

VDD_3V3

Rp2

36k

Rd2

5.1k

5V supply

Pmos

Power_switch

OUT

Rp1

36k

Rd1

5.1k

Nmos

GND

4.7uF

LDO

Switch_enable

VDD_3V3

CC1

CC2

Rpu3

BUS

VDD_3V3

Rpd3

OTG_FS_DFP_UFP

VDD

GPIO_2

OTG_FS_V

GPIO_1

ADC_IN1

ADC_IN2

STM32xx

BUS

GND-A1-B12-A12-B1

OTG_FS_ID

DP1-A6

DP2-B6

DN1-A7

DN2-B7

OTG_FS_DP

OTG_FS_DM

The suggested sequence is:

1. Connect GPIO1 to OTG_FS_DFP_UFP driving a high level, and GPIO2 to Switch_enable driving a low level, to identify the platform as UFP.

2. If VBUS is detected, the platform starts with the USB2.0 controller acting as a device.

3. If no VBUS is detected after 200 ms minimum, OTG_FS_DFP_UFP is pulled down to be identified as a DFP through the Rp resistors, and to check whether a UFP is connected by comparing the ADC_IN1 and ADC_IN2 voltages to the expected threshold on the CC lines. Power switch X1 is kept disabled.

4. If UFP connection is detected, Switch_enable is pulled up to provide VBUS on the connector, and the platform starts with the USB2.0 controller acting as host.

Because of the plug reversibility, the two DP/DN pairs need to be connected as pairs as close as possible to the receptacle, before routing to the STM32 device.

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Type-C with power delivery using integrated UCPD peripheral

11 Type-C with power delivery using integrated UCPD peripheral

This chapter may not fully apply to STM32 MPU products. Refer to Section 9 Product offer for their specificities.

11.1 Software overview

STMicroelectronics delivers a proprietary USB-PD stack based on the USB.org specification. The stack architecture overview is shown below.

Figure 13. USB-PD stack architecture

USB-PD application

User application

USBPD core stack

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USBPD port partner

USBPD device

Hardware: LL HAL and BSP

Type-C bus

Two parts are fully managed by STMicroelectronics (USBPD core stack and USBPD devices), so the user only needs to focus development effort on two other parts:

• User application part: called the 'Device Policy Manager' inside the USB organization specification. ST delivers an application template to be completed according the application need.

• Hardware part: the effort is mainly focussed on energy management, which depends on the resource materials chosen by the user to manage Type-C power aspects.

This document provides hardware implementation guidelines for the use of the STM32 resources (ADC, GPIO, and so on), but the developers' reference for power constraints is Chapter 7: 'Power Supply' of the Universal Serial Bus Power Delivery Specification.

Also refer to [1] for further information.

AN5225 - Rev 3

page 22/64

11.2 Hardware overview

Using the STM32 UCPD peripheral, flexible and scalable architectures can be achieved. STM32 GP peripherals such as PWM, ADC, DAC, I2C, SPI, UART, COMP, OPAMP, RNG, and RTC can be used. See the STM32CubeMx pinout tools for detailed information.

USART4_RX / PC11

PC12

PC13

PC14-OSC32_IN

PC15-OSC32_OUT

VBAT

VREF+

VDD/VDDA

VSS/VSSA

GPIO_Output / PF0-OSC_IN

GPIO_Output / PF1-OSC_OUT

GPIO_Input / PF2-NRST

GPIO_Input / PC0

GPIO_Input / PC1

GPIO_EXTI2 / PC2

GPIO_EXTI2 / PC3

Figure 14. Device pinout example

PB9

PC10 / USART4_TX

646362

PB7 / USART1_RX

PB6 / USART1_TX

PB3 / COMP2_INM

PB4 / COMP2_INP

PD3 / UCPD2_DBCC2

5352515049

PD4

PD5

PD6

PB5

PB8

LQFP64

2829303132

171819

PD2 / UCPD2_CC2

AN5225

Hardware overview

PD0 / UCPD2_CC1

PC9 / TIM1_CH2

PD1 / UCPD2_DBCC1

PC8 / TIM1_CH1

PA15 / USART2_RX

PA14-BOOT0 / USART2_TX

PA13

PA12 [PA10]

PA11 [PA9]

PA10 / UCPD1_DBCC2

PD9

PD8 / I2S1_CK

PC7

PC6

PA9 / UCPD1_DBCC1

PA8 / UCPD1_CC1

PB15 / UCPD1_CC2

PB14

PB13

PA6

ADC1_IN0 / PA0

ADC1_IN1 / PA1

ADC1_IN2 / PA2

ADC1_IN3 / PA3

I2S1_SD / PA7

DAC1_OUT1 / PA4

DAC1_OUT2 / PA5

COMP1_INM / PC4

PB1

PB2

PB10

PB11

PB12

I2S1_WS / PB0

COMP1_INP / PC5

The following sections show how to implement each power mode from the hardware point of view. All information concerning the software implementation is available in the reference specification.

AN5225 - Rev 3

page 23/64

11.2.1 DBCC1 and DBCC2 lines

Recap of Dead battery functionality in Type-C systems

A USB Type-C sink supporting the Dead battery function keeps pulling the attached CC line(s) down as per

Table 8 even when unpowered. According the USB Type-C standard, this can be implemented as a resistor or a

voltage clamp, as shown in the following table. Thanks to this, the USB Type-C source attached to the sink can detect that the sink is unpowered (which corresponds to dead battery for battery-powered application). The USB Type-C source (for example a battery charger) can then supply power through the VBUS line.

AN5225

Hardware overview

Table 8. USB Type-C sink behavior on CC lines

State

Sink without Dead battery support Sink with Dead battery support

Unpowered

Powered 5.1 kΩ 5.1 kΩ resistor

Pull-down function on CC lines

None

5.1 kΩ resistor or a voltage clamp

(DB)

When the USB Type-C sink is back to powered, it changes the value of its Rd pull-down resistance to one of values specified for normal operation.

Upon transiting from Dead battery state to VBUS-powered state, the Type-C specification requires that the switch of the Rd value from DB to “operating” does not transit through a state without any pull-down resistance. It accepts a short transient during which the value of Rd is out of specified operating values. Refer to Termination parameters section of the USB Type-C specification for full requirements.

Implementation on STM32 devices with integrated UCPD peripheral

The devices incorporate the Rp and Rd function of the CCx (x = 1 or 2) pins to fulfill the USB Type-C requirements. For the Dead battery support, the DBCCx (x = 1 or 2) pins must externally be connected with their respective CCx pins.

Control paths (1) to (3) shown in Figure 15 through Figure 18 manage the switching between Rp and Rd functionality on the CCx pins, according to the application topology and state.

When the STM32 device is unpowered, a voltage exceeding 1 V on the DBCCx pins acting as inputs activates, through the control path (3), the Dead battery pull-down functionality (DB) on their respective CCx pin. It is maintained until the device is powered and the software disables it through the control path (1). The DB disable action activates Rd or Rp value for normal operation that the software application should set beforehand.

When the device is used as USB Type-C source or as a USB Type-C sink without Dead battery support, the DBCCx pins can be used as GPIOs controlled through the control path (2). In such applications, a weak external pull-down resistor (for example 100 kΩ) on the DBCCx pin ensures that DB pull-down functionality is not activated on the corresponding CCx pin when the device is powered down.

AN5225 - Rev 3

DBCCx usage in non-protected application

When the device is unpowered, the DBCCx pins act as inputs. A high level on a DBCCx has the consequence of exposing Rd = DB on the corresponding CCx pin to signal dead battery state. For the device acting as sink to support the Dead battery function when directly connected with a USB Type-C source, the DBCCx pins must be shorted with their corresponding CCx pins. As soon as the device is powered, the Rd exposed on its CCx pins automatically transits to the value defined through the control registers, as shown in Figure 15. The termination in this configuration must be of Rd (pull-down) type.

page 24/64

Figure 15. Non-protected sink application supporting Dead battery feature

USB Type-C

connector

VBUS

Power supply

VDD

AN5225

Hardware overview

CPU

Cortex

(1)

CPU

(software)

(3)

CCx

DBCCx

CCx

USB Type-C

connector

Type-C

STM32

Type-C source

Type-C sink application

Controls

Table 9. Non-protected sink - sequence of exiting Dead battery mode

Sequence

Step 0 0 V 0 V DB -

Step 1 5 V 0 V DB VBUS arrives

Step 2 5 V 3.3 V default Rd device supply arrives

Step 3 5 V 3.3 V as selected by SW upon write to ANAMODE

VBUS VDD Rd value Comment

application

AN5225 - Rev 3

When the device acts as a USB Type-C source, the Rd on CCx pins must never be set to DB value. This is ensured by keeping the DBCCx pins separate from their corresponding CCx pins and by pulling them down through a high-value (such as 100 kΩ) external pull-down resistor, which in the unpowered state ties them low. The solution also fits a non-protected non-Dead-battery sink application.

In both cases, when the device is powered, the DBCCx pins can be used as I/Os, as shown in Figure 16.

page 25/64

Figure 16. Non-protected sink not supporting Dead battery feature

USB Type-C

connector

VBUS

Power supply

VDD

AN5225

Hardware overview

CPU

Cortex

(1)

CPU

(software)

(3)

(2)

CCx

DBCCx

CCx

GPIO / AF

CCx

USB Type-C

connector

Type-C

STM32

Type-C source

Type-C sink application

Controls

DBCCx usage in protected application

A protection circuit (such as TCPP01-M12) can be placed between the STM32 device and the Type-C connector of the application. When active, it separates the device CCx pins from the CCx lines to protect the device against electrical stress such as ESD on the Type-C connector of the application that may be destructive when no or a non-terminated cable is connected. When deactivated, it connects the device CC pins to the Type-C connector.

Typically, the protection circuit is supplied from the VBUS line. It may be activated/deactivated through either a dedicated command or as function of its power supply. In the latter case, it isolates the CCx pin of the device from the Type-C connector when unpowered (protection active), and it couples the CCx pin of the devices with the Type-C connector when powered (protection inactive or bypass).

For applications supporting Dead battery feature, the active protection circuit on a CCx line must expose a Rd = DB to the Type-C connector CCx line. Its activation/deactivation must be based on its powering state (VBUS voltage). As soon as the USB Type-C source provides supply/charging voltage on VBUS, the protection circuit is deactivated (its Rd deconnected and the CCx line connected with the device CCx pin). However, as the STM32 device may not yet be supplied at that instant, it must take over the Dead battery signaling (expose Rd = DB on the CC pin) from the protection circuit. This is why the DBCCx pin must be shorted with the corresponding CCx pin and it cannot be used for other purposes.

The following figure shows a typical application with protection, supporting Dead battery feature.

application

AN5225 - Rev 3

page 26/64

Figure 17. Protected sink application supporting Dead battery feature

USB Type-C

connector

VBUS

Power supply

VDD

AN5225

Hardware overview

CPU

Cortex

(1)

CPU

(software)

(3)

(2)

CCx

DBCCx

CCx

Protection

CCx

USB Type-C

connector

Type-C

STM32

GPIO(s)

Type-C source

Type-C sink application

Controls

The following table shows Dead battery mode exit sequence for a USB Type-C sink application with a protection circuit. The term connected/isolated means CCx pins connected / non-connected with Type-C source CCx lines. The protection circuit state active means protection activated, Rd = DB of the protection circuit exposed to Type-C

source. The protection circuit state bypassmeans protection circuit deactivated, not affecting the CC line and connecting the device CCx pins with the Type-C source CCx lines.

application

Table 10. Protected sink application - sequence of exiting Dead battery mode

Sequence VBUS VDD

Step 0 0 V 0 V active isolated/DB -

Step 1 5 V 0 V bypass connected/DB VBUS arrives

Step 2 5 V 3.3 V bypass connected/ default Rd device supply arrives

Step 3 5 V 3.3 V bypass

Step 4 5 V 3.3 V bypass, low power

Protection circuit

state

Device CC pins/Rd

value

connected / as selected

by SW

connected / as selected

by SW

Comment

upon write to

ANAMODE

upon I2C write to

protection circuit

The protection circuit of applications not supporting Dead battery feature does not incorporate the DB pull-down device.

It can be activated/deactivated based on its supply voltage (Figure 18) or by software through a dedicated input (Figure 19 - control path (4)). The latter allows the device to set up, through the ANAMODE bitfield, the desired Rd value before the protection is deactivated. In both cases, the DBCCx lines can be used as I/Os. The following figures show examples of application topology for either case.

AN5225 - Rev 3

page 27/64

AN5225

Hardware overview

Figure 18. Protected sink application not supporting Dead battery feature - activation through supply

USB Type-C

connector

Power supply

VDD

VBUS

CPU

Cortex

(1)

CPU

(software)

(3)

(2)

CCx

DBCCx

CCx

Protection

CCx

USB Type-C

connector

Type-C

STM32

GPIO(s)

Type-C source

Type-C sink application

Controls

Figure 19. Protected sink application not supporting Dead battery feature - activation through dedicated

input

USB Type-C

connector

VBUS

application

Power supply

AN5225 - Rev 3

CPU

Cortex

VDD

(3)

(1)

(2)

CPU

(software)

(4)

STM32

Type-C sink application

Controls

CCx

DBCCx

GPIO(s)

Protection

CCx

USB Type-C

connector

Type-C

Type-C source

application

page 28/64

Summary of application topologies

The following table lists the principal topologies of USB Type-C application with compatible STM32 microcontrollers.

Protected

No Yes Sink Yes No

No No Sink No Yes

Yes Yes Sink Yes No Protection circuit deactivated when supplied

Yes No Sink No Yes

1. Pertains to CCx line

11.2.2 Sink port

The USB Type-C Power Delivery sink (SNK) port exposes pull-down resistors (Rd) to the CC lines, and it consumes power from the VBUS line (5 V to 20 V and up to 5 A).

From a sink point of view:

Mandatory

• Type-C port asserts Rd (pull-down resistor) on CC lines

• VBUS sensing

• Source detach detection, when VBUS moves outside the vSafe5V range

Optional

• Sink power from VBUS

Optional protection

• OVP as defined by usb.org:

– In the attach state, a sink should measure the VBUS voltage level.

– An STM32 general-purpose ADC can perform this measurement.

• Protection and EMI filtering on CC1, CC2, and VBUS lines. See Section 14 Recommendations

The features are summarized in the following table:

Table 11. Summary of principal Type-C application topologies

Application DBCCx

Dead battery

(1)

compliant

Not

applicable

Sink/source

Source No Yes

Shorted with

CCx

AN5225

Hardware overview

Note

Reusable

Application must ensure low level on DBCCx when the device is unpowered.

Protection circuit deactivated when supplied: the application must ensure low level on DBCCx when the device is unpowered.

Protection circuit deactivated by software: the default Rd is never exposed to Type-C source.

Rp exposed on CCx when the device is powered.

The application must ensure low level on DBCCx when the device is unpowered.

AN5225 - Rev 3

page 29/64

Table 12. Sink features

AN5225

Hardware overview

Feature

Protocol

Communication

channels CC1 and

CC2

Dead battery

VBUS level,

vSafe5V,

measurement

Power

Sink power from

VBUS

Extra Power switch GPIO 1 Power switch

Protection

CC1 and CC2 - - See Section 14 Recommendations Optional

VBus - - See Section 14 Recommendations Optional

Software

Message repetition TIM - -

Message

transmissions

STM32

peripherals

involved

UCPD: CC1,

CC2

UCPD:

DBCC1,

DBCC2

ADC 1

- - DC/DC from VBUS to 3.3 V (VDD)

DMA - -

number

of STM32

pins

2 -

2 - Handles Rd

External components or devices Comments Signal name

Mandatory. Able to

handle Rd and Rp

Resistor divider bridge with or

without op-amp for safety purpose

Mandatory only for

OVP protection

Optional, LDO,

DC/DC, SMPS

MOSFET or power

switch can be use

Used to drive

timing repetition

1200 µs et 900 µs

For TX et RX

Optional,

purpose

transfer

CC1, CC2

DBCC1,

DBCC2

V_SENSE

SNK_EN

CC1 and CC2

on Type-C side

Vbus on Type-

C side

See UM2552

for details

See UM2552

for details

The following architecture schematics explain how to implement various sink modes.

11.2.2.1 VBUS-powered sink

From the STM32 point of view, VDD is generated from VBUS. An external LDO, DC/DC converter, or SMPS is used, and an optional power-switch wire on VBUS can power extra load. The SNK_EN GPIO pin controls this optional power-switch.

Regarding the protocol, two dedicated STM32 UCPD pins, DBCC1 and DBCC2, set Rd on the CC1 and CC2 lines. The DBCC lines must be wired to CC lines. No software action is needed, as Rd is present on the CC lines through the DBCC lines, with or without the STM32 power supply (VDD). After STM32 power-up, the USB-PD software stack switches the resistor connection from the DBCC to the CC lines.

AN5225 - Rev 3

page 30/64

Figure 20. Unprotected VBUS-powered (Dead battery) sink connections

AN5225

Hardware overview

LOAD

Useful only for limiting load at start-up (and during USB suspend)

SNK_EN

Power supply:

DCDC/SMPS/LDO

GPIO

VDD

Resistor

ADCx_INy

DBCC1

VBUS

bridge

V_SENSE

CC1

STM32

(with UCPD)

CC2

VSS

Signal description

• CC1 and CC2 communication channel signals wired to dedicated Type-C connector pins

• The DBCC1 dead-battery signal is wired to CC1. This handles Rd when the STM32 is not powered via the CC1 line.

• The DBCC2 dead-battery signal is wired to CC2. This handles Rd when the STM32 is not powered via the CC2 line.

Optional:

• V_SENSE wired to an ADC through a resistor divider. VBUS voltage measurement for OVP and safety purposes. The software stack, using the HAL_ADC driver, measures the VBUS voltage level.

• SNK_EN signal GPIO connects and disconnects an optional VBUS load.

DBCC2

USB Type-C

receptacle

AN5225 - Rev 3

page 31/64

Time line

Cable Detach Attach Detach

AMS#2(SNK)

Protocol CC SRC side Rp AMS#1(SRC) Rp-1.5 Rp-1.5

3A Rp-1.5

Rd=DBCC

Rd=CC

1.5A

SNK side R d

Rd=DBCC

Power VBU S SRC side 15V

9V vSafe5V

vSafe0V 0V 5V 1.5A 0V

VBUS SNK side 15V

9V vSafe5V

vSafe0V 0V 5V 1.5A 0V

LOAD SNK side 0V 5V 1.5A 0V

GP ios SNK SNK_EN

V_SENSE

SOFTWARE SNK STM32 VDD

BOOT

APPLI USB-PD

State 0 1 2 3 3 3 3 3 3 4 5 6 7 8 9

AN5225

Hardware overview

Figure 21. VBUS-powered sink timeline

The states are described below. Actions in italics are GPIO-based (ADC, IO, and so on):

• State 0: No connection between equipment

– Detach state

– Rp = 1.5A Rd = 5.1K (DBCC pin)

• State 1: Connect cable; VBUS is in Attach state

• State 2: STM32 boot, start application and initialize USB-PD software

• State 3: Port partner starts AMS power negotiation

• State 4: USB-PD: use Rd from CC instead of DBCC

• State 5: SNK detects the attachment

• State 6: USB-PD: Enable load using SNK_EN GPIO and a contract is established

• State 7: USB-PD SW: OVP and safety are looking for V/I VBUS senses

• State 8: Disconnect cable, VBUS is OFF on the sink side

• State 9: Source discharges VBUS to vSafe0V

AN5225 - Rev 3

page 32/64

11.2.2.2 Separately powered sink

The STM32 device is powered from a separate AC/DC or DC/DC converter, SMPS, LDO, or battery, and not from VBUS. An additional load can optionally be powered from VBUS through a power switch controlled by the SNK_EN GPIO.

Regarding the protocol, the CC1 and CC2 lines set Rd. The DBCC1 and DBCC2 lines must be connect to GND.

AN5225

Hardware overview

Figure 22. SNK external power connections

MCU

power

Power source

LOAD

Useful only for limiting load at start-up (and during USB suspend)

Power supply: DCDC/SMPS/

LDO

VDD

STM32

(with UCPD)

VSS

SNK_EN

GPIO

Resistor

bridge

V_SENSE

ADCx_INy

CC1

DBCC1

CC2

DBCC2

VBUS

USB Type-C

receptacle

Signal description

• CC1 and CC2 communication channel signals wired to dedicated Type-C connector pins

• DBCC1 signal wired to GND (as dead-battery mode is not used)

• DBCC2 signal wired to GND (as dead-battery mode is not used)

Optional:

• V_SENSE signal wired to an ADC through a resistor divider

• VBUS voltage is measured for OVP and safety purposes

• The software stack, using the HAL_ADC, measures the VBUS voltage level

SNK_EN signal GPIO pin connects and disconnects an optional VBUS load.

AN5225 - Rev 3

page 33/64

Time line

Cable Detach Attach Detach

AMS#2(SNK)

Protocol C C SRC side Rp AMS#1(SRC)

3A Rp-1.5

1.5A

SNK side R d Rd=CC

Power VBU S SRC side 15V

vSafe5V

vSafe0V 0V 5V 1.5A 9V 1.5A 15V 1.5A 5V 0V

VBUS SNK side 15V

vSafe5V

vSafe0V 0V 5V 1.5A 9V 1.5A 15V 1.5A 5V 0V

15V 9V 5V

LOAD SNK side 0V 0V 5V 1.5A 9V 1.5A 15V 1.5A 5V 0V

GP ios SNK SNK_EN

V_SENSE

SOFTWARE SNK STM32 VDD

BOOT APPLI USB-PD

State 0 1 2 2 2 2 2 2 3 4 5 6 7 8 9

AN5225

Hardware overview

Figure 23. Sink external power time line

The states are described below. Actions in italics are GPIO-based (ADC, IO, and so on)

• State 0: No connection between equipment

– Detach state

– Rp = 1.5 A Rd = 5.1 K (CC pin)

• State 1: Connect cable. VBUS is in Attach state.

• State 2: AMS between SRC and SNK.

• State 3: USB-PD: Enable load using SNK_EN GPIO pin.

• State 4 SNK requests 9 V.

• State 5: USB-PD SW: OVP and safety are looking for V/I Vbus senses.

• State 6: SNK requests 15 V.

• State 7: SNK requests 5 V.

• State 8: Disconnect cable, VBUS is off on the sink side.

• State 9: Source discharge VBUS to vSafe0V.

11.2.3 Source port

The USB Type-C Power Delivery source (SRC) port exposes pull-up resistor (Rp) to the CC lines and it provides power over VBUS (5 V to 20 V and up to 5 A).

From a source point of view:

Mandatory

• Type-C port asserts Rp on CC lines

• Feed power to VBUS

• During detach or communication failure, the source reduces VBUS to vSafe0V.

An STM32 GP GPIO discharges VBUS using an external MOSFET.

Optional

• An STM32 GP ADC can do these measurements using a shunt or resistor bridge

Optional protection

AN5225 - Rev 3

page 34/64

AN5225

Hardware overview

• Protection and EMI filtering on CC1, CC2 and V

lines. See Section 14 Recommendations.

BUS

The features are summarized in Table 13.

Table 13. Source features

Feature

Protocol

CC1 and CC2

communication

channels

Dead Battery

support

VBUS level,

vSafe0V,

measurement

Power

Provide power from

VBUS

Discharge VBUS to

vSafe0V

ISense

measurement

CC1 and CC2 See Section 14 Recommendations

Protection

VBUS - - See Section 14 Recommendations -

Software

Message repetition TIM - -

Message

transmissions

STM32

Peripherals

involved

UCPD:

CC1, CC2

UCPD:

DBCC1,

DBCC2

ADC 1

GPIO 1 Power switch

GPIO 1 MOSFET + charge resistors Mandatory SRC_DISCH

ADC 1 Op-amp + shunt resistors Optional I_SENSE

DMA - -

Number

of STM32

pins

2 - Mandatory

External components or devices Comments Signal name

Resistor bridge with or without op-

amp for safety purpose

Optional V_SENSE

Mandatory,

Dual-MOSFET

can be used

CC1 and CC2 on

Type-C side

VBUS on Type-C

Used to drive

timing repetition

1200 µs et 900

µs

For TX et RX

transfer

See [1] for details

CC1

CC2

DBCC1

SRC_EN

side

AN5225 - Rev 3

Figure 24 explains how to handle Source (SRC) mode. From the STM32 point of view, power is provided by an

external source such as an AC/DC, DC/DC, SMPS, LDO, or battery.

Rp management is handled by the UCPD software stack. In this case, the DBCC lines must not be wired to the CC1 and CC2 lines. The DBCC1 and DBCC2 pins are wired to GND.

page 35/64

Figure 24. Source architecture

AN5225

Hardware overview

MCU

power

Power source

VBUS power

GPIO

DC-DC

5V / 9V / 15V

Power supply:

DCDC/SMPS/LDO

VDD

STM32

(with UCPD)

DAC / ADC

GPIO

SRC_EN

VSS

CC1

DBCC1

CC2

DBCC2

ADCx_INx

V and I

sensing

USB Type-C

receptacle

ADCx_INy

VBUS

SRC_DISCH

Note that the VCONN circuit is not shown in this figure. See Section 13.1 Sourcing power to VBUS.

Signal description

• CC1 and CC2 communication channel signals wired to dedicated Type-C connector pins

• the DBCC1 signal is wired to GND

• the DBCC2 signal is wired to GND

Optional:

• V_SENSE signal wired to an ADC through a resistor divider. VBUS voltage measurement for OVP and safety purposes. Software stack, using the HAL_ADC driver to measure the VBUS voltage level.

• In the case of negative VBUS transitions, for example 15 V to 5 V or 9 V to 5 V, a discharge path can be used before the load switch (controlled by SRC_EN) to reduce the time needed for this transition and to stay in specification.

AN5225 - Rev 3

page 36/64

Time line

Cable Detach Attach Detach

AMS#2(SNK)

Protocol CC SRC side Rp AMS#1(SRC)

3A Rp-1.5

1.5A

SNK side Rd Rd=CC

Power VBUS SRC side 15V

9V vSafe5V

vSafe0V 0V 5V 1.5A 0V

VBUS SNK side 15V

9V vSafe5V

vSafe0V 0V 5V 1.5A 0V

GP ios SRC SRC_EN

DISCH

V_SENSE

I_SENSE

SOFTWARE SRC STM32 VDD

BOOT APPLI USB-PD

State 0 1 2 2 2 2 2 2 3 4 5

AN5225

Hardware overview

Figure 25. SRC (source) mode power timings

The states are described below. Actions in italics are GPIO-based (ADC, IO, and so on):

• State 0: No connection between equipment

– Detach state

– Rp = 1.5 A, Rd = 5.1 KΩ (CC pin)

• State 1: Connect cable. VBUS is on

– Attach state

– USB-PD switches on VBUS using the SRC_EN GPIO pin

– Capability exchange

• State 2: AMS between SRC and SNK

• State 3: USB-PD SW: OVP and safety are looking for V/I VBUS senses

• State 4: Disconnect cable, VBUS is OFF on the sink side

– USB-PD initiates VBUS discharge using the DISCH GPIO pin, until VBUS reaches vSafe0V

• State 5: Source VBUS discharged to vSafe0V

AN5225 - Rev 3

page 37/64

11.2.4 Dual-role power port

Dual-role power (DRP) port refers to a USB Power Delivery port that can operate as either a source or a sink. The role of the port is fixed to either source or sink, or may alternate between the two port modes. Initially, when operating as a source, the port also takes the DFP role, and when operating as a sink, the port takes the UFP role. The port role may be changed dynamically to reverse either power or data roles.

From a dual-role power port point of view:

Mandatory:

• Type-C port asserts Rp on CC lines when in source mode

• Type-C port assert Rd on CC lines when in sink mode

• Feed power to VBUS

• During detach or communication failure, the source takes VBUS down to vSafe0V

– An STM32 GP GPIO discharges VBUS using an external MOS

Optional:

• Measure VBUS voltage and current values

– A STM32 GP ADC can do this measurement using a shunt, or a resistor bridge

• Get power from VBUS

• Source 'detach' detection, when VBUS moves outside vSafe5V range

• Manage fast role swap (FRS) protocol. (USB-PD 3.0 only)

Optional protection:

• Protection and EMI filtering on CC1, CC2 and VBUS lines. See Section 14 Recommendations

The features are summarized in Table 14:

AN5225

Hardware overview

Table 14. Dual-role power port features

Feature

Protocol

CC1 and CC2

communication

channels

Dead Battery

VBUS Level, vSafe0V,

vSafe5V ,

measurements

Fast Role Swap

On Power level - - - - -

Provide power from

VBUS

Extra Power switch GPIO - Power switch

Discharge VBUS to

vSafe0V

ISense measurement ADC 1

STM32

Peripherals

involved

UCPD:

CC1, CC2

UCPD:

DBCC1, DBCC2

ADC 1

UCPD:

FRSTX1,

FRSTX2

GPIO 1 Power switch

GPIO 1

Number of

STM32 pins

2 -

External components

or devices

Resistor divider bridge

with or without op-Amp

for safety purpose

MOS to drive CC lines

to GND

MOS + charge

Resistors

OpAmp + shunt

Resistors

Comments Signal name

Mandatory

Able to handle Rd

& Rp

Mandatory

Wire to GND

Mandatory for OVP

protection purpose

Mandatory

Mandatory, MOS

can be use

Optional, MOS can

be use

Mandatory SRC_DISCH

Optional I_SENSE

CC1

CC2

DBCC1

V_SENSE

FRSTX1

FRSTX2

SRC_EN

SNK_EN

AN5225 - Rev 3

page 38/64

AN5225

Hardware overview

Feature

STM32

Peripherals

involved

Number of

STM32 pins

External components

or devices

Comments Signal name

Protection

CC1 and CC2 - - See chapter xxx Optional

VBUS - - See chapter xxx Optional

Software

same as previous - - - - -

Figure 26 shows the connections used in DRP mode.

Figure 26. DRP connections

LOAD

Useful only for limiting load at start-up (and during USB suspend)

sensing

VBUS

CC1 and CC2 on

Type-C side

VBUS on Type-C

side

MCU

power

Power source

VBUS power

DCDC/SMPS/LDO

VDD

STM32

(with UCPD)

GPIO

DAC / ADC

DC-DC

5V / 9V / 15V

GPIO

V_SENSE

VSS

CC1

DBCC1

CC2

DBCC2

ADCx_INx

V and I

sensing

SNK_EN

GPIO ADCx_INw

SRC_EN

USB Type-C

receptacle

ADCx_INy

AN5225 - Rev 3

SRC_DISCH

page 39/64

Hardware overview

Note that the VCONN circuit is not shown in this figure. See Section 13.1 Sourcing power to VBUS.

The signal descriptions are given in Section 11.2.2 Sink port and Section 11.2.3 Source port.

Time line

Figure 27. DRP with FRS mode time line example

AN5225

The steps in italics are based on GPIOs (ADC, IO, and so on).

• State 0: No connection between equipment

– Detach state

– DRP = SRC role Rp = 1.5 A (CC pin)

• State 1: USB-PD stack decide to move from SRC to SNK role

– DRP = SNK role Rd = 5.1K (CC pin)

• State 2: USB-PD stack decide to move from SNK to SRC role

– DRP = SRC role Rp = 1.5A (CC pin)

• State 3: USB-PD stack decide to move from SRC to SNK role

– DRP = SNK role Rd = 5.1K (CC pin)

AN5225 - Rev 3

page 40/64

11.2.5 Dual-role power port with FRS

In this configuration, the STM32 device is supplied from a separate source such as an AC/DC or DC/DC converter, SMPS, LDO, or battery. The UCPD peripheral handles Rp and Rd through software. The power role, source or sink, can be changed on-the-fly without any cable disconnect when both devices are DRP ports.

Fast role swap (FRS) function allows any source with sudden power loss (for example mains power) to signal the condition to a sink with fast role swap capability far more rapidly than without FRS. As FRS signaling/detection works during messaging and regardless of the collision control, it takes no longer than 50 µs. Once the sink detects the FRS signaling, it prepares to detect the VBUS level drop. Then it switches its role to SRC, taking over the VBUS drive within a delay (for example 150 µs) specified by the FRS procedure.

Figure 28. DRP with FRS VBUS = 5 V / 9 V / 15 V connections

AN5225

Hardware overview

MCU

power

Power source

VBUS power

LOAD

Useful only for limiting load at start-up (and during USB suspend)

DCDC/SMPS/LDO

VDD

STM32

(with UCPD)

GPIO

DAC / ADC

DC-DC

5V / 9V / 15V

sensing

SNK_EN

GPIO ADCx_INw

SRC_EN

GPIO

V_SENSE

VSS

CC1

DBCC1

FRSTX_1

CC2

DBCC2

FRSTX_2

ADCx_INx

V and I

sensing

VBUS

USB Type-C

receptacle

ADCx_INy

AN5225 - Rev 3

SRC_DISCH

Note that the VCONN circuit is not shown in this figure. See Section 13.1 Sourcing power to VBUS.

Signal description

• The CC1 and CC2 communication channel signals wired to dedicated Type-C connector pins

page 41/64

Cable Detach Attach Detach

Protocol C C SRC side Rp

3A Rp-1.5 COM FRS COM COM COM COM Rp-1.5

1.5A

SNK side Rd Rd=CC Rd=CC

Power VBUS DRP1 side 15V

9V vSafe5V

vSafe0V 0V 5V 1.5A vSafe0V 5V 1.5A 0V

LOAD DRP1 side 0V 5V 1.5Amax 0V

VBUS DRP2 side 15V

9V vSafe5V

vSafe0V 0V 5V 1.5A 0V 5V 1.5A vSafe0V

LOAD DRP2 side 0V 5V 1.5Amax OV

GP ios DRP1 SRC_EN ACT AS SOURCE

SNK_EN ACT AS SINK

DISCH

V_SENSE

I_SENSE

DRP2 SRC_EN ACT AS SOURCE

SNK_EN ACT AS SINK

DISCH

V_SENSE

I_SENSE

SOFTWARE DRP1 STM32 VDD

BOOT APPLI USB-PD

DRP2 STM32 VDD

BOOT APPLI USB-PD

State 0 1 2 3 4 5 6 7 8 9 10 11

AN5225

Hardware overview

• The DBCC1 signal is wired to GND.

• The DBCC2 signal is wired to GND.

• The SRC_EN signal GPIO pin is used to switch-on VBUS using an external MOSFET or power switch.

• The SRC_DISCH signal GPIO pin initiates the discharge of VBUS on detach. An external MOSFET can be used.

• The FRSTX1 and FRSTX2 fast role swap signals are wired to external MOSFETs to drive the CC lines.

• The V_SENSE signal is wired to an ADC through a resistor divider. The VBUS voltage measurement for OVP and safety purpose. The software stack, using the HAL_ADC driver, measures the VBUS voltage level.

• The I_SENSE signal is wired to an ADC through a resistor shunt. VBUS current measurement for safety purposes. The software stack, using the HAL_ADC driver, measures the VBUS current level.

• The SNK_EN signal GPIO pin is used to connect and disconnect an optional VBUS load.

Time line

Figure 29. DRP with FRS - time line example

AN5225 - Rev 3

The steps in italics are based on GPIOs (ADC, IO, and so on)

• State 0: No connection between equipment

– Detach state

– Rp = 1.5A Rd = 5.1K (CC pin)

page 42/64

• State 1: Connect cable

– VBUS is on DRP1 set SRC_EN GPIO pin

• State 2: Capabilitiy exchanges

– DRP2 switches the on load on V

using the SNK_EN GPIO pin

BUS

• State 3: FRSTX (fast role swap) start

• State 4: DRP1 moves V

to vSafe0V

BUS

• State 5: The DISXH GPIO pin initiates the DRP1 discharge

• State 6: End of V

discharge

BUS

• State 7: Role swap between DRP1 and DRP2

• State 8: DRP2 enables V

• State 9: DRP1 uses the SNK_EN GPIO pin on the V

using the SRC_EN GPIO pin

BUS

load ON

• State 10: Disconnect cable

• State 11: End of discharge

AN5225

Hardware overview

AN5225 - Rev 3

page 43/64

AN5225

Type-C with power delivery using a general-purpose peripheral

12 Type-C with power delivery using a general-purpose peripheral

This chapter may not fully apply to STM32 MPU products. Refer to Section 9 Product offer for their specificities.

12.1 Software overview

The software architecture is the same as that described in Section 11.1 Software overview.

12.2 Hardware overview

Figure 30. Hardware view for Type-C power delivery with a general-purpose peripheral

AN5225 - Rev 3

Using a general-purpose peripheral, the TCPM/TCPC interfaces are a convenient way of handling USB power delivery. STM32 MCUs and STM32 MPUs using a communication bus can handle all TCPM/TCPC companion chips.

Usually the I2C, SPI or GPIOs are used to handle communication messages and exceptions.

page 44/64

12.2.1 Sink port using TCPM/TCPC interface

In sink (SNK) mode, the Type-C port must expose Rd (pull-down resistor) on CC lines, and takes power from VBUS. The sink detects source attachment when VBUS reaches vSafe5V. Detection requires an ADC for example.

The STM32 communicates with the TCPM/TCPC interface, typically using the I2C bus. In some cases an SPI, ADC, DAC, or GPIO completes the communication between the STM32 general-purpose MCU and the TCPM/ TCPC external component.

Figure 31. Sink port using TCPM/TCPC interface

AN5225

Hardware overview

power

Power

source

MCU

LOAD

DCDC/SMPS/

LDO

LDO -> 3.3

VDD

STM32

(TCPM)

I2C

GPIO

VDD

SNK_EN

TCPC

VBUS

sensing

ADC

CC1

CC2

USB Type-C

receptacle

AN5225 - Rev 3

page 45/64

12.2.2 Source port using TCPM/TCPC interface

In source (SRC) mode, the Type-C port must expose Rp (pull-up resistor) to the CC lines and provide power through VBUS. During detach or communications failures, the source must reduce VBUS to vSafe0V. This means that a device must discharge VBUS.

The STM32 (acting as TCPM) usually communicates with TCPM/TCPC interfaces using the I2C bus. In some cases an SPI, ADC, DAC, or a GPIO complete the communication between the STM32 general-purpose MCU and TCPM/TCPC external components.

Figure 32. Source mode using TCPM/TCPC interface

TCPC power

MCU power

DCDC/SMPS/

LDO

VDD

AN5225

Hardware overview

USB Type-C

receptacle

CC1

Power source

VBUS

STM32

(TCPM)

ADC/ DAC

GPIO DAC

5 V/9 V/15 V

VDD

DC-DC

GPIO

I2C

SPI

GPIO

ADC

DAC

GND

SRC_EN

TCPC

ADC

V/I

sensing

CC2

SRC_DISCH

ADC

VBUS

AN5225 - Rev 3

page 46/64

12.2.3 Dual-role power port using TCPM/TCPC interface

A dual-role power (DRP) port can operate as either a source (SRC) or a sink (SNK). The role of the port can be fixed to either source or sink, or it can alternate between the two port states. Initially when operating as a source, the port also takes role of a downstream facing port (DFP), and when operating as a sink, the port takes the role of an upstream facing port (UFP). The port role may change dynamically to reverse either power or data roles.

The STM32 usually communicates with the TCPM/TCPC interface using the I2C bus. In some cases, an SPI, ADC, DAC, or GPIO completes communications between the STM32 general-purpose MCU and the TCPM/ TCPC external component.

Figure 33. Dual-role power port using TCPM/TCPC interface

LOAD

TCPC power

MCU

power

DCDC/SMPS/

LDO

VDD

SNK_EN

sensing

ADC

AN5225

Hardware overview

USB Type-C

receptacle

VBUS

CC1

Power source

VBUS power

VDD

STM32

GPIO DAC

DC-DC

5 V/9 V/15 V

I2C

SPI

GPIO

ADC

DAC

GND

TCPC

SRC_EN

ADC

V/I

sensing

CC2

SRC_ DISCH

ADC

VBUS

AN5225 - Rev 3

page 47/64

Dedicated architecture proposals and solutions

13 Dedicated architecture proposals and solutions

This chapter may not fully apply to STM32 MPU products. Refer to Section 9 Product offer for their specificities.

13.1 Sourcing power to VBUS

SRC port and DRP acting as Power Delivery source provide power to the VBUS line. Commonly used power stages include DC/DC converter, AC/DC converter, and switched-mode power supply (SMPS), with or without a battery. A power switch connects their output (VOUT) to the VBUS line. The general-purpose STM32 ADC, DAC, GPIO, and I2C peripherals allow flexible and scalable power stage control, as shown in the following figure.

Figure 34. Sourcing power to VBUS

Power switch

VIN

AC/DC DC/DC

SMPS

VOUT

AN5225

VBUS

VREF

DAC/

PWM

I_SENSE

ADCx_INy

Error

ENABLE

GPIO

CONTROL

I2C

GPIO

SRC_EN

STM32

general-purpose

ADCx_INy

V_SENSE

Signal description

• ADC: VBUS voltage and current measurement

• GPIO: power switch control, power stage enable, error sensing

• PWM or DAC: voltage reference to the power stage

• I2C: digital control of a power stage with I2C-bus.

In a STM32G0 implementation, the DC/DC converter is driven by a PWM generated with a timer (available in the STM32,). The aim is to determine the PWM corresponding to the requested voltage. An iteration algorithm estimates the target PWM, and a voltage measurement confirms whether the expected value is reached.

VBUS sense

13.2

AN5225 - Rev 3

DC/DC output control with GPIOs

Control through a resistor bridge switched with GPIOs

The VREF line voltage is set with a resistor bridge dividing the VOUT line voltage. The division ratio is switched to the desired value with open-drain GPIOs, as shown in the following figure.

page 48/64

AN5225

DC/DC output control with GPIOs

VIN

Figure 35. Setting V

VOUT

with a switched resistor bridge

Ref

STM32

DC/DC

VREF

converter

open-drain

GPIO1

open-drain

GPIO2

Control with a GPIO acting as a PWM output

The VREF line voltage is set with a resistor bridge R1/R2 dividing the VOUT line voltage, and with an open-drain PWM GPIO output connecting the bottom of the resistor bridge to ground during a portion of time defined with the duty cycle. The voltage in the middle point of the resistor bridge is smoothed to its mean level with a capacitor that forms, with the resistors of the resistor bridge, a low-pass RC filter. Varying the PWM duty cycle varies the VOUT line voltage.

VIN

DC/DC

converter

Figure 36. Setting V

VOUT

VREF

with a PWM GPIO

Ref

STM32

PWM

open-drain

GPIO

clk

AN5225 - Rev 3

page 49/64

AN5225

Applying VCONN on CC lines

13.3 Applying V

An SRC port or a DRP playing the role of source must support VCONN function in the following cases:

• to supply or draw more than 3 A

• to support USB3

A single V the CC1 or CC2 pin, and, simultaneously, two MOSFETs isolate the STM32 UCPD CC1 and CC2 pins from the

CC lines. Two FRS commutation MOSFETs discharge the CC lines when the power switches stop applying V

CONN

This implies the use of at least two GPIOs to control VCONN_EN1 and VCONN_EN2, as shown in the following figure.

CONN

to the CC lines.

on CC lines

CONN

voltage generator is present in the system. Two power switches apply the V

Figure 37. Applying V

DC-DC

5 V

VCONN_EN1

CC1

DBCC1

CONN

Power

switch 1

on CC lines

CONN

Power

switch 2

CONN

Type-C

CC1

CONN

USB

(5 V) to either

STM32

FRSTX1

UCPD

VCONN_EN2

CC2

DBCC2

FRSTX2

Signal description

Two GPIOs (shown as VCONN_EN1 and VCONN_EN2 in the figure) control the switch to apply V lines and the simultaneous isolation of the STM32 CC pins from the CC lines.

For software details, see [1].

CC2

CONN

to the CC

AN5225 - Rev 3

page 50/64

13.3.1 Time line

Cable Detach Attach Detach

AMS#2(SNK) C OMM

Protocol C C SRC side Rp AMS#1(SRC)

3A Rp-1.5

1.5A

SNK side Rd R d=CC

VCONN CC 2 SRC side Rp

3A Rp-1.5

1.5A

SNK side Rd R d=CC 5V 1A

Power VBU S SRC side 15V

9V vSafe5V

vSafe0V 0V 5V 1.5A 0V

VBUS SNK side 15V

9V vSafe5V

vSafe0V 0V 5V 1.5A 0V

GP ios SRC SRC_EN

DISCH

V_SENSE

I_SENSE

VCONN_EN1

FRSTX1

Discharge Vconn

SOFTWARE SRC STM32 VDD

BOOT APPLI USB-PD

State 0 1 2 3 4 5 6 7 8 9

AN5225

Applying VCONN on CC lines

Figure 38. Applying V

- time line example

CONN

The sequence is as follows, where actions in italics are based on GPIOs (ADC, IO, and so on):

• State 0: No connection between equipment

– Detach state

– Rp = 1.5A Rd = 5.1K (CC pin)

AN5225 - Rev 3

• State 1: Connect cable. VBUS is turned on using the SRC_EN GPIO. Attach state.

– USB-PD switch on VBUS using SRC_EN GPIO pin

– capabilities exchanged

• State 2: Request VCONN ON

• State 3: Enable VCONN using VCONN_EN1/2 GPIOs

• State 4: USB-PD SW: OVP and safety are looking for V/I VBUS senses

• State 5: Request VCONN ON

• State 6: Disable VCONN using VCONN_EN1/2 GPIOs

– Start discharging CC1/2 line using FRSTX pin or a GPIO

• State 7: Disconnect cable, VBUS is OFF on the sink side

– USB power delivery uses the DISCH GPIO pin to initiate the VBUS discharge until the VBUS voltage

reaches vSafe0V

• State 8: The VBUS voltage reaches vSafe0V

page 51/64

13.4 FRS signalling

FRS signaling is only required for Type-C DRP role swapping. Only a DRP operating as a power source optionally sends FRS signals on power-outage detection.

FRS signaling (TX): UCPD peripheral requires external hardware to pull the CC line strongly to GND

• This implies two external NMOS transistors, controlled by the STM32 UCPD peripheral

• One per CC line, controlled with GPIO set to the corresponding FRSTX1 or FRSTX2 AF

FRS detection (RX): The detection of FRS signaling is internal. It can be enabled by software.

• Software uses a UCPD interruption.

The UCPD peripheral provides a control bit (FRSTX) that is available through alternate-function multiplexing. It is only written to 1 to start the 'FRS signaling' condition. The condition is auto-cleared in order to respect the required timing. See the relevant STM32 MCU or MPU product datasheet for further details. This behavior is introduced in Power Delivery3.0, is optional, and only applies to DRP roles. It allows a fast solution to swap power roles for a source that loses its ability to supply power.

A DRP in source (SRC) mode signals 'FRS' as an alert condition in order to swap power roles (that is, the VBUS source) as quickly as possible. Typically, this is useful in the absence of a local battery.

When the VCONN feature is used, FRSTX1 and FRSTX2 discharge the CC1 and CC2 lines through MOSFETs.

AN5225

FRS signalling

Figure 39. Fast role-swap DRP mode circuit

STM32

CC1

CC2

FRSTX1

FRSTX2

Type-C

CC1

CC2

AN5225 - Rev 3

page 52/64

Monitoring VBUS voltage and current

13.5 Monitoring VBUS voltage and current

Protection and safety

A DC/DC converter circuit, such as the L7987, is used to generate VBUS and VCONN, and includes built-in OTP / OVP / OCP generation. These errors can be handled in software at the user application level for safety purposes. To do this, the DC/DC fault output signal can be routed to EXTI on the STM32 side.

PD protocol

A SNK port or a DRP in the role of power sink measures the VBUS level to handle REQUEST_ACCEPT / PS_RDY / DETACH protocol messages on the software side. For this purpose, one ADC is required on the STM32 side.

A SRC port or a DRP in the role of power source provides power to the VBUS and keeps its voltage within the specified target (through monitoring it and controlling the DC/DC converter), for PDO or APOD uses cases.

Method

To measure the VBUS current, use a low resistance shunt. To measure VBUS voltage, use a basic resistor bridge. Optionally add an operational amplifier for OVP and safety purposes.

Note: TSC2011 and TSC2012 precision bidirectional current sense amplifier can be used. See datasheets on

www.st.com.

AN5225

Figure 40. VBUS voltage and current monitoring circuit

STM32

ADC

Isense

Vsense

VBUS

Rs = Shunt R1, R2 = Resistor bridge

Type-C receptacle

VBUS

GND

Note: Extra protection can be added on Isense and Vsense. See Section 14 Recommendations.

AN5225 - Rev 3

page 53/64

14 Recommendations

AN5225

Recommendations

14.1

Note: SBU may be left open if no Alternate Mode is supported. When Alternate Mode is supported, add a resistor

ESD/EOS protection devices for USB Type-C

Dedicated ESD and EOS protection can be used on:

• VBUS power delivery signals

• D+/D-, TX/RX Super-speed and High-speed signals

• CC communication channel signals

• SBU side-band usage signal

superior to 4 MΩ to ensure USB Safe state.

For further information, refer to [4] and to www.st.com (search Type-C protection).

Table 15. Recommended protection devices

Function Device

3.3 V SMLVT3V3

Power supply

User push button

Joystick ESDA6V1-5SC6 (five lines)

5 V DSDA7P120-1U1M

9 to 12 V ESDA15P60-1U1M

ESDALC6V1-1U2 (one line, pitch 350 µm)

ESDA5V3L (two lines)

14.2

TVS must be selected according to the voltage on the VBUS (that can be higher than 5 V):

• ESDA7P120-1U1M for 5 V VBUS

• ESDA13P70-1U1M for 9 V VBUS

• ESDA15P60-1U1M for 12 V VBUS

• ESDA17P50-1U1M for 15 V VBUS

• ESDA25P35-1U1M for 20 V VBUS

Capacitors on CC lines

The USB PD specification allows CC receiver (cReceiver) capacitance in the range of 200 pF to 600 pF.

For noise filtering purposes, an extra 390 pF +/- 10% capacitance must be added on each CC line.

AN5225 - Rev 3

page 54/64

14.3 TCPP01 Type-C port protection device

Two Type-C power delivery failure modes are identified:

• VBUS high voltage short circuit to the CC lines when a unplug is done with a poor mechanical quality connector. Over voltage protection is needed on the CC line. This use case appears only when power delivery is used.

• VBUS line compromised if a defective charger is stuck at a high voltage. Overvoltage protection is needed on the VBUS line. This use case can occur even when power delivery is not used.

A dedicated single chip can be used for system protection. The TCPP01-M12 is a cost effective solution to protect low-voltage MCUs or other controllers performing USB Type-C Power Delivery management of a power sink. The TCPP01-M12 provides 20 V short-to-VBUS over-voltage and IEC ESD protection on CC lines, as well as programmable over-voltage protection with an NMOS gate driver for the VBUS line.

The TCPP01-M12 also integrates dead battery management, and can be completely turned off for batterypowered devices. A fault report is also generated.

TVS is still required on VBUS (ESDA25P35-1U1M), and then only the maximum voltage is considered.

14.3.1 Sink applications

The following figure shows a sink application drawing all its power from the USB Type-C connector VBUS line.

Figure 41. Entirely VBUS-powered sink

AN5225

TCPP01 Type-C port protection device

GATE

TCPP01-M12

GND

T1 N-MOSFET STL11N3LLH6

SOURCE

VCC

FLT

DB/

CC1

CC2

LDO

3.3 V

GPIO2*

GPIO1

CC1

CC2

* Not mandatory

D1 TVS

ESDA25P35-1U1M

VBUS

USB-C connector

CC1

CC2

GND

IN_GD

VBUS_CTRL

CC1c

CC2c

• FLT (FAULT) is an open-drain output pin.

• DB/ is a pull-down TCPP input. Connect it to 3.3 V if not managed by the MCU software.

VCC

STM32

UCPD Low-

voltage

power

delivery

controller

GND

ADC

DBCC1

DBCC2

AN5225 - Rev 3

page 55/64

TCPP01 Type-C port protection device

Figure 42. Sink application with battery (PD3.0)

AN5225

T1 N-MOSFET STL11N3LLH6

GATE

TCPP01-M12

GND

SOURCE

VCC

FLT/

DB/

CC1

CC2

management

ADC

GPIO1

GPIO3*

GPIO2

CC1

CC2

* Not mandatory

D1 TVS

ESDA25P35-1U1M

VBUS

USB-C connector

CC1

CC2

GND

IN_GD

VBUS_CTRL

CC1c

CC2c

• FLT (FAULT) is an open-drain output pin.

• DB/ is a pull-down TCPP input. Connect it to 3.3 V if not managed by the MCU software.

Power

OUT

3.3 V

VDD

STM32

UCPD Low-

voltage power

delivery

controller

GND

DBCC1

DBCC2

Figure 43. 15 W sink application with battery

* Not mandatory

D1 TVS ESDA25P35-1U1M

VBUS

USB-C connector

CC1

CC2

GND

IN_GD

VBUS_CTRL

TCPP01-M12

CC1c

CC2c

GATE

GND

T1 N-MOSFET

STL11N3LLH6

SOURCE

VCC

DB/

FLT

CC1

CC2

5.1 kohm

GPIO1

GPIO2*

ADC1

ADC2

5.1 kohm

Power

management

ADC

VDD

STM32

UCPD

Low-voltage

Power delivery

controller

GND

OUT

3.3 V

• FLT (FAULT) is an open-drain output pin, to leave open if not connected.

• When GPIO1 is low, TCPP01-M12 is OFF with zero current consumption.

• When GPIO1 is low, TCPP01-M12 is ON with ADC1 or ADC2 checking the source capability.

AN5225 - Rev 3

page 56/64

In dead battery condition, the following sequence applies:

1. TCPP01-M12 presents a DB clamp (1.1 V) on CC1 and CC2 lines.

2. The source detects the clamp presence and applies 5 V on VBUS.

3. N-MOSFET T1 is normally ON and the power management block is supplied with 5 V.

4. The MCU wakes-up, and applies 3.3 V on GPIO1 to wake up TCPP01-M12.

5. TCPP01-M12 releases the clamp on the CC1 and CC2 lines so that ADC1 or ADC2 can sense the SOURCE pin capability with the voltage across R5 or R6.

14.3.2 Handling dead battery condition

The DB/ (dead battery resistor management) pin is a pulled-down active-low TCPP01 input. The DB/ pin can either be connected to VCC or driven by an MCU GPIO.

As long as the DB/ input is low (connected to ground or left open and tied low through a built-in 5 kΩ pull-down resistor), the dead-battery resistors are connected and CC switches are opened (OFF state).

When the DB/ pin is tied to VCC, the DB resistors on the CC pins are disconnected and CC switches are closed (ON state).

DB/ usage (sink application):

• After system power-up, the DB/ pin must be kept low, which activates DB Rd of TCPP01.

• Once the DB Rd is enabled on STM32 CC pins, the DB/ pin must be set high.

AN5225

TCPP01 Type-C port protection device

AN5225 - Rev 3

page 57/64

15 Additional information

The USB Power Delivery protocol over CC lines is defined as an extension to both USB2.0 and USB3.1, and only applies to the use of the Type-C connector.

Protocol purpose

The purpose of this protocol is to negotiate the power capabilities and power requirements of the devices connected through a USB Type-C® cable, in order to safely deliver power from the power source device to the

power sink device.

The protocol combined with the Type-C connection allows the increase of the maximum power delivery to 100 W (5 A at 20 V).

The power delivery role (source or sink) is dissociated from the upstream/downstream-facing port roles. For example, a USB device/hub (upstream-facing port) can deliver power to the USB host (downstream-facing port). During the initial connection, the UFP is the sink and the DFP is the source. Both role pairs (source/sink and UFP/ DFP) can be swapped over the Type-C connection.

New Type-C cable additional pins

The new Type-C cable has two additional wires, CC1 and CC2, for configuration control.

Optionally, one of these pins can be configured as a VCONN supply to power an external accessory. In this case, the signalling function of the pin is not available.

AN5225

Additional information

Power Delivery port - pull-up/down resistors

A device acting as a Type-C port supporting Power Delivery protocol must pull the CC line(s) up or down:

• Power source: pull up with Rp equal to one of three specified values, depending on the power requirements of the sink

• Power sink: pull down with Rd equal to a specified value

• Dual-role power port: as power source or power sink, depending on its actual role.

System attach

Once a debounce period has elapsed, the system becomes attached:

• On CC, power delivery messaging can be used for communication over CC lines

– power capabilities, for example beyond 5 V/3 A

– power-role swaps

– data role swaps (similar to HNP in OTG)

– VCONN swap

• On VCONN: on seeing an Ra resistor a 5 V supply must be provided

Single Type-C port pins

• Source/sink/DRP port cases:

– Two CC pins (CC1/CC2) allow for unknown orientation of the cable

• Cable and accessory cases:

– Orientation is pre-determined

– A single CC pin is needed

AN5225 - Rev 3

Dead battery support

Dead battery signalling capability of a Type-C power sink translates into exposing a pull-down resistor of a specified value or a voltage clamp to the CC lines when the power sink device is unpowered. It is interpreted as a request to receive VBUS. It thus facilitates the charging of equipment with a dead battery, and also powering one with no battery.

Type-C power source (such as a wall charger) must not provide dead battery signalling.

page 58/64

Revision history

Table 16. Document revision history

Date Version Changes

24-Apr-2019 1 Initial release.

Updated:

• Section Introduction

• Section 1.2 Reference documents

• Table 7. Fixed and programmable power supply current and cabling

requirements

• Figure 24. Source architecture

• Figure 28. DRP with FRS VBUS = 5 V / 9 V / 15 V connections

26-Sep-2019 2

1-Sep-2020 3

• Figure 37. Applying V

• Figure 41. Entirely VBUS-powered sink

• Figure 42. Sink application with battery (PD3.0)

• Section 14.3.1 Sink applications

• Figure 43. 15 W sink application with battery

Added:

• Figure 8. USB Type-C Power Delivery block diagram and

Figure 9. STM32G0 Discovery kit USB Type-C analyser

• New Figure 26. DRP connections

• New Figure 1

Removed Source and Source/Sink mode description subsections from

Section 14.3 TCPP01 Type-C port protection device.

Updated:

• Section Introduction

• Section 1.2 Reference documents

• Section 5 Power profiles

• Section 9 Product offer

• Section 11 Type-C with power delivery using integrated UCPD

peripheral, Section 11.2 Hardware overview

• Section 12 Type-C with power delivery using a general-purpose

peripheral, Section 12.2 Hardware overview

• Section 13 Dedicated architecture proposals and solutions

• Section 14 Recommendations

CONN

on CC lines

AN5225

AN5225 - Rev 3

page 59/64

AN5225

Contents

1 General information ...............................................................2

1.1 Acronyms and abbreviations .....................................................2

1.2 Reference documents...........................................................3

2 USB Type-C in a nutshell ..........................................................4

2.1 USB Type-C® vocabulary........................................................5

2.2 Minimum mandatory feature set ..................................................5

3 Connector pin mapping............................................................6

3.1 VBUS power options............................................................7

4 CC pins............................................................................8

4.1 Plug orientation/cable twist detection ..............................................8

4.2 Power capability detection and usage ............................................10

5 Power profiles ....................................................................11

6 USB power delivery 2.0 ...........................................................12

6.1 Power delivery signaling........................................................12

6.1.1 Packet structure ........................................................12

6.1.2 K-codes...............................................................12

6.2 Negotiating power .............................................................13

7 USB power delivery 3.0 ...........................................................14

8 Alternate modes ..................................................................15

8.1 Alternate pin re-assignments ....................................................15

8.2 Billboard .....................................................................16

9 Product offer .....................................................................17

10 Type-C with no power delivery ....................................................19

10.1 STM32 USB2.0-only device conversion for USB Type-C platforms ....................19

10.2 STM32 USB2.0 host conversion for USB Type-C platforms ..........................19

10.3 STM32 legacy USB2.0 OTG conversion for USB Type-C platforms....................20

11 Type-C with power delivery using integrated UCPD peripheral .....................22

11.1 Software overview.............................................................22

11.2 Hardware overview ............................................................23

AN5225 - Rev 3

page 60/64

AN5225

Contents

11.2.1 DBCC1 and DBCC2 lines .................................................24

11.2.2 Sink port ..............................................................29

11.2.3 Source port ............................................................34

11.2.4 Dual-role power port .....................................................38

11.2.5 Dual-role power port with FRS .............................................41

12 Type-C with power delivery using a general-purpose peripheral ...................44

12.1 Software overview.............................................................44

12.2 Hardware overview ............................................................44

12.2.1 Sink port using TCPM/TCPC interface .......................................45

12.2.2 Source port using TCPM/TCPC interface .....................................46

12.2.3 Dual-role power port using TCPM/TCPC interface ..............................47

13 Dedicated architecture proposals and solutions...................................48

13.1 Sourcing power to VBUS .......................................................48

13.2 DC/DC output control with GPIOs ................................................48

13.3 Applying V

13.3.1 Time line ..............................................................51

on CC lines ....................................................50

CONN

13.4 FRS signalling ................................................................52

13.5 Monitoring VBUS voltage and current ............................................53

14 Recommendations................................................................54

14.1 ESD/EOS protection devices for USB Type-C®....................................54

14.2 Capacitors on CC lines.........................................................54

14.3 TCPP01 Type-C port protection device ...........................................55

14.3.1 Sink applications........................................................55

14.3.2 Handling dead battery condition ............................................57

15 Additional information ............................................................58

Revision history .......................................................................59

AN5225 - Rev 3

page 61/64

AN5225

List of tables

Table 1. USB Type-C receptacle pin descriptions ....................................................6

Table 2. Power supply options .................................................................7

Table 3. Attached device states - source perspective ................................................. 8

Table 4. DFP CC termination (Rp) requirements.................................................... 10

Table 5. UFP CC termination (Rd) requirements ................................................... 10

Table 6. Voltage on sink CC pins (multiple source current advertisements) ................................. 10

Table 7. Fixed and programmable power supply current and cabling requirements ............................ 11

Table 8. USB Type-C sink behavior on CC lines .................................................... 24

Table 9. Non-protected sink - sequence of exiting Dead battery mode ..................................... 25

Table 10. Protected sink application - sequence of exiting Dead battery mode ................................ 27

Table 11. Summary of principal Type-C application topologies ...........................................29

Table 12. Sink features ..................................................................... 30

Table 13. Source features ....................................................................35

Table 14. Dual-role power port features .......................................................... 38

Table 15. Recommended protection devices ....................................................... 54

Table 16. Document revision history .............................................................59

AN5225 - Rev 3

page 62/64

AN5225

List of figures

Figure 1. USB connectors ...................................................................4

Figure 2. Receptacle pinout ..................................................................6

Figure 3. Pull up/down CC detection ............................................................9

Figure 4. Power profile .................................................................... 11

Figure 5. SOP* signaling ...................................................................12

Figure 6. Pins available for reconfiguration over the Full Featured Cable .................................. 15

Figure 7. Pins available for reconfiguration for direct connect applications ................................. 16

Figure 8. USB Type-C Power Delivery block diagram ............................................... 17

Figure 9. STM32G0 Discovery kit USB Type-C analyser ............................................. 17

Figure 10. Legacy device using USB Type-C receptacle .............................................. 19

Figure 11. Legacy host using USB Type-C receptacle................................................ 20

Figure 12. Legacy OTG using USB Type-C receptacle ............................................... 21

Figure 13. USB-PD stack architecture........................................................... 22

Figure 14. Device pinout example .............................................................23

Figure 15. Non-protected sink application supporting Dead battery feature ................................. 25

Figure 16. Non-protected sink not supporting Dead battery feature ....................................... 26

Figure 17. Protected sink application supporting Dead battery feature..................................... 27

Figure 18. Protected sink application not supporting Dead battery feature - activation through supply ............... 28

Figure 19. Protected sink application not supporting Dead battery feature - activation through dedicated input .........28

Figure 20. Unprotected VBUS-powered (Dead battery) sink connections ................................... 31

Figure 21. VBUS-powered sink timeline ......................................................... 32

Figure 22. SNK external power connections ...................................................... 33

Figure 23. Sink external power time line ......................................................... 34

Figure 24. Source architecture ................................................................ 36

Figure 25. SRC (source) mode power timings ..................................................... 37

Figure 26. DRP connections ................................................................. 39

Figure 27. DRP with FRS mode time line example .................................................. 40

Figure 28. DRP with FRS VBUS = 5 V / 9 V / 15 V connections .........................................41

Figure 29. DRP with FRS - time line example...................................................... 42

Figure 30. Hardware view for Type-C power delivery with a general-purpose peripheral ........................ 44

Figure 31. Sink port using TCPM/TCPC interface ................................................... 45

Figure 32. Source mode using TCPM/TCPC interface................................................ 46

Figure 33. Dual-role power port using TCPM/TCPC interface........................................... 47

Figure 34. Sourcing power to VBUS ............................................................ 48

Figure 35. Setting V

Figure 36. Setting V

Figure 37. Applying V

Figure 38. Applying V

Figure 39. Fast role-swap DRP mode circuit ...................................................... 52

Figure 40. VBUS voltage and current monitoring circuit ............................................... 53

Figure 41. Entirely VBUS-powered sink.......................................................... 55

Figure 42. Sink application with battery (PD3.0) ....................................................56

Figure 43. 15 W sink application with battery ...................................................... 56

with a switched resistor bridge ............................................... 49

Ref

with a PWM GPIO ........................................................ 49

Ref

on CC lines.......................................................... 50

CONN

- time line example ....................................................51

CONN

AN5225 - Rev 3

page 63/64

AN5225

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

AN5225 - Rev 3

page 64/64

ST AN5225, STM32 Application note

Specifications and Main Features

Frequently Asked Questions

User Manual

1 General information

1.1 Acronyms and abbreviations

1.2 Reference documents

2 USB Type-C in a nutshell

2.2 Minimum mandatory feature set

3 Connector pin mapping

3.1 VBUS power options

4 CC pins

4.1 Plug orientation/cable twist detection

4.2 Power capability detection and usage

5 Power profiles

6 USB power delivery 2.0

6.1 Power delivery signaling

6.1.1 Packet structure

6.1.2 K-codes

6.2 Negotiating power

7 USB power delivery 3.0

8 Alternate modes

8.1 Alternate pin re-assignments

8.2 Billboard

9 Product offer

10 Type-C with no power delivery

10.1 STM32 USB2.0-only device conversion for USB Type-C platforms

STM32 USB2.0 host conversion for USB Type-C platforms

10.3 STM32 legacy USB2.0 OTG conversion for USB Type-C platforms

11 Type-C with power delivery using integrated UCPD peripheral

11.1 Software overview

11.2 Hardware overview

11.2.1 DBCC1 and DBCC2 lines

11.2.2 Sink port

11.2.2.1 VBUS-powered sink

11.2.2.2 Separately powered sink

11.2.3 Source port

11.2.4 Dual-role power port

11.2.5 Dual-role power port with FRS

12 Type-C with power delivery using a general-purpose peripheral

12.1 Software overview

12.2 Hardware overview

12.2.1 Sink port using TCPM/TCPC interface

12.2.2 Source port using TCPM/TCPC interface

12.2.3 Dual-role power port using TCPM/TCPC interface

13 Dedicated architecture proposals and solutions

13.1 Sourcing power to VBUS

DC/DC output control with GPIOs

Applying VCONN on CC lines

13.3.1 Time line

13.4 FRS signalling

13.5 Monitoring VBUS voltage and current

14 Recommendations

Capacitors on CC lines

14.3 TCPP01 Type-C port protection device

14.3.1 Sink applications

14.3.2 Handling dead battery condition

15 Additional information

Revision history