ST AN487 Application note

AN487

APPLICATION NOTE

INTRODUCTION TO A 10A MONOLITHIC SWITCHING

REGULATOR IN MULTIPOWER-BCD TECHNOLOGY

by C. Diazzi

The L497X series of high c urrent switching r egulator ICs exploit Multipower -BCD technology to achieve
very high output currents with low power dissipation – up to 10A in the Multiwatt power package and

3.5A in a DIP package.

Switched mode techniques led to t he develo pme nt of high efficiency c ircuits offering space s aving and a
reduction in costs, mainly of th e heatsink and output LC filter. For these applications a n ew technology,
called MULTIPOWER-BCD, has been developed which allows the integration on the same chip of isolated
power DMOS elements, Bipolar transistors and CMOS logic.

The technology is particularly suitable for the problems rising in the switch mode field, due to the charac­teristics of high efficiency, fast switching speed, no secondary breakdown of the power DMOS element.

The great flexibility that we ha ve at our disposal for the c hoice of the s igna l an d drivin g s ections com po­nents allows optimization and compactness of the system. With MULTIPOWER-BCD it has been possible
to implement the family L497X, a new series of fully integrated switching regulators suitable for DC-DC
converters working in Buck configuration. The complete family consists of five devices which differ each
other only by the output current v alue (2A, 3.5A, 5A, 7A, 10 A) they can deliver to the load. The devices
rated at 2A and 3.5A are assembled in Power Dip (16+2+2), while the others are assembled in the
Multiwatt15 package. Each device integrates a DMOS output power stage, a control section, limiting cur­rent and supervisor functions like Reset and Power Fail signal for microprocessors applications.

Output voltage can be adj usted starting from the internal reference voltage (5. 1V) up to 4 0V, allowing a
maximum output power of 80W for the 2A version a nd of 400W f or the 10A vers ion. M aximum o perat ing
supply voltage is 55V.

THE TECHNOLOGY

The technology architecture is bas ed on the vertical DMOS sil icon gate process that allows a chan nel
length of 1.5 micron ; using a junction isolation technique it has be en possible to mix on the same chip
Bipolar and CMOS transistors along with the DMOS power components (Fig. 2). Figure 1 shows how this
process brings a rapid increase in power IC complexity compared to conventional bipolar technology.

Figure 1. BCD process and increase in power ICs complexity.

November 2003

1/13

AN487 APPLICATION NO TE

Figure 2. Cross section of the BDC mixed technology.

In the 70’s class B circuits and DC circuits allowed output power in the range of 70W. By 1980 ,with the
introduction of switching techniques in power ICs, output powers up to 200W were rea ched; with BCD
technology the output power increased up to 400W.

FUNCTIONS AND BLOCK DIAGRAM

The complete block diagram of the hi gh power L4970A is shown in fig.3. Each bl ock is analysed in the
follo wing .

Figure 3. Block diagram of the 10A monolithic regulator L4970A.

POWE R SU PPLY
The device is provided with an internal stabilized p ower supply ( Vstart =12V ), that p rovides the supply

voltage to the analog and digital co ntrol blocks and also the suppl y vo ltage to th e bootstrap section. The
Vstart voltage supplies also the internal Reference Voltage section that provides accurate 5.1V voltage to
the control loop. Through trimming techniques the 5.1V reference is within +- 2% limits.

2/13

AN487 APPLICATION NOTE

OSCILLATOR and FEDF ORWARD
The oscillator block (fig.4) generates the sawtooth waveform that sets the switching frequency of the sys-

tem. The signal, compared with the output voltage of the error amplifier, generates the PWM signal to be
sent to the power output stage. The oscillator features a voltage feed-forward technique which is com­pletely integrated and doesn’t require any external component. Feed-forward function works in the supply
voltage range 15-45V. The rate of increase of the sawtooth wavw-form is directly proportional to the input
voltage Vcc. As Vcc increases, the output pulse-width (transistor on-time) decreases in such a manner as
to provide a constant "volt-second’ product to the inductance(fig.5).

Figure 4. Oscillator circuit

From fig.5 it is shown that the duty cycle c hanges due to the ramp increase when V cc increases. T he error
amplifier output doesn’t have to change to keep the loop in regulation. This feature increases significantly
the line regulation performance.

Figure 5. Voltage Feeforward waveform.

3/13

AN487 APPLICATION NO TE

A resistor, between Rosc and GND , define s a curr ent that is mirrored in terna lly to c harge the oscillator
capacitor on the Cosc pin. The voltage at pin.Rosc is a function of Vcc value for the implementation of the
feed-forward fun ction (oscillator slope proportion al to Vcc ). A compa rator is sensing the voltage a cross
Cosc capacitor and dis-carge it when the ram p exceedes an u pper threshold proportional to V cc for the
implementation of the feed-forward function. The Cosc discharge current is internally controlled at a value
of about 20 mA. The lower threshold of the comparator is about 1.3V (2VBE). Here are reported basic
equations for the oscillator:

V

9V

–

I

CHARGE

V

TH.HIGH

CC

------------------------------- -=

V

CC

------------------------------- - 2V

BE

R

OSC

I

DISCH

–

9

for 15V ≤ V

@ 20m A (2)

9V

BE

+=

BE

≤ 45V (1)

CC

for 15V ≤ V

≤ 45V (3)

CC

V

TH. LOW

F

SWITCH

Note that formula (5) does not take in account the discharge time of C
at high F

SWITCH

(200 KHz), and that is dependent on C

T

DISCH

--------------------------------------------- ------------------------------- -=

= 2VBE (4)

9

--------------------------------

≅

R

OSCCOSC

, that is not negletable working

OSC

⋅

osc

OSC

V

T H.HIGHVTH.LOW

–()C

value.

20m A

(5)

(6)

By whic h :

----------------------------------- ----------------- -

R

oscCosc

------------------------- - T

1

+

9

DISCH

(7)

During the discharge time of Cosc a clock pulse is generated t hat is av ailable on pi n.SYNC and that can
be used to synchronize max 3 dev ices of the sam e f ami ly. See also fig. 6 and fig. 7 for the switchin g fre­quency versus value of R4 (R

osc

).

PWM
The comparison between oscillator sawtooth and error amplifier output generates the PWM signal that

feeds the driving stages. A PWM latch structure is implemented to avoid multiple pulses that could be dan­gerous for the power stage. A maximum duty cycle limitation is impleme nted in the PWM s tage. Such
limitation is obtained by the synchronization pulse generated in the oscillator section during the Cosc dis­charge time. When the pulse is present the driver is inhibited. In this way even if the error amplifier output
completely overcomes the oscillator sawtooth, the power stage can not work in DC conditions, but is
switched off during the clock pulse allowing a maximum duty cycle tipically in the range 90 - 95 % .

SOFT START
Soft start (see fig.8) is an essential function for correct start-up and to obtain a monotonically increasing

output voltage, without overstressing the output power stage. Soft start operates at the start-up of the sys­tem and after the intervention of thermal protection. The function is realized through a capacitor connected
to soft start pin, which is charged at constant current(about 100uA) up to a value of about 7V.

During the charging tim e , t hrough PNP transisto r Q1 t he voltage at the output of the t rans conduc-tance
amplifier is forced to increase with the same rising speed of Css cap acitor. As the capacitor is c harged,

4/13