ST AN440 Application note
AN440
Application note
QII and QIII TRIAC triggering with positive power supply
Introduction
New TRIACs with high commutation and dv/dt performances are now available on the
market.
Generally these TRIACs can be triggered only in the first three quadrants (case of
Snubberless™, logic level and Snubberless high temperature TRIACs) as shown in
Figure 1.
This paper describes a trigger circuit supplying a negative gate current for quadrants II and
III implemented in a system using a positive power supply.
Without a new design, just by adding a capacitor and a diode, new series TRIACs can
replace conventional TRIACs.
Figure 1. The quadrants of Snubberless, logic-level, and Snubberless high
temperature TRIACs
I
I
T
T
+-
+-
nd
nd
2
2
rd
rd
3
3
--
--
+ +
+ +
st
st
1
1
th
th
4
4
NOT
NOT
TRIGGERABLE
TRIGGERABLE
I
I
G
G
TM: Snubberless is a trademark of STMicroelectronics
A
A
1
1
I
I
T
T
I
I
G
G
A
A
2
2
March 2008 Rev 3 1/8
www.st.com
Principle of proposed gate circuit AN440
1 Principle of proposed gate circuit
To drive the TRIAC in the 2nd and 3rd quadrants, a discharge capacitor is used as shown in
Figure 2.
Figure 2. Basic diagram of the triggering circuit
+ Vcc
MCU
MCU
+ Vcc
+ Vcc
I/O
I/O
R3
R3
Tr
Tr
+ Vcc
R2
R2
C
C
D
D
LOAD
LOAD
R1
R1
TRIAC
TRIAC
LINE
GND
GND
GND
GND
When the transistor Tr is switched off, capacitor C is charged through resistance R2 and
diode D. The diode is used to avoid a capacitor charging current through the TRIAC gate. A
Schottky diode could be used to keep the voltage drop level below the gate non trigger
voltage (V
). When the TRIAC is triggered, Tr transistor is switched on, C is discharged
GD
through R1 and Tr and a negative current flows through the TRIAC gate.
We have to consider different parameters to define all the components:
● The TRIAC gate triggering current (I
● The time duration of the gate current pulse.
● The TRIAC latching current (I
) especially for low rms current loads.
L
GT
).
2/8
AN440 Gate current pulse width setting
2 Gate current pulse width setting
The TRIAC latching current (IL) is the minimum value of the main current which allows the
component to remain in the conducting state after the gate current I
That is to say the gate current has to be higher than I
until the main current reaches the
GT
latching current.
Example: for most of CW Snubberless TRIACs (refer to datasheet for further information):
has been removed.
G
Q1 – Q3: I
Q2: I
max = 50 mA
L
max = 60 mA
L
Example: for most BW Snubberless TRIACs:
Q1 – Q3: I
Q2: I
max = 70 mA
L
max = 80 mA
L
Figure 3. Gate control principle
I
I
a1
a1
t
t
1
1
I
I
Lmax
Lmax
I
I
g
g
t
t
1
1
t
t
t
I
I
GM
GM
2
2
I
I
GM
GM
t
3/8
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