ST AN439 Application note

AN439

Application note

Snubberless™ and logic level TRIAC behavior at turn-off

Introduction

The use of TRIACs is limited by their switching behavior. Indeed, there is a risk of spurious triggering after conduction if the slope of the decreasing current is too high, and/or if the slope of the reapplied voltage is too high. The designer must then take some precautions: device over-rating, switching aid network (snubber), and junction temperature margin, and so on. This generally involves additional costs.

After a brief discussion of commutation when a TRIAC is turned off, this article will describe the behavior of the logic level and Snubberless TRIACs, which present high commutation capabilities.

Contents

1 TRIAC turn-off description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 (dI/dt)c versus (dV/dt)c characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Application requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3.1 TRIAC with resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3.2 TRIAC with inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 TRIAC without snubber network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Logic level and Snubberless TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Operation in Q1-Q2-Q3 quadrants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Performances and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 Logic level TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.2 Snubberless TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 Logic level TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.2 Snubberless TRIACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

March 2008 Rev 3 1/16

www.st.com

TRIAC turn-off description AN439

1 TRIAC turn-off description

1.1 Definition

The TRIAC can be compared to two thyristors mounted in back-to-back and coupled with a control area which allows the triggering of this Alternating Current Switch with only one gate (see Figure 1).

Looking at the TRIAC silicon structure (see Figure 2), it can be noted that the conduction areas, corresponding to these two thyristors, narrowly overlap each other on the control area.

Figure 1. Simplified equivalent

schematic of TRIAC circuit

Figure 2. Example of TRIAC silicon

structure

Gates

Ctrl

A1 G

Gates

Ctrl

During the conduction time, a certain quantity of charge is injected into the structure. The biggest part of this charge disappears by recombination during the current decrease, while another part is extracted after the turn-off by the reverse recovery current. Nonetheless, an excess charge remains, particularly in the neighboring regions of the gate, which can induce the triggering of the other conduction area when the mains voltage is reapplied across the TRIAC. This is the problem of commutation.

For a given structure at a determined junction temperature, the turn-off behavior depends on:

1. The quantity of charge which remains when the current drops to zero. The quantity of the charge is linked to the value of the current which was circulating in the TRIAC approximately 100 µs, about two or three times the minority carriers’ life time, before the turn-off. Thus, the parameter to consider is the slope of the decreasing current, called the turn-off dI/dt or dI/dt

. (see Figure 3)

OFF

2. The slope of the reapplied voltage during turn-off. This parameter is the commutation dV/dt, called the turn-off dV/dt or dV/dt current, proportional to the dV/dt

, flows into the structure, and therefore charges are

OFF

(see Figure 3). A capacitive

OFF

injected and added to those coming from the previous conduction.

2/16

AN439 TRIAC turn-off description

Figure 3. dI/dt and dV/dt at turn-off

Mains

OUT

dI/dt

OFF

dV/dt

OFF

1.2 (dI/dt)c versus (dV/dt)c characterization

To characterize the turn-off TRIAC behavior, we consider a circuit in which the slope of the decreasing current can be adjusted. In addition, the slope of the reapplied voltage can be controlled by using, a circuit of resistors and capacitors connected across the TRIAC. For a determined dV/dt which induces the spontaneous triggering of the TRIAC. This is the critical dI/dt the (dI/dt)c in TRIAC datasheets. This is also the way to trace the curve of the TRIAC commutation behavior (see TRIAC datasheet curve “Relative variation of critical rate of decrease of main current (dI/dt)c versus reapplied (dV/dt)c”).

In TRIAC datasheets, the commutation behavior is specified in different way according to the TRIAC technologies. For standard TRIAC, a minimum (dV/dt)c is specified for a given (dI/dt)c. For logic level TRIACs, a minimum (dI/dt)c is specified for two given (dV/dt)c (0.1 V/µs and 10 V/µs). For Snubberless TRIACs, a minimum (dI/dt)c is specified without (dV/dt)c limitation.

Figure 4 represents the curve of the commutation behavior obtained with a standard 4 A

TRIAC. This TRIAC is available with different sensitivities:

● Z0402: I

● Z0405: I

● Z0409: I

● Z0410: I

For lower sensitive gate TRIACs (Z0409 and Z0410), the (dI/dt)c is slightly modified according to the (dV/dt)c. For sensitive gate TRIACs (Z0402 and Z0405), this parameter noticeably decreases when the slope of the reapplied voltage increases.

((dV/dt)c), we progressively increase the dI/dt

OFF

= 3 mA;

= 5 mA;

= 10 mA;

= 25 mA.

COM

until a certain level

OFF

, called

3/16

TRIAC turn-off description AN439

Figure 4. Relative variation of (dI/dt)c versus (dV/dt)c for a 4 A standard TRIAC

(typical values)

Area of spurious firing at

commutation

Safe area

In practice, the current waveform, and thus the dI/dt we cannot change it.

So, in TRIAC applications, it is always necessary to know the dI/dt a TRIAC with a suitable (dI/dt)c. This is the most important parameter.

Suppose a circuit in which the dI/dt

OFF

4 A TRIACs, characterized by the curves in Figure 4, will be not suitable even if the dV/dt is equal to 0.1 V/µs.

1.3 Application requirements

1.3.1 TRIAC with resistive load

In this case, the TRIAC current and the mains voltage are in phase (see Figure 5). When the TRIAC switches off (i.e. when the current drops to zero), the mains voltage is equal to zero at this instant and will increase across the TRIAC according to the sinusoidal law:

Equation 1

)t·

sin(VV

·=

MaxMains

For the European mains, i.e. V

Equation 2

= 220 V at 50 Hz, the slope will be:

RMS

, is imposed by the load. Generally

OFF

of the load to choose

OFF

reaches 2 times the specified (dI/dt)c. The standard

OFF

≈

)Hz()V(RMS)s/V(OFF

s/V1.010f·22Vdt/dV

µπµ···

For 110 V, 60 Hz mains, the slope will be: dV/dt

These relatively low dV/dt dI/dt

only depends on the load rms current and the mains frequency. For resistive loads,

OFF

correspond to the left points on the curves in Figure 4. The

OFF

as for most other loads, we will have:

Equation 3

π=

4/16

≈ 0.06 V/µs.

OFF

≈

I5.010f22Idt/dI ·····

)Hz()A(RMS)ms/A(OFF

)A(RMS

AN439 TRIAC turn-off description

Figure 5. Current and voltage waveforms for resistive loads (phase control)

dI/dt

OFF

Mains

dV/dt

OFF

1.3.2 TRIAC with inductive load

An inductive load induces a phase lag between the TRIAC current and the mains voltage (see Figure 6).

When the current drops to zero, the TRIAC turns off and the voltage is abruptly applied across its terminals. To limit the speed of the reapplied voltage, a resistive / capacitive network mounted in parallel with the TRIAC is generally used (see Figure 13). This “snubber” is calculated to limit the dV/dt the (dI/dt)c specified in the datasheet. The dI/dt

at a value for which the dI/dt

OFF

is also determined in this case by the

OFF

is lower than

OFF

load impedance (Z) and the mains rms voltage. (see. AN437 for RC snubber circuit design)

Figure 6. Current and voltage waveforms for inductive loads (phase control)

dI/dt

OFF

Mains

dV/dt

OFF

5/16

TRIAC turn-off description AN439

1.4 TRIAC without snubber network

Without snubber circuit, the dV/dt

is limited by the capacitance between anode cathode

OFF

junction of the TRIAC. When the current drops to zero, the TRIAC is considered as a switch which turns off. The dampened oscillating circuit is constituted by the loads, L and R, and the internal capacitance, C

, of the TRIAC (see Figure 7). The final value E depends on the

peak mains voltage and the phase difference (φ) between voltage and current.

Figure 7. TRIAC commutation on an inductive load without a snubber network

Load

Mains

≈ E

Load

VT(t)

dV/dt

OFF

For a second order linear differential equation with a step function input, the voltage variation across the TRIAC (V

(t)) is given by:

Equation 4

)t(dV2dt)t(Vd1

E)t(V

=++·

With damping factor:

Equation 5

Undamped natural resonance:

)F(T)(

· L

)H(

Equation 6

=ω

)s/rad(0

CL1·

)F(T)H(

Final voltage value:

Equation 7

)sin(2VE

RMS

For example, the typical internal capacitances of 1 A, 12 A and 24 A TRIACs are respectively 12 pF, 90 pF and 180 pF (without direct voltage junction polarisation, worst case). Without snubber, and for most part of inductive loads, the damping factor (ξ) is generally lower than 1.

φ··=

6/16

AN439 TRIAC turn-off description

For an underdamped oscillating circuit (0 ≤ ξ ≤ 1), the voltage variation (VT(t)) across the TRIAC is defined by:

Equation 8

⎛ ⎜

ω ⎜ ⎝

ωξ

·-

With damped natural resonance:

⎞

··-

ωξ

⎟

e)tsin()tcos(·EE)t(V

···

⎟ ⎠

Equation 9

1 ξωω -·=

In the case of pure inductive load (R = 0, worst case), the circuit is undamped. The maximum reapplied dV/dt

across the TRIAC is:

OFF

Equation 10

dt/dV

)s/V(OFF

)V(RMS

C.L

)F(T)H(

tat10.

Without snubber, according to the characteristics of inductive loads, the maximum dV/dt

OFF

without snubber will be limited to about 60 V/µs for 100 – 220 V applications. Thus, it is not necessary to get the (dI/dt)c values for (dV/dt)c above 100 V/µs .

7/16

Logic level and Snubberless TRIACs AN439

2 Logic level and Snubberless TRIACs

2.1 Operation in Q1-Q2-Q3 quadrants

To make significant progress in the TRIAC technology is to essentially improve the turn-off behaviour. In other words, the critical (dI/dt)c has to be improved.

To reach this aim, a different structure has been developed. In this structure, the different active areas have been decoupled to separate the elementary thyristors and the gate area. This improvement provides the gate triggering in the fourth quadrant. In practice this modification does not lead to a problem because the gate drive circuits generally work in Q1/Q3 or Q2/Q3. (see Figure 8)

Figure 8. Basic gate drive circuits in Q1/Q3 or Q2/Q3 operations

Diac

Opto-triac

Q1/Q3 operation Q2/Q3 operation

µC

For a given technology, the TRIACs commutation behaviour depends on the gate sensitivity. The correlation between the critical (dI/dt)c and the triggering gate current for 12 A TRIACs is represented in Figure 9. For a same current rating and gate sensitivity, Snubberless TRIACs present a (dI/dt)c at least 2 times higher than for standard TRIACs.

Figure 9. Correlation between commutation behavior and sensitivity

(measurement performed on several lots of 12 A TRIACs)

Critical

(dI/dt)c (A/ms)

Snubberless TRIACs

Snubberless Triacs Standard TRIACs

Standard Triacs

10 20

8/16

30 40 50

IGT(mA)

3rd quadrant

AN439 Logic level and Snubberless TRIACs

Logic level TRIACs use the breakthrough of the Snubberless technology to improve the trade-off between sensitivity and commutation. Nevertheless, a snubber can still be necessary with these TRIACs.

2.2 Performances and specifications

2.2.1 Logic level TRIACs

In this category, sensitive TRIACs are defined by a maximum gate current (IGT) of 5 mA for the TW type and 10 mA for the SW one.

In the datasheets of logic level TRIACs, a minimum (dI/dt)c is specified for the following cases:

● Resistive load with a (dV/dt)c of 0.1 V/µs.

● Inductive load with a (dV/dt)c of 10 V/µs.

For example, a 6 A logic level TRIAC is specified as follows:

Table 1 . (dI/dt)c and (dV/dt)c specifications for a 6 A logic level TRIAC

BTA06 / BTB06

Symbol Test Conditions Quadrant

(1)

(dI/dt)c

1. Minimum IGT is guaranted at 5% of IGT max

2. For both polarities of A2 referenced to A1

VD = 12 V RL = 30 Ω

(dV/dt)c = 0.1 V/µs Tj = 125 °C

(2)

Without snubber T

I - II - III MAX. 5 10 mA

I - II - III MAX. 1.3 V

= 125 °C 1.2 2.4

= 125 °C - -

TW SW

2.7 3.5

MIN.

Unit

A/ms(dV/dt)c = 10 V/µs T

2.2.2 Snubberless TRIACs

This series covers the range of 6 to 25 A with gate currents of 35 mA (CW type) and 50 mA (BW type). This series has been specially designed so that the TRIACs turn-off without external snubber circuit.

For a same size and gate sensitivity, the (dI/dt)c improvement is at least equal to 2 between Snubberless and standard TRIACs (see Figure 10).

9/16

Logic level and Snubberless TRIACs AN439

Figure 10. Comparison between standard and Snubberless 12 A TRIACs

(dI/dt)c (A/ms)

18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1 0

0.1 1 10 100

BTA/BTB12-xBW

2 times

≈

BTA/BTB12 -xB

(dV/dt)c (V/µs)

Whatever the nature of the load, there is absolutely no risk of spurious turn-off triggering if the dI/dt

is lower than the specified (dI/dt)c value. The specified (dI/dt)c for a

OFF

Snubberless TRIAC is higher than the decreasing slope of its rms on-state current specified (I

T(RMS)

Equation 11

π=

)Hz()A(RMS)ms/A(OFF

I5.010f22Idt/dI ·≈····

)A(RMS

·=

)A(RMS)ms/A(OFF

·=

)A(RMS)ms/A(OFF

Hz50forI44.0dt/dI

Hz60forI53.0dt/dI

For example, the slope of the decreasing current in a TRIAC conducting 6 A, 8 A, 10 A, 12 A, 16 A or 25 A when the current drops to zero is given in the Ta bl e 2 .

Ta bl e 2 summarizes also the characteristics of the available BW and CW Snubberless

TRIACs.

Table 2. (dI/dt)c specification for available BW and CW Snubberless TRIACs and

slope of the different decreasing rms on-state currents (I

Typ e

T(RMS)

(A)

BTA / BTB 6 600

BTA / BTB 8 600 or 800

BTA / BTB 10 600 or 800

DRM

Volt ag e

/ V

(V)

RRM

)

Suffix

Max.

(mA)

Static

(dV/dt)

Min.

(V/µs)

CW 35 400 3.5

BW 50 1 000 5.3

CW 35 400 4.5

BW 50 1 000 7

CW 35 500 5.5

BW 50 1 000 9

(dI/dt)c

Min.

(A/ms)

T(RMS)

(1)

)

T(RMS)

(A/ms)

x 0.5

BTA / BTB 12 600 or 800

BTA / BTB 16 600 or 800

10/16

CW 35 500 6.5

BW 50 1 000 12

CW 35 500 8.5

BW 50 1 000 14

AN439 Logic level and Snubberless TRIACs

Table 2. (dI/dt)c specification for available BW and CW Snubberless TRIACs and

slope of the different decreasing rms on-state currents (I

CW 35 500 13

BTA / BTB 25 600 or 800

BW 50 1 000 22

1. (dI/dt)c specified without snubber

T(RMS)

)

12.5

11/16

Logic level and Snubberless TRIACs AN439

2.3 Typical applications

2.3.1 Logic level TRIACs

These TRIACs can be directly controlled by logic circuits and microcontrollers like the ST6 or ST7 series. Outputs of ST6/ST7 can sink currents up to 20 mA per I/O line, and therefore drive TW and SW.

These TRIACs are ideal interface for power components supplied by 110 V or 220 V, such as valves, heating resistances, and small motors.

The specification of the critical (dI/dt)c on both resistive and inductive loads offers:

● Knowledge of the security margin of the circuit in relation to the risk of the spurious

triggering

● Optimization of the performance of the TRIAC used, which results in a cost reduction

Figure 11. Light dimmer circuit with ST6/ST7 (SW TRIACs type is recommended)

+5V

LINE

NEUTRAL

SW TRIACs

type

100

100k

1/2W

820

+5V

5.6V zener

MODE

100k

220k

22k

diode

220n

400V

1N4148

+5V

RESET

VDD

PA0

PA1

PB2

PB3

PB4

PB5

OSCOUT

0V 0V 0V 0V

+5V

100u

6.3V

ST6/ST7

PB0

PB1

NMI

TEST

VSS

OSCIN

8MHz

10p10p

4.7M

TOUCH

3 x

SENSOR

+5V

220k

2.3.2 Snubberless TRIACs

The commutation of Snubberless TRIACs is specified without a (dV/dt)c limitation. The external snubber circuit can be suppressed for TRIAC turn-off and leads to a noticeable cost reduction. Nevertheless, a snubber circuit is sometimes used to eliminate spurious triggering due to fast line transients (see Figure 13).

Thanks to their significant improvement in the trade-off between gate sensitivity (I critical (dI/dt)c value and also static dV/dt, Snubberless TRIACs are used in circuits which need high safety margin, such as:

● Static relays in which the load is not well defined. With standard TRIACs, it is difficult to

adapt the snubber to all possible cases. Snubberless TRIACs resolve this problem (see

Figure 12).

12/16

) and

AN439 Logic level and Snubberless TRIACs

Figure 12. Solid state relay diagram, using Zero Voltage Switching with opto-TRIAC

SSR

INPUT

Mains

LOAD

Solid State Relay

● Motor drive circuits. The circuit Figure 12 shows an asynchronous motor controlled in

both direction by turning on each TRIAC alternately.

Figure 13. Motor control circuit using Snubberless TRIACs (Ls + r = network for

series protection)

Mains

Start Run

Gate

drive

circuit

VDR

VDRVDR

Note: Series impedance (r + L) is needed to protect the blocked TRIAC in case of unwanted

triggering (when the other is already on). Only one clamping device (V

) provides

overvoltage protection for both TRIACs (IEC 61000-4-5). Snubber networks (R1C1 and R2C2) eliminate spurious triggering due to fast line transients (IEC 61000-4-4).

The specified (dI/dt)c for a Snubberless TRIAC is higher than the decreasing slope of its specified rms on-state current (I

). This feature is important for several applications,

T(RMS)

including:

● Circuits in which the dI/dt

For universal motors, due to the impact of the brushes, the dI/dt

is higher than the dI/dt

OFF

calculated with the Equation 3.

OFF

is typically three

OFF

times higher (see Figure 14). Tab le 3 illustrates the component choice optimization by using Snubberless TRIACs. For example, a 8 A Snubberless TRIAC is sufficient to control a 110 V / 600 W motor instead of a 16 A standard TRIAC.

13/16

Logic level and Snubberless TRIACs AN439

Figure 14. TRIAC turn-off behavior for universal motors

dI/dt

T(RMS)

dI/dt

Average slope

of the TRIAC

current

Table 3. TRIAC choice for universal motor control

Power

Mains voltage

and frequency

Load

current

~ 3 x ? x I

~ 3 x ω xI

OFF

dI/dt

Max.

OFF

(1)

PEAK

Standard

TRIAC

Snubberless

TRIAC

220 V / 50 Hz 3 A rms 6 A 3.5 A/ms BTx10-600B BTx06-600BW

600 W

110 V / 60 Hz 6 A rms 10 A 7 A/ms

220 V / 50 Hz 6 A rms 10 A 7 A/ms

BTx16-600B

(2)

BTx16-600B

(2)

BTx08-600BW

1200 W

110 V / 60 Hz 12 A rms 16 A 15 A/ms

1. Maximum dI/dt

2. This type specified at 7 A/ms minimum can be too small. Certain applications could need 25 A standard TRIAC.

● Circuits which generate waveforms with a very high dI/dt

. This parameter depends on the type of motor and can be higher during start-up.

OFF

BTx40-600B

/ BTx41-600B

, such as inductive load

OFF

BTx24-600CW

controlled by a diode bridge (see Figure 15). The current variation at turn-off is then only limited by the parasitic inductance of the line and the diodes bridge circuit.

Figure 15. Inductive load controlled by a diode bridge

Mains

14/16

Inductive load

Inductive load (motor, valve …)

(motor, valve …)

AN439 Conclusion

3 Conclusion

Thanks to the logic level and Snubberless TRIACs, the designer can use devices with a commutation behavior which is compatible with all applications in the 50 or 60 Hz range. This includes phase control and static commutation for loads going from a few watts to several kilowatts.

These classes of TRIAC offer:

● An increase in the security margin of circuits, particularly where there is a risk of

spurious triggering

● Reduction of costs by using logic level TRIACs, without the need of an interface

between the TRIAC gate and the logic circuit, or using Snubberless TRIACs, which are specified without a resistive / capacitive network

4 Revision history

Table 4. Document revision history

Date Revision Changes

May-1992 1 Initial release.

19-Apr-2004 2 Stylesheet update. No content change.

07-Mar-2008 3

Reformatted to current standards. Complete rewrite for text and graphics. Part numbers updated for current products.

15/16

AN439

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16/16

ST AN439 Application note

Specifications and Main Features

Frequently Asked Questions

User Manual

1 TRIAC turn-off description

1.1 Definition

Figure 3. dI/dt and dV/dt at turn-off

1.2 (dI/dt)c versus (dV/dt)c characterization

1.3 Application requirements

1.3.1 TRIAC with resistive load

Figure 5. Current and voltage waveforms for resistive loads (phase control)

1.3.2 TRIAC with inductive load

Figure 6. Current and voltage waveforms for inductive loads (phase control)

1.4 TRIAC without snubber network

Figure 7. TRIAC commutation on an inductive load without a snubber network

2 Logic level and Snubberless TRIACs

2.1 Operation in Q1-Q2-Q3 quadrants

Figure 8. Basic gate drive circuits in Q1/Q3 or Q2/Q3 operations

2.2 Performances and specifications

2.2.1 Logic level TRIACs

Table 1 . (dI/dt)c and (dV/dt)c specifications for a 6 A logic level TRIAC

2.2.2 Snubberless TRIACs

Figure 10. Comparison between standard and Snubberless 12 A TRIACs

2.3 Typical applications

2.3.1 Logic level TRIACs

Figure 11. Light dimmer circuit with ST6/ST7 (SW TRIACs type is recommended)

2.3.2 Snubberless TRIACs

Figure 12. Solid state relay diagram, using Zero Voltage Switching with opto-TRIAC

Figure 14. TRIAC turn-off behavior for universal motors

Table 3. TRIAC choice for universal motor control

Figure 15. Inductive load controlled by a diode bridge

3 Conclusion

4 Revision history

Table 4. Document revision history