ST AN432 Application note
AN432
APPLICATION NOTE
USING ST62xx I/O PORTS SAFELY
by J.Stockinger
INTRODU CT I ON
All members of the ST62 Series of Microcontrollers from STMicroelectronics feature I/O ports
with configurab le bit f unctio ns. In add ition man y I/O bits m a y be se t as inp uts to the on -chi p
Analog to Digital Converter. T his p ort bit func tion is i n addition to the norm al I/O functi ons of
input (with or without i nterna l pull-up r esistor) , ou tput ( open dr ain or pu sh-pul l) or edg e/le vel
selectable interrupt input (with pull-up). This flexibility makes the ST62 series suitable for
many industrial control applications (and for many other uses).
This application no te e xplains the arch itecture of the I/O bit a ss ociate d with thes e por t fu nctions and provides some indications on the correct use of these features for functions such as
keyboard scanning and analog inputs. The correct manner to switch between these function is
also demonstrated in order to prevent potential malfunctions in operation.
Rev. 1.1
AN432/1203 1/12
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USING ST62xx I/O PORTS SAFELY
1 I/O PORT STRUCTURE
The ST62 I/O Port with Analog Input (hereafter referred to as I/O port) is comprised of 8 identical bit structures as shown in Figure 1. These include the interface to the ST62 internal databus and the three registers selecting the programmable options. I/O Ports without the analog
capability are identical with the exception of the analog input buffer and control logic.
The control re gisters a re nam ed the Data R egister ( DR) , the D ata D irection Re gister (DDR)
and the Option Register (OR). The DDR and OR are accessed directly at their addresses for
read and write cycles i.e. data is written to the register and can be read from the register. The
OR Register has a different operation and care must be taken when reading and writing to this
register.
Figure 1. ST62XX I/O port structure with A /D inp ut
Note: The control registers are located in the ST62 Dataspace, please refer to the individual device da-
tasheets for the specific addresses for the I/O ports with analog capability.
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USING ST62xx I/O PORTS SAFELY
Fi
Fi
gure 2. Data register access
gure 3. Read multiplexing
Table 1. Input and output modes of an I/O cell
DDR OR DR I/O pin input/output modes
0 0 0 input with pull-up
0 0 1 input no pull-up
0 1 0 interr up t input with pull-u p
0 1 1 analog input
1 0 DR open drain output
1 1 DR push-pull output
For most microco ntrollers which use p rogrammable flex ibility for I/O pins, it has bee n
common, to reduce the number of registers, to use the data register address for 3 purposes:
– writing to the DR
– reading the DR content
– reading the state of the I/O pin.
With this convention, the data read from the DR register may come from two different sources,
the DR output and the I/O pin. The source is selected by a multiplexer controlled by the state
of the DDR.
If the DDR bit corresponding to the I/O pin contains a “1", the port pin is set to output. Subsequent read accesses to DR will return the content of the DR.
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USING ST62xx I/O PORTS SAFELY
If the DDR bit corresponding to the I/O pi n contains a “0 ", the port pin i s set to input. Subsequent read accesses to DR will return the state of the I/O pi n. T his means that the D R bit i s effectively Read Only when the bi t is in O utput mod e. To r ead the content of any DR bi t set to
input mode a copy of the DR content previously written must be saved in Data RAM.
Writing to the DR bit is possible in both input and output modes. It is important to note this as
in input mode, DR is used to set the input pin characteristics (table 1). Due to the flexibility of
programming each I/O bit i ndividually, s ome p ins of a port may b e configur ed to input mode
and others to output mod e. Reading the DR will re turn some D R bit contents (from p ins in
output mode) and some I/O pin states (from pins in input mode) combined in the one byte. As
will be shown in a following section this can create serious system malfunctions if care is not
taken.
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