ST AN413 Application note
1 Introduction
The ST9 family offers the microprocessor designer a wide variety of architectural features
configurable to the user’s specific application requirements. Central to all these
configurations is a multiple register based microcomputer core to which may be added onchip, powerful peripheral components including A/D converters, Serial Communication
Interface units (SCIs), and 16-bit Multifunction timers with input capture/output compare
capabilities. The availability, on-chip, of these application-specific units obviates the need for
external interface design as well as offering high-speed and good reliability.
The particular peripherals incorporated on-chip may themselves be individually configured
to offer a wide variety of functional (architectural) alternatives. This configuration is typically
implemented by simple software routines included in the power-on- or system- reset
routines. The sole difficulty which the user may initially encounter stems, in fact, from the
power and versatility of this approach to system design. The large number of available
options means that the user must specify a large number of system parameters by
initializing control register contents for the specific peripheral units.
AN413
Application note
Initialization of the ST9
The objective of this Application Note is to suggest to the user a programming structure and
philosophy to aid in the initial configuration of the system. The approach is illustrated by a
number of specific examples selected from the wide range available for the ST9030,
ST9040 families, but are applicable to all ST9s.
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www.st.com
Contents AN413
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 ST9 basic system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 The vector address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Port initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Multifunction timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Multifunction timer initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 A/D converter configuration/initialization . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 SCI unit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.7 SCI unit initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.8 Timer/watchdog unit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.9 Timer/watchdog unit initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.10 Interrupt service routine organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix A ST9 core and peripheral configuration/initialization . . . . . . . . . . . 19
Appendix B Examples of ST9 peripheral configurations . . . . . . . . . . . . . . . . . . 25
Appendix C Examples of timer 0 configurations . . . . . . . . . . . . . . . . . . . . . . . . . 30
Appendix D Examples of A/D converter configurations . . . . . . . . . . . . . . . . . . . 37
Appendix E Examples of SCI configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Appendix F Examples of watchdog/timer configurations . . . . . . . . . . . . . . . . . 43
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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AN413 List of tables
List of tables
Table 1. Reserved locations of program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Port functional allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. System configuration: system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. System configuration: page registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Port configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Multi-function timer configuration/initialization registers (MFT0). . . . . . . . . . . . . . . . . . . . . 21
Table 7. Timer data/status registers (MFT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. Configuration/initialization registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. A/D channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. A/D threshold registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. SCI configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. SCI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. Watchdog/timer configuration/initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. SPI initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15. EEPROM initialization (ST9040 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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System reset AN413
2 System reset
After processor Reset the control and status registers, located on the group F pages (0-63)
are forced to preset values which define a default Reset configuration for the ST9 system.
By way of example the internal clock frequency (INTCLK) is set to the internal crystal
oscillator (or externally applied clock frequency, if supplied) divided by two without
prescaling, and the individual pins of Parallel Ports 0,1, and 6 are set to bidirectional Pull-up
mode (for systems with on-chip ROM). On releasing the external RESET signal the
processor PC is loaded with the contents of the Reset Vector stored in address locations 0
and 1. This causes a jump to a Reset routine in which the designer may reconfigure the ST9
system as appropriate to the requirements of his particular application, by loading suitable
values into the system registers.
The number of registers to be initialized may be considerable for a representative ST9
system. Additionally, the application-specific interrupt routines will, in general, involve the
manipulation of substantial system resources, e.g. read/write of data registers, and
test/reset of status, mask, and control registers. The associated programming task may
appear daunting in prospect on first acquaintance with the ST9 system.
Conceptually, the organization of the associated software is relatively simple and
straightforward as may be recognized by grouping under four headings the programming
steps involved in the initialization of ST9 peripherals and the organization of interrupt service
routines.
a) ST9 core system configuration
Certain core system resources are common to all on-chip peripherals and may be
specified in a common routine which is invoked at System Reset. Such common
resources include clock configuration, system and user stack specification, global
interrupt masking, processor priority setting, parallel port bit-by-bit specification, and
setting of external memory wait-cycles. The setting up of the interrupt vector table, and
certain global masking or enabling operations, may also be included under this
heading.
b) Individual on-chip peripheral configuration
The configuration of on-chip peripherals, e.g. Multifunction Timers, A/D Converters,
etc., involves the loading of suitable bit-patterns into group F page registers. This
enables the specification of input and output signals, determination of the peripheral’s
mode of operation, and the selection of internal or external clock and control signals.
c) Individual on-chip peripheral initialization
The initialization of a particular on-chip peripheral may involve the setting or clearing of
device-specific enable and masking bits, specification of interrupt priority levels,
clearing of status/flag values, and the loading of data and/or limit registers.
d) Organization of interrupt service routines
This will normally include context-saving and restoring of the PC and system status,
plus the working-register and page-pointer registers, together with the values of any
working registers used in the routine. The routine proper may include testing of status
flag bits, and the reading and writing of data registers associated with the particular
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AN413 System reset
device. Finally, the interrupt pending bits should be cleared, the context restored, and
individual masking and enabling bits restored to the appropriate values.
In practical programming terms there will normally be a single routine invoked on system
RESET which carries out the core system configurations listed under heading a) above. For
each individual peripheral there will typically be a single routine which carries out the
configuration and initialization operations listed under headings b) and c). There will also be
one or more interrupt routines associated with each peripheral, e.g. the A/D converter may
require in general two interrupt routines, one for End of Conversion, and one for out of range
operation (i.e. Analog Watchdog operation) on channels 6 and 7.
An example of a core-system configuration is given in Appendix B, and Appendices C,D,E,
and F give configuration/initialization examples, and Interrupt routines for the Timer, A/D
Convertor, SCI unit, and Timer/Watchdog respectively.
There is not enough space in a short note to discuss these programmes in detail on a line by
line basis. Instead the approach will be to list, for each device, the resources which need to
be taken into consideration when configuring, initializing, and servicing the particular device.
An example will then be given of the specific use of each such resource. With this
background, the interested user should be able to follow in detail those listings most relevant
to his particular application area.
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ST9 basic system configuration AN413
3 ST9 basic system configuration
Ta bl e 3 and Tab le 3 in Appendix A list the registers which should be loaded with specified
bit-patterns in order to initialize the ST9 to a basic system configuration. A demonstration
routine which carries this out for a representative ST9 system is listed in Appendix B. The
main routine, RESET_START, is invoked at system Reset. Also shown in Appendix B are
the Assembler Declarations and directives which enable the Interrupt Vector Address Table
to be set up in program memory.
3.1 The vector address table
The ST9 implements an interrupt vectoring structure that allows the on-chip peripheral to
identify the location of the first instruction of the Interrupt Service Routine (ISR). Each
interrupt module has a specific Interrupt Vector Register (IVR) mapped on the register file
pages. When the interrupt request is acknowledged, the peripheral interrupt module
provides, via the IVR, the vector to point to the address of the Interrupt Service Routine in
the Vector Table.
The Interrupt Vector table containing the list of addresses of the Interrupt Service Routine
must be located in the first 256 locations of program memory. The first 6 locations of
Program memory are reserved as follows:
Table 1. Reserved locations of program memory
Address Content
0 Address high of Power on Reset routine
1 Address low of Power on Reset routine
2 Address high of Divide by Zero Trap Subroutine
3 Address low of Divide by Zero Trap Subroutine
4 Address high of Top Level ISR
5 Address low of Top Level ISR
Note that since the above locations are fixed by the hardware no associated IVR register is
involved. For certain interrupt modules more than one interrupt routine may be required. For
example the A/D Converter has separate interrupts for the End of Conversion and Channel
6/7 analog underflow/overflow conditions.
In such cases the IVR register specifies the more significant, and the interrupt module
hardware specifies the least significant bits of the Vector Table address.
The following Assembler outline shows how the corresponding Vector table entries may be
established.
ADC_IT_VECT:= 30h
.
.org ADC_IT_VECT
.word ADC_WDG
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AN413 ST9 basic system configuration
.word ADC_EOC
.
ADC_WDG:
; Code for the Analog Watchdog Routine is included here
; Note that in the example in Appendix B
; the System Reset routine is invoked for out of
; range conditions on Channels 6 and 7
.
iret
ADC_EOC:
; End of A/D conversion interrupt routine included here
iret
3.2 Port initialization
The ST9 has up to a maximum of 64 lines dedicated to input/output. These lines, grouped
into eight 8-bit ports, can be independently programmed to provide parallel input/outputs
with or without handshake or may be used to connect in/out signals to/from the peripherals
(e.g. Core, Timers, SCI units, etc.) present on the chip. The functional allocation of the Ports
to support system tasks may be summarized as follows:
Table 2. Port functional allocations
Port Functions
0
1
2
3 Usable as I/O Port (without handshake) or for Timer functions.
4 Usable as I/O Port (with or without handshake)
5 Usable as I/O Port (with or without handshake).
6 Usable as I/O Port (without handshake)
7
Usable as I/O Port (without handshake) or as multiplexed low-address and data
lines for external memory.
Usable as I/O Port (without handshake) or as high-address lines for external
memory.
Usable as I/O Port (without handshake) or for SPI functions; Also INT1, INT2, and
INT3 inputs.
Usable as I/O Port (without handshake) or for SCI functions. Also used for INT4,
INT5, and INT6 inputs or for Control signals for slow external memory
Ports 0, 1, and 6 are automatically initialized on system Reset to correspond to the installed
on-chip memory.
Ports 2, 3, 4, 5, 6, and 7 need to be initialized (if available) to satisfy the specific application
requirements
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ST9 basic system configuration AN413
for external I/O, plus any alternative function assignments of port pins, and internal
interconnections. Tab le 5 ,Appendix A, lists the complete set of Port Configuration registers
together with their addresses.
Example:
C7 0A spp P3C_PG
F5 FC 05 ld P3C0R,#00000101b
F5 FD 0F ld P3C1R,#00001111b
F5 FE 05 ld P3C2R,#00000101b
In this example Port 3 pins 4, 5, 6, and 7 are configured as bidirectional pins, with weak pullup output and TTL inputs. Pins 0 (T0INA) and 2 (T0INB) are configured as TTL inputs, and
Pins 1 (T0OUTA) and 3 (T0OUTB) are configured as Alternate Function Push-pull outputs.
3.3 Multifunction timer configuration
The ST9 Multifunction Timer is configured by loading suitable control-bit patterns in the
group F page register TCR, TMR, ICR, OACR, and OBCR (see Ta bl e 6 in Appendix A). Note
that registers EIMR and CICR provide global control functions common to all on-chip
peripherals and are hence initialized conveniently in the basic system configuration routine.
The External Input Control Register, ICR, controls input source selection (internal/external),
input mode selection (falling/rising edge sensitive, etc.), counter mode of operation
(continuous, one-shot, etc.), and input function (Gate, Trigger, up/down control, etc.).
Example:
F5 FA 54 ld T_ICR,#01010100b
This instruction selects the external input A as a falling-edge-sensitive Trigger input, and the
B input is a normal Port I/O pin.
The Multifunction Timer Control Register, TCR, controls counter clear and prescaler reload
operations as well as providing a counter enable control bit and counter status flags.
Example:
F5 F8 48 ld T_TCR,#01001000b
This instruction halts the counter operation but provides for subsequent UP counting with
counter clear and Prescaler reload on Reg0 or Reg1 capture.
The Multifunction Timer Mode Register, TMR, selects the clock source for the counterprescaler input, enables Retrigger or Continuous mode, and controls register load/capture
operations.
Example:
98 8C ld T_TMR,#10001100b
This pattern enables output 1 and disables output 0, disables bi-value modes, and selects
Reg0 for capture and Reg1 for monitor. Retriggerable continuous mode is selected.
The Output Control Register, OACR, links the output T0OUTA to counter overflow/underflow
and Compare events, and provides for subsequent Set, Reset, or Toggle of the external
output. The on-chip event (OCE) may be linked to a COMP0 event.
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AN413 ST9 basic system configuration
Example:
F5 F5 1B ld T_OACR,#00011011b
In this example T0OUTA is preset to 1, and is subsequently set by COMP0, toggled by
COMP1, and Reset by OVF. The OCE signal is generated by a successful CMP0 compare
event.
The Output Control Register, OBCR, links the output T0OUTB to counter overflow/underflow
and Compare events, and provides for subsequent Set, Reset, or Toggle of the external
output. The on-chip event (OCE) may be linked to a counter overflow/underflow event.
Example:
F5 F6 83 ld T_OBCR,#10000011b
In this example T0OUTB is preset to 1, and is subsequently reset by COMP0, and set by
OVF and COMP1.
The OCE signal is generated by a counter overflow/underflow event.
3.4 Multifunction timer initialization
Initialization of the Multifunction Timer requires loading of the Prescaler register and the two
Comparison registers. The timer Status register should be cleared, the Vector Table entry
should be set, and the Multifunction Timer counter actions enabled. The interrupt/DMA
priority levels should be set and the mask bits should be adjusted as appropriate to the
application. Further, if DMA operations are specified, DMA address and counter registers
will require initialization.
The Prescaler Register, PRSR, holds the preset value for the 8-bit prescaler.
Example:
BC 00 ld T_PRSR,#00h
This defines a division ratio of 1 and the maximum counter clock is generated (INTCLK/3).
The Multifunction Timer Flags Register, FLAGR, contains flags which register successful
capture or comparison events together with OVF/UNF and overrun conditions.
Example:
15 FE FD and T_FLAGR,#~ocm0
This example resets the overrun bit for COMP0 operations.
The Interrupt Vector Register, IVR, should be loaded with the 5 most significant bits of the
Multifunction Timer’s interrupt vector address in program memory. The interrupt source
(compare, capture, or OVF/UNF) provides the least significant 3 bits to provide the correct
vector link.
Example:
F5 F2 10 ld T0_IVR,#T0_IT_VECT
In this example IVR is loaded with the start address (10h) of the block of 8 words in the
vector table allocated to the 5 different Multifunction Timer interrupts.
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ST9 basic system configuration AN413
The Interrupt/DMA Control Register, IDCR, is used to set the Interrupt and DMA priority
levels, and the DMA transfer source and destination. It also enables Swap mode and
contains End of Block condition flags.
Example:
F5 F3 D6 ld T0_IDCR,#11000110b
In this example the priority level is set at a value of 6, and the Swap mode is disabled. The
DMA capture channel source is REG0, and the DMA compare channel source is CMP0.
The Interrupt/DMA Mask Register, IDMR, contains a global Multifunction Timer Interrupt
enable plus individual DMA and Interrupt enable bits for overflow as well as successful
capture and comparison events.
Example:
F5 FF 04 ld T_IDMR,#00000100b
0F FF 80 or T_IDMR,#gtien
The first instruction sets the interrupt enable on CMP0, and the second instruction globally
enables all Multifunction Timer interrupts.
The DMA Counter Pointer Register, DCPR, defines the DMA area and source, and specifies
the location of the DMA length register.
Example:
F5 F0 4C ld T0_DCPR,#CPT_LG_DMA
The DMA length register is 4Ch = rr12 = RR76 and the transfer occurs to/from
Program/Data memory.
The DMA Address Pointer Register, DAPR, defines the DMA area and source, and specifies
the location of the DMA address register.
Example:
F5 F1 48 ld T0_DAPR,#CPT_AD_DMA
The DMA address register is 48h = rr8 = RR72. In conjunction with the DPCR value in the
above example it specifies Program memory for the buffer.
3.5 A/D converter configuration/initialization
Configuration of the A/D converter requires loading of 4 registers only, CLR, CRR, ICR, and
IVR (Ta bl e 9 ), and initialization of this device involves, apart from global masking, loading of
two double (threshold registers). Hence a single routine can be written to cover both the
configuration and initialization aspects of A/D Converter use.
The Control Logic Register, CLR, defines the Analog channel conversion start address,
selects internal/ external triggers, and enables continuous or single conversion and power
up/down modes. This register also contains a start/stop status/control bit.
Example:
F5 FD 04 ld AD_CLR,#00000100b
In this example, the conversion scan starts with channel 0 when enabled, powers up the A/D
convertor, halts conversion, and specifies single conversion scan mode.
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AN413 ST9 basic system configuration
Please note that before enabling any A/D conversion, it is mandatory to set the low bit of
Control Logic Register at least 60ms before the first conversion start. This is in order to
correctly bias the analog section of the converter.
The Interrupt Vector Register, IVR, defines the most significant 6 bits of the vector table byte
address. It thus points to the first of two word addresses which correspond to the analog
watchdog and End of conversion interrupt routines.
Example:
F5 FF 32 ld AD_IVR,#ADC_ITEOC_VECT
In this example, an address of 50 (decimal) is loaded into IVR. Hence a subsequent A/D
convertor EOC interrupt will cause a Vector Table access at location 50.
The Interrupt Control Register, ICR, contains the priority level specification, the two source
interrupt flags (Analog Watchdog and EOC) and their individual masking bits.
Example:
F5 FE 20 ld AD_ICR,#00100000b
05 FE 20 or AD_ICR,#00000110b
In this example, the priority level is first set at 0, End of Conversion interrupts are enabled,
and the Analog Watchdog interrupt is masked. The second instruction then sets the priority
to a level of 6.
If the Analog Watchdog is enabled (bit 6 in ICR) it will be necessary to load the threshold
registers for channels 6 and 7. In this case access will be made in the interrupt routine to
register CRR.
The Compare Result Register, CRR, contains 4 flags showing the results of comparison
operations between the current values of data registers 6 and 7, and the upper and lower
threshold registers.
3.6 SCI unit configuration
The list of registers to be initialized when configuring the SCI unit is given in Ta bl e 11 . The
functions of these registers, and some illustrative examples of their use, are as follows:
The Character Configuration Register, CHCR, is used to define the serial frame format.
Example:
AC E3 ld S_CHCR,#E3h
This example defines a serial frame as follows: 8 data bits, 1 stop bit, even parity, and
address input if the character matches the contents of the Address Register.
The Clock Configuration Register, CLCR, is used to specify the transmitter, receiver, and
Baud Rate clock sources, and the clock divisor ratio. It also enables Auto Echo and
Loopback test modes.
Example:
BC 80 ld s_clcr,#txclk
In this example, the Transmitter and Receiver clocks are provided by the Baud Rate
Generator. Each data bit period will be 16 clock periods (asynchronous mode), and the Auto
Loop and Loopback modes are disabled.
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ST9 basic system configuration AN413
The Baud Rate Generator Register, BRGR, specifies a 16-bit division ratio.
Example:
BF DC 00 4E ldw s_brgr,#DIV_9600
This example specifies a division ratio yielding 9600 Bauds with a 24 Mhz external clock.
Writing to a Baud Rate Generator Register immediately disables and resets both the SCI
Baud Rate generator, the transmitter and receiver circuitry. After writing to the remaining
Baud Rate Generator Register, the transmitter and receiver circuits are enabled. The Baud
Rate Generator will load the new value and start counting.
To initialize the SCI, user should first initialize one Baud Rate Generator Divisor Register.
This will reset all SCI circuitry. Initialize all other SCI registers for the desired operating
mode. To enable the SCI, initialize the remaining Baud Rate Generator Register.
The Address Compare Register, ACR, contains an 8-bit value which may be used as a
match against which a received address may be tested to set the Receive Address Pending
bit.
Example:
5C 0D ld s_acr,#RETURN
This will cause the Receive Address Pending bit to be set if an End of Command character
bit-pattern is received.
The Interrupt Vector Register, IVR, defines the most significant 5 bits of the vector table byte
address. It thus points to the first of four vector table word address entries.
Example:
4C 00x ld s_ivr,#SCI_IT
In this example, after the external symbol has been linked in, the Vector Table entry address
will be loaded into IVR at execution time.
The Interrupt Mask Register, IMR, contains five interrupt masking bits and two End of Block
DMA status bits. It also selects the shift register or holding register as source of the
transmitter register empty interrupt.
Example:
6C 05 ld s_imr,#00000101b
In this example the interrupt pending bits are reset, the Transmitter data interrupt is masked,
and the Receiver data, data error, and address interrupts are unmasked.
The Interrupt/DMA Priority Register, IDPR, specifies the Interrupt/DMA priority, selects one
of four Address modes, and controls the emission of Break characters and enables
address/9th bit data mode. It also provides mask bits for Receive and Transmit DMA
transfers.
Example:
9C 04 ld s_idpr,#04h
In this example a priority level of 4 is specified, and Transmitter DMA requests are masked.
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AN413 ST9 basic system configuration
3.7 SCI unit initialization
The list of registers to be initialized when initializing the SCI unit is given in Tab le 1 2 . The
functions of these registers, and some illustrative examples of their use, are as follows:
The Receiver DMA Transaction Counter Pointer Register, RDCPR, contains the register file
address of the receiver DMA transaction counter. In addition it determines whether the DMA
transfers occur in the register file or in memory.
Example:
An example of the use of this register is provided below (see RDAPR example).
The Receiver DMA Destination Address Pointer Register, RDAPR, contains the register file
address of the receiver DMA data destination. In addition, in conjunction with bit 0 of
RDCPR, it determines whether the DMA transfers occur in Program or Data memory.
Example:
00 FF LNG-DMA_SCI := 0Fh
00 A0 DEPART_DMA_SCI := 0A0h
00 02 NUM_RDAP := 2
00 03 NUM_RDCP := 3
2C 03 ld S_rdcpr,#NUM_RDCP
1C 02 ld S_rdapr,#NUM_RDAP
F5 03 0F ld R#NUM_RDCP,#(LNG_DMA_SCI)
F5 02 00 ld R#NUM_RDAP,#(DEPART_DMA_SCI)
In this program sequence the DMA transaction counter and Address Pointer register
addresses are defined to be R3 and R2 respectively. These two registers are initialized for a
block of size 15 bytes starting at register address A0, i.e. R160.
The Transmitter DMA Transaction Counter Pointer Register, TDCPR, contains the register
file address of the transmitter DMA transaction counter. In addition it determines whether
the DMA transfers occur in the register file or in memory.
Example:
An example of the use of this register is provided below (see TDAPR example).
The Transmitter DMA Destination Address Pointer Register, TDAPR, contains the register
file address of the transmitter DMA data destination. In addition, in conjunction with bit 0 of
TDCPR, it determines whether the DMA transfers occur in Program or Data memory.
Example:
00 FF LNG-DMA_SCI := 0Fh
00 A0 DEPART_DMA_SCI := 0A0h
00 06 NUM_TDAP := 6
00 07 NUM_TDCP := 7
2C 07 ld S_TDCPR,#NUM_TDCP
3C 06 ld S_TDAPR,#NUM_TDAP
Doc ID 1875 Rev 2 13/45
ST9 basic system configuration AN413
F5 07 0F ld R#NUM_TDCP,#(LNG_DMA_SCI)
F5 06 00 ld R#NUM_TDAP,#(DEPART_DMA_SCI)
In this program sequence the DMA transaction counter and Address Pointer register
addresses are defined to be R7 and R6 respectively. These two registers are initialized for a
block of size 15 bytes starting at register address A0, i.e. R160.
3.8 Timer/watchdog unit configuration
Configuration of the Timer/Watchdog requires loading of the 6 registers listed in Ta bl e 1 3,
Appendix A.
The Timer/Watchdog Control Register, WDTCR, contains a start/stop bit, and is also used
to select input, output, and counter modes, as well as input and output enable bits.
Example:
BC 80 ld wdtcr,#80h
In this example the Timer starts counting down in continuous mode, and the input and
output sections are disabled.
The Wait Control Register, WCR, as well as specifying the number of wait states for access
to off-chip program and data memory enables the Watchdog function.
Example:
CC 40 ld wcr,#wden
In this example the Watchdog action is disabled, and the number of wait states are set to
zero.
The External Interrupt Vector Register, EIVR, contains a bit, TLIS, which is used to control
the Top Level Interrupt source (Timer/Watchdog EOC or External NMI). A second bit IAOS
is used to select the Timer/Watchdog as an interrupt source on channel A0 (INT0). This
register is also used to supply the 4 most significant bits of the External Interrupt Vector.
Example:
6C 20 ld eivr,#EXT_IT_VECT
In this example the Timer/Watchdog EOC generates an interrupt on channel A0 at each End
of Count. The Top Level Interrupt is isolated from the NMI input and may be used for a
Software Trap.
The Timer/Watchdog Prescaler Register, WDTPR, contains an 8-bit value which is loaded
into the Prescaler register.
Example:
90 DA clr wdtpr
The specified Prescaler value of zero leads to a minimum timer count period of 333ns,
assuming a system clock running at 12MHz.
The Timer/Watchdog High Register, WDTHR, and Timer/Watchdog Low Register, WDTLR,
together contain a 16-bit value which is loaded into the counter at each End of Count.
Example:
BF F8 0B BB ldw WDTR,#3003
14/45 Doc ID 1875 Rev 2
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