ST AN4104 Application note

AN4104

Application note

Using the STM32F0xx DMA controller

	Introduction
	This application note describes how to use the STM32F0xx direct memory access (DMA)
	controller. The STM32F0xx DMA controller, the Cortex™-M0 core, the advanced
	microcontroller bus architecture (AMBA) bus and the memory system contribute to provide a
	high data bandwidth and to develop very-low latency response time software.
	This application note also describes how to take full advantage of these features and ensure
	correct response times for different peripherals and subsystems.
Note:	To ensure a quick start, application cases presented in this document are implemented in C
	language and are available in Project\STM32F0xx_StdPeriph_Examples within the
	STM32F0xx_StdPeriph_Lib package.

May 2012

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Contents	AN4104

Contents

1	DMA controller description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3
	1.1	DMA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	3
	1.2	DMA Data managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4

1.2.1 Round robin priority scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2.2Peripheral to Memory, Memory to Peripheral and Peripheral to Peripheral

DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.3 Memory to Memory DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.4 Choosing channel priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3 DMA Interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2	DMA firmware driver API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . . . 7
	2.1	How to use DMA Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 9
3	DMA programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . 10
	3.1	ADC DMA transfer to TIM example . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 10
	3.2	DMA Flash to RAM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 10
	3.3	DMA RAM to DAC example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 10
	3.4	SPI DMA example: communication between two SPIs using DMA . . . . . 11
	3.5	USART communication boards data exchange using DMA example	. . . 11
4	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. . 12

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AN4104	DMA controller description

1 DMA controller description

Direct memory access (DMA) is used in order to provide high-speed data transfer betweenperipherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.

The DMA allows data transfers to take place in the background, without the intervention of the Cortex-M0 processor. During this operation, the main processor can execute other tasks and it is only interrupted when a whole data block is available for processing. Large amounts of data can be transferred with no major impact on the system performance.

The DMA is mainly used to implement central data buffer storage (usually in system SRAM) for different peripheral modules. This solution is less expensive in terms of silicon and power consumption compared to a distributed solution where each peripheral needs to implement its own local data storage.

Depending on the sales type used, one or two DMA controllers are implemented.

The STM32F0xx DMA controller has 5 channels for DMA1 in total, each dedicated to manage memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests.

1.1DMA Overview

The DMA(s) offer(s):

●independently configurable channels (requests)

●Each channels are connected to dedicated hardware DMA requests, software trigger is also supported on each channel

●Priorities between requests from channels of one DMA are software programmable (4 levels: very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.)

●Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. The source and the address must have the same data size (to be aligned on the data size).

●Support for circular buffer management

●3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel

●Memory-to-memory transfer

●Peripheral-to-memory and memory-to-peripheral as well as peripheral-to-peripheral transfers

●Access to Flash, SRAM, APB and AHB peripherals as source and destination

●Programmable number of data to be transferred: up to 65536

The DMA aims to offer a relatively large data buffer to all peripherals. This buffer is usually located in system SRAM.

Each channel is assigned to a unique peripheral (data channel) at a given time. Peripherals connected to the same DMA channel (CH1 to CH5 in Table 1 for STM32F0xx devices) cannot be used simultaneously with active DMA (DMA function active in the peripheral register).

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DMA controller description							AN4104
	The different peripherals supporting DMA transfers in STM32F0xx devices are shown in
	Table 1.
	Table 1.	Peripherals served by DMA1 and channel allocation
	Peripherals		CH1	CH2	CH3	CH4	CH5
	ADC	ADC1	ADC1	ADC1
	SPI	SPI1		SPI1_RX	SPI1_TX
		SPI2				SPI2_RX	SPI2_TX
		USART1		USART1_	USART1_RX	USART1_	USART1_RX
				TX		TX
	USART
		USART2				USART2_	USART2_RX
						TX
	I2C	I2C1		I2C1_TX	I2C1_RX
		I2C2				I2C2_TX	I2C2_RX
						TIM1_CH4	TIM1_UP
		TIM1		TIM1_CH1	TIM1_CH2	TIM1_TRIG
							TIM1_CH3
						TIM1_COM
		TIM2	TIM2_CH3	TIM2_UP	TIM2_CH2	TIM2_CH4	TIM2_CH1
		TIM3		TIM3_CH3	TIM3_CH4	TIM3_CH1
					TIM3_UP	TIM3_TRIG
		TIM6/DAC			TIM6_UP
	TIM				DAC
							TIM15_CH1
		TIM15					TIM15_UP
							TIM15_TRIG
							TIM15_COM
		TIM16			TIM16_CH1	TIM16_CH1
					TIM16_UP	TIM16_UP
		TIM17	TIM17_CH1	TIM17_CH1
			TIM17_UP	TIM17_UP
Note:	For more details,refer to RM0091 DMA section for STM32F0xx devices.

1.2DMA Data managing

The DMA controller performs direct memory transfer by sharing the system bus with the Cortex-M0 core. When the CPU and DMA are targeting the same destination (memory or peripheral) the DMA request may stop the CPU access to the system bus for several bus cycles. The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU.

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