ST AN4092 Application note

AN4092

Application note

Hw recommendations for SPC564Axx / SPC563Mxx

Introduction

The SPC564Axx /SPC563Mxx devices target a range of powertrain applications:

●Low to mid range engine management

●Automotive transmission control

The devices are based on the e200zx Power Architecture® core and feature the second version of the enhanced Timing Processor Unit (eTPU2) for advanced, independent timing control operations.

This document aims to provide guidelines to design the ECU hardware in the most efficient way. It is focused on:

●Power Management Controller (PMC)

●FMPLL and oscillator

●Configuration pins and unused IOs

●ADC see Section 4: ADC

●Reset

May 2012

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Contents	AN4092

Contents

1	Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . .			. 6
	1.1	Single 5 V system power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
		1.1.1	External power supply slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
		1.1.2	3.3 V power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
		1.1.3	1.2 V power supply and regulator controller . . . . . . . . . . . . . . . . . . . . . .	7
		1.1.4	External ballast transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
		1.1.5	1.2V core regulator external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
		1.1.6	Inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
		1.1.7	Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	1.2	External power supply configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14

1.2.1 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.2 External power supply slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.2.3 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.3	Mixed configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
1.4	Low-Voltage-Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
1.5	Voltage fine tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
1.6	Stand-by RAM functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	1.6.1	SRAM Standby switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
	1.6.2	Standby Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	1.6.3	Brown-out Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17

1.7 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

	1.7.1	Internal logic power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	1.7.2	Analog power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	1.7.3	Voltage regulator power consumption . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	1.7.4	3.3V power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	1.7.5	IOs power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	1.7.6	Package power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
2	FMPLL and crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19

2.1 Crystal oscillator and external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.1.1 External circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1.2 Recommended crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.2 Crystal or external reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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2.3 Bypass mode or normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 Ramp up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3	Configuration pins and unused IOs . . . . . . . . . . . . . . . . . . . . . . . . . . .		23
	3.1	Boot modes (SPC564Axx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	3.2	Boot modes (SPC563Mxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	3.3	Clock reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	3.4	Weak pull configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	3.5	RSTCFG (SPC564Axx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	3.6	Unused I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24

4	ADC .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	25
	4.1	Alternative approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
5	Reset	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	5.1	/RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	5.2	/RSTOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	5.3	Reset source description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	5.4	Reset circuitry example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33

Appendix A Previous recommended PMC network configurations . . . . . . . . . 34

Appendix B Further information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

B.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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List of tables	AN4092

List of tables

Table 1. External network specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2. Miscellaneous decoupling caps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Fine tuning parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Crystal total load capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6. SPC564Axx / SPC563Mxx ADC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 7. Reset source description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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AN4092	List of figures

List of figures

Figure 1. Voltage regulator external components guaranteed configuration 1 . . . . . . . . . . . . . . . . . . 9 Figure 2. Voltage regulator external components guaranteed configuration 2 . . . . . . . . . . . . . . . . . 10 Figure 3. Inrush current example - without collector resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. Inrush current example - with collector resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. VDD distribution using a small plane example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Implementation of decoupling Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. System clock diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. PCB layout example for SPC563Mxx / SPC564Axx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Simplified ADC circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11. Reset circuitry example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 12. SPC563Mxx configuration/SPC564Axx configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 13. Alternate SPC563Mxx configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Power Management Controller (PMC)	AN4092

1 Power Management Controller (PMC)

The SPC564Axx / SPC563Mxx devices require three separate power supplies, nominally:

●5V (VDDREG, VDDEHx, VDDA);

●3.3V (VRC33, VDDEHx, VDDEx);

●1.2V (VDD, VDDPLL);

In addition, an optional 0.95 - 1.2 / 2 - 5.5 V Vstby for the SRAM stand-by functionality may be required(a).

Different modes of operations are possible:

●Single 5V system power supply (SPC564Axx: QFP176 only, SPC563Mxx: QFP144 only)

●Three external power supplies

●5V and 3.3V provided externally (1.2 V internally controlled)

●5V and 1.2V provided externally (3.3 V internally generated)

1.1Single 5 V system power supply

The SPC564Axx in QFP176 and the SPC563Mxx in QFP144 devices can operate from a single 5 volt system power supply. An on-chip regulator is provided for 3.3 volts, and an onchip regulator controller is provided for the 1.2 volt supply. The 1.2 volt controller requires an external NPN ballast transistor and external bypassing for proper operation. This section covers the requirements for the regulator controller and the bypass capacitors for the device.

The Voltage Regulator Supply (VDDREG) is the 5V input to the internal 3.3V regulator and the 1.2 regulator controller. This input can be tied to VSS to disable these feature. However grounding VDDREG disables also the low voltage inhibit (LVI) circuit. Refer to Section 1.2: External power supply configuration for more details.

The SPC564Axx in BGA324 and the SPC563Mxx in QFP176 devices instead cannot operate from a single 5 volt system power supply. Most of the SPC564Axx EBI interface pins (main difference between BGA324 and QFP176) can’t be powered with 5V, therefore an additional external voltage supply (3.3 V) is needed. Similarly, SPC563Mxx QFP176 Nexus pins (ALT_MDOx, ALT_MSEOx, ALT_EVTI, ALT_EVTO and ALT_MCKO) must be supplied with 3.3 V.

1.1.1External power supply slew rate

Make sure that all power supply ramps are not too fast and in line to what is specified in the device datasheet. Higher slew rates might cause false ESD trigger.

1.1.23.3 V power supply

The 3.3V regulator circuitry is completely contained within the device and it requires only the 5V input supply (VDDREG) and a bypass capacitor on the regulator output(s), VRC33. This 3.3V regulator is intended for internally operation only (oscillator, part of FLASH, some

a. Refer to Section 1.6: Stand-by RAM functionality

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AN4092	Power Management Controller (PMC)

Nexus pins) and it must not be used to supply external circuitry or other IOs. Nevertheless, VRC33 can be used as the reference on the debug connector of the JTAG/Nexus interface(b).

Please notice that the JTAG and some Nexus signals (TCK, TDI, TDO, TMS, JCOMP, MSEO[0:1], RDY, MDO[4..11], EVTO, EVTI) even if powered by a nominal 5V supply, VDDEH7, are always operating on 3.3 voltage levels, being MultiV pads configured by default (this setting cannot be changed) in low swing mode. On the other hand, when the same MultiV pads are configured as GPIO (or eTPU), they work on 5V levels (this setting cannot be changed either).

1.1.31.2 V power supply and regulator controller

Most of the internal device circuitry is powered by the 1.2 V VDD input. This includes the core and the majority of the device internal logic. An internal regulator controller is implemented to provide a more cost optimized solution. By using an external ballast transistor, the power loss from reducing the 5 V to 1.2 V can be dissipated externally.

This 1.2V voltage regulator controller provides a current signal (VRCCTL) that drives the base of the external transistor. VDD is internally connected to the a sense signal that is compared to an internal bandgap reference that sets the reference voltage. Depending on VDD the current flowing out of the VRCCTL is adjusted to keep the 1.2 voltage level.

1.1.4External ballast transistor

The following NPN transistors are guaranteed for use with the on-chip voltage regulator controller: ON Semiconductor BCP68T1 or NJD2873 as well as NXP BCP68. The collector of the external transistor is preferably connected to the same voltage supply source as the output stage of the regulator, however it can also be connected to another voltage supply (for example 3.3 V).

Any other transistor type / vendor may not work with the circuitry proposed in the

Section 1.1.5: 1.2V core regulator external circuitry in all the conditions, considering the PVT (Process, Voltage, Temperature) worst cases.

Gain

The maximum current available or the VDD supply depends on the gain of the NPN transistor used, it should be high enough to allow the operation in the worst case scenario in

terms of current consumption, given the minimum current that can be sourced by VRCCTL(c).

From the SPC564Axx point of view, the worst case is at hot, the device may require up to 450mA(d) on the VDD. On the other hand, usually the worst case gain is obtained at cold.

In addition the transistor gain should not be too high otherwise the regulator may become unstable.

b.IEEE-ISTO 5001™ - 2003 extract: “The VREF signal is used to establish the signaling levels of the debug interface of the target system. Any current drawn from this pin should be limited to that needed for voltage translation and/or signal interpolation and is not intended to supply logic functions or power. VREF is not necessarily at the target processor VDD level.”

c.Please refer to device DS.

d.Preliminary data. Check the latest DS for updated figures.

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Power dissipation

Another important point is that the external transistor must be able to dissipate the power due to the voltage drop. The worst case is calculated as follow: (VDDREGmax - VDDmax(e)) * IDDmax = (5.25 - 1.32) * 0.450 = 1.768W. Depending on the package, this power might not be dissipated. For example, if the total thermal resistance is 25C/Watt, Tj = 150C e Tamb = 125C, 1W is the maximum allowed. Sometimes a heatsink is required to reduce the overall thermal resistance and thus increase the power dissipation.

An optional collector resistor can help in sharing the power dissipation. For example a 2 Ohm resistor on the collector reduce the voltage drop between collector and emitter by 0.9 V. In this case the transistor has to dissipate only (5.25 - 1.32 - 0.9) * 0.450 = 1.3635W.

Ballast transistor saturation voltage

On the other hand, the value of the collector resistor cannot be too high because the transistor must always be operating out of the saturation region: VCE>VCEsat. For example, if the VCEsat = 0.3V, Rmax = (VDDREGmin - VDDmax - VCEsat) / IDDmax = (4.75 - 1.32 - 0.3)

/ 0.45 = 7.6 Ohm.

1.1.51.2V core regulator external circuitry

In the Figure 1 and Figure 2 are shown the guaranteed configuration of the external components(f). Collector and emitter caps should be the same type capacitors; otherwise series impedance mismatch require bigger bypass capacitor on the 5V supply. The value of the collector cap can be reduced to the ones of the emitter to allow the matching.

The ground connection is also critical and must be as close as possible to the mandatory VDD capacitor bank to be effective.

The snubber circuit on the base is required for stability reasons.

e.The worst case is normally with VDD = 1.12V, however the max current is specified when VDD = 1.32V.

f.Refer also to Appendix A: Previous recommended PMC network configurations

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Power Management Controller (PMC)

Figure 1. Voltage regulator external components guaranteed configuration 1

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Power Management Controller (PMC)	AN4092

Figure 2. Voltage regulator external components guaranteed configuration 2

6		6$$2%'
	#REG
4		0&8
#C
	+EEP PARASITIC	62##4,
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Table 1.	External network specification
External component		Min.	Typ.	Max.	Notes
T1					NJD2873 or BCP68 only
Cb		1.1uF	2.2uF	2.97uF	X7R, -50% / +35%
Ce		3 x 2.35uF	3 x 4.7uF +	3 x 6.35uF +	X7R, -50% / +35%
		+ 5uF	10uF	13.5uF
Equivalent ESR of Ce		5mOhm		50mOhm
capacitors
					X7R, -50% / +35%
					In order to have one cap on each VDD
					(EMC rules), depending on the package the
Cd		4 x 50nF	4 x 100nF	7 x 135nF	number of these capacitors may be
					increased up to 7x100nF.
					700nF is the absolute max allowed: it can
					be also split in 12x56nF or 17x47nF.
Rb		9Ohm	10Ohm	11Ohm	+/-10%

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Table 1.	External network specification (continued)
External component		Min.	Typ.	Max.	Notes
Creg			10uF		Depending on the 5V regulator impedance,
					the required capacitor can go up to 100uF
Rc		1.1Ohm		5.6Ohm	May or may not be required. It depends on
					the allowable power dissipation of T1
Re		0.18Ohm	0.2Ohm	0.22Ohm	+/-10% The required value can be obtained
					by using more resistors in parallel

Table 2.	Miscellaneous decoupling caps
Supply		Quantity	Value	Notes
VRC33		1	470nF - 2uF	Low ESR (<50mOhm)
VSTBY		1	10nF	To be grounded if the Stand-by feature is
				not used.
VDDPLL		1	100nF
		1	10nF
VDDEHx		4	100nF	Two pairs each side
		4	1nF
VDDA		1	10uF	To be connected between VDDA and VSSA
VRH		1	10nF
VRL
VSSA
				REFBYPC is not a supply. The external
REFBYPC		1	100nF	bypass capacitor must be placed between
				REFBYPC pin and GND.

1.1.6Inrush current

Since big capacitors need to be charged, a large current can be required when the power is turned on, to be more precise when the 1.2V regulator is switched on.

A soft-start circuitry is included in the 1.2V regulator but the ramp is only limited to 60-80us (PVT variation), being ineffective for limiting the inrush current.

As already pointed out in the Section 1.1.4, the resistor on the collector may or may not be required depending on the allowable power dissipation of the ballast transistor. However the resistor on the collector can be also very useful in limiting the current necessary to charge the capacitors during power on.

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	Figure 3. Inrush current example - without collector resistor

Figure 4. Inrush current example - with collector resistor

1.1.7Layout recommendations

The inductance of the heatsink rail of the ballast transistor and the MCU lead to inductance in the system. The placement of the transistor also affects the inductance, due to the lengths of the 1.2 V traces (from the emitter to the VDD pins) and of the VRCCTL signal: those inductances eventually reduce the phase margin jeopardizing the regulator stability.

It is mandatory to keep the parasitic inductance between the emitter and VDD pins lower than 20nH.

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