ST AN4088 Application note
AN4088
Application note
Migrating from STM32F1 to STM32F0
Introduction
For designers of STM32 microcontroller applications, it is important to be able to easily
replace one microcontroller type by another one in the same product family. Migrating an
application to a different microcontroller is often needed, when product requirements grow,
putting extra demands on memory size, or increasing the number of I/Os. On the other
hand, cost reduction objectives may force you to switch to smaller components and shrink
the PCB area.
This application note is written to help you and analyze the steps you need to migrate from
an existing STM32F1 device to an STM32F0 device. It gathers the most important
information and lists the vital aspects that you need to address.
To migrate your application from STM32F1 series to STM32F0 series, you have to analyze
the hardware migration, the peripheral migration and the firmware migration.
To benefit fully from the information in this application note, the user should be familiar with
the STM32 microcontroller family. You can refer to the following documents that are available
from www.st.com.
● The STM32F1 family reference manuals (RM0008 and RM0041), the STM32F1
datasheets, and the STM32F1 Flash programming manuals (PM0075, PM0063 and
PM0068).
● The STM32F0 family reference manual (RM0091) and the STM32F0 datasheets.
For an overview of the whole STM32 series and a comparison of the different features of
each STM32 product series, please refer to AN3364 Migration and compatibility guidelines
for STM32 microcontroller applications.
Ta bl e 1 lists the microcontrollers and development tools concerned by this application note.
Table 1. Applicable products
Type Product sub-class
Microcontroller
July 2012 Doc ID 023072 Rev 1 1/60
STM32 F0 Entry-level
STM32 F1 Mainstream
www.st.com
Contents AN4088
Contents
1 Hardware migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Boot mode compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Peripheral migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 STM32 product cross-compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Reset and clock controller (RCC) interface . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7 GPIO interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 EXTI source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9 FLASH interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.10 ADC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.11 PWR interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Real-time clock (RTC) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15 USART interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16 CEC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Firmware migration using the library . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1 Migration steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 RCC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 FLASH driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 CRC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.5 GPIO configuration update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5.1 Output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5.2 Input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5.3 Analog mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.5.4 Alternate function mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/60 Doc ID 023072 Rev 1
AN4088 Contents
4.6 EXTI Line0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7 NVIC interrupt configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.8 ADC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.9 DAC driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.10 PWR driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.11 Backup data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.12 CEC application code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.13 I2C driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.14 SPI driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.15 USART driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.16 IWDG driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Doc ID 023072 Rev 1 3/60
List of tables AN4088
List of tables
Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F1 series and STM32F0 series pinout differences . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. STM32 peripheral compatibility analysis F1 versus F0 series . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. IP bus mapping differences between STM32F0 and STM32F1 series. . . . . . . . . . . . . . . . 10
Table 6. RCC differences between STM32F1 and STM32F0 series . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Example of migrating system clock configuration code from F1 to F0 . . . . . . . . . . . . . . . . 15
Table 8. RCC registers used for peripheral access configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DMA request differences between STM32F1 series and STM32F0 series . . . . . . . . . . . . 17
Table 10. Interrupt vector differences between STM32F1 series and STM32F0 series. . . . . . . . . . . 19
Table 11. GPIO differences between STM32F1 series and STM32F0 series . . . . . . . . . . . . . . . . . . 21
Table 12. FLASH differences between STM32F1 series and STM32F0 series . . . . . . . . . . . . . . . . . 23
Table 13. ADC differences between STM32F1 series and STM32F0 series . . . . . . . . . . . . . . . . . . . 24
Table 14. PWR differences between STM32F1 series and STM32F0 series. . . . . . . . . . . . . . . . . . . 26
Table 15. STM32F10x and STM32F0xx source clock API correspondence . . . . . . . . . . . . . . . . . . . 32
Table 16. STM32F10x and STM32F0xx FLASH driver API correspondence. . . . . . . . . . . . . . . . . . . 33
Table 17. STM32F10xx and STM32F0xx CRC driver API correspondence . . . . . . . . . . . . . . . . . . . . 35
Table 18. STM32F10x and STM32F0xx MISC driver API correspondence . . . . . . . . . . . . . . . . . . . . 40
Table 19. STM32F10x and STM32F0xx DAC driver API correspondence . . . . . . . . . . . . . . . . . . . . . 42
Table 20. STM32F10x and STM32F0xx PWR driver API correspondence . . . . . . . . . . . . . . . . . . . . 43
Table 21. STM32F10xx and STM32F0xx CEC driver API correspondence . . . . . . . . . . . . . . . . . . . . 45
Table 22. STM32F10xx and STM32F0xx I2C driver API correspondence . . . . . . . . . . . . . . . . . . . . . 47
Table 23. STM32F10xx and STM32F0xx SPI driver API correspondence . . . . . . . . . . . . . . . . . . . . . 51
Table 24. STM32F10x and STM32F0xx USART driver API correspondence . . . . . . . . . . . . . . . . . . 54
Table 25. STM32F10xx and STM32Fxx IWDG driver API correspondence . . . . . . . . . . . . . . . . . . . . 58
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4/60 Doc ID 023072 Rev 1
AN4088 Hardware migration
1 Hardware migration
The entry-level STM32F0 and general-purpose STM32F1xxx families are pin-to-pin
compatible. All peripherals shares the same pins in the two families, but there are some
minor differences between packages. The transition from the STM32F1 series to the
STM32F0 series is simple as only a few pins are impacted (impacted pins are in bold in
Ta bl e 2 ).
Table 2. STM32F1 series and STM32F0 series pinout differences
STM32F1 series STM32F0 series
QFP48 QFP64 Pinout QFP48 QFP64 Pinout
55PD0 - OSC_IN 5 5 PH0 - OSC_IN
66PD1 - OSC_OUT 6 6 PH1 - OSC_OUT
-18VSS_4 -18PF4
-19VDD_4 -19PF5
35 47 VSS_2 35 47 PF6
36 48 VDD_2 36 48 PF7
20 28 Boot1/PB2 20 28 PB2
The migration from F1 to F0 has no impact on the pinout, except that the user wins 2 or 4
GPIOs for his/her application at VSS/VDD 2 and 4 locations, depending on the package
used.
Doc ID 023072 Rev 1 5/60
Boot mode compatibility AN4088
2 Boot mode compatibility
The way to select the boot mode on the F0 family differs from F1 devices. Instead of using
two pins for this setting, F0 gets the nBOOT1 value from an option bit located in the User
option bytes at 0x1FFFF800 memory address. Together with the BOOT0 pin, it selects the
boot mode to the main Flash memory, the SRAM or to the System memory. Tab le 3
summarizes the different configurations available for selecting the Boot mode.
Table 3. Boot modes
F0/F1 Boot mode selection
Boot mode Aliasing
BOOT1 BOOT0
x 0 Main Flash memory
0 1 System memory
1 1 Embedded SRAM
Note: The BOOT1 value is the opposite of the nBOOT1 option bit.
Main Flash memory is selected
as boot space
System memory is selected as
boot space
Embedded SRAM is selected as
boot space
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AN4088 Peripheral migration
3 Peripheral migration
As shown in Ta bl e 3 , there are three categories of peripherals. The common peripherals are
supported with the dedicated firmware library without any modification, except if the
peripheral instance is no longer present. You can change the instance and, of course, all the
related features (clock configuration, pin configuration, interrupt/DMA request).
The modified peripherals such as: ADC, RCC and RTC are different from the F1 series ones
and should be updated to take advantage of the enhancements and the new features in F0
series.
All these modified peripherals in the F0 series are enhanced to obtain smaller silicon print
with features designed to offer advanced high-end capabilities in economical end products
and to fix some limitations present in the F1 series.
3.1 STM32 product cross-compatibility
The STM32 series embeds a set of peripherals which can be classed in three categories:
● The first category is for the peripherals which are, by definition, common to all products.
Those peripherals are identical, so they have the same structure, registers and control
bits. There is no need to perform any firmware change to keep the same functionality,
at the application level, after migration. All the features and behavior remain the same.
● The second category is for the peripherals which are shared by all products but have
only minor differences (in general to support new features). The migration from one
product to another is very easy and does not need any significant new development
effort.
● The third category is for peripherals which have been considerably changed from one
product to another (new architecture, new features...). For this category of peripherals,
the migration will require new development, at the application level.
Ta bl e 4 gives a general overview of this classification.
Doc ID 023072 Rev 1 7/60
Peripheral migration AN4088
Table 4. STM32 peripheral compatibility analysis F1 versus F0 series
Peripheral F1 series
SPI Ye s
WWDG
IWDG
DBGMCU Ye s Yes No JTAG, No Trace
CRC
EXTI
F0
series
Yes++
Feature Pinout FW driver
Two FIFO available, 4-bit to
16-bit data size selection
Compatibility
Identical Partial compatibility
Ye s Yes Same features NA Full compatibility
Ye s Yes+ Added a Window mode NA Full compatibility
Identical for the
SWD
Ye s Yes++
Ye s Ye s +
Added reverse capability and
initial CRC value
Some peripherals are able to
generate event in stop mode
NA Partial compatibility
Identical Full compatibility
Kernel clock, arbitration lost
flag and automatic
CEC
Ye s Yes++
transmission retry, multi-
Identical Partial compatibility
address config, wakeup from
stop mode
DMA
Ye s Ye s
1 DMA controller with 5
channels
NA Full compatibility
Partial compatibility
TIM
PWR
Ye s Yes+ Enhancement Identical Full compatibility
Ye s Ye s +
No Vref, Vdda can be greater
than Vdd, 1.8 mode for core.
Identical for the
same feature
Partial compatibility
PD0 & PD1 =>
RCC Yes Yes+ New HSI14 dedicated to ADC
PF0 & PF1 for the
Partial compatibility
osc
Choice for independent clock
USART
Ye s Ye s +
sources, timeout feature,
Identical Full compatibility
wakeup from stop mode
Communication events
I2C
Ye s Ye s + +
managed by HW, FM+,
wakeup from stop mode,
Identical New driver
digital filter
DAC
ADC
Yes Yes+ DMA underrun interrupt Identical Full compatibility
Ye s Ye s + +
Same analogic part, but new
digital interface
Identical Partial compatibility
Subsecond precision, digital
RTC
Ye s Ye s + +
calibration circuit, time-stamp
function for event saving,
Identical for the
same feature
New driver
programmable alarm
FLASH Yes Yes+ Option byte modified NA Partial compatibility
GPIO
Yes Yes++ New peripheral 4 new GPIOs Partial compatibility
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AN4088 Peripheral migration
Table 4. STM32 peripheral compatibility analysis F1 versus F0 series (continued)
Peripheral F1 series
CAN Ye s N A N A N A N A
USB FS
Device
Ethernet Ye s N A N A N A N A
SDIO Ye s N A N A N A N A
FSMC Ye s N A N A N A N A
Touch
Sensing
COMP NA Yes NA NA NA
SYSCFG NA Yes NA NA NA
Ye s N A N A N A N A
NA Yes NA NA NA
F0
series
Feature Pinout FW driver
Compatibility
Note: Yes++ = New feature or new architecture
Yes+ = Same feature, but specification change or enhancement
Yes = Feature available
NA = Feature not available
3.2 System architecture
The STM32F0 MCU family has been designed to target an entry-level market, with lowpower capabilities and easy handling. In order to fulfill this aim while keeping the advanced
high-end features proper to the STM32, the core has been changed for a Cortex-M0. Its
small silicon area, coupled to a minimal code footprint, allows for low-cost applications with
32 bits performance. Figure 1 shows the correspondence between the M3 and M0 sets of
instructions. Moving from F1 to F0 requires a recompilation of the code to avoid the use of
unavailable features.
Doc ID 023072 Rev 1 9/60
Peripheral migration AN4088
Figure 1. System architecture
Important modifications have been performed on the MCU organization too, starting by
switching from a Harvard to Von Neumann architecture, decreasing the system complexity,
or focusing on SW Debug in order to simplify this precise feature.
3.3 Memory mapping
The peripheral address mapping has been changed in the F0 series versus F1 series. The
main change concerns the GPIOs which have been moved from the APB bus to the AHB
bus to allow them to operate at the maximum speed.
Ta bl e 5 provides the peripheral address mapping correspondence between F0 and F1
series.
Table 5. IP bus mapping differences between STM32F0 and STM32F1 series
Peripheral
TSC
CRC 0x40023000
FLITF 0x40022000 0x40022000
RCC 0x40021000 0x40021000
DMA1/DMA 0x40020000 0x40020000
STM32 F0 series STM32 F1 series
Bus Base address Bus Base address
0x40024000 NA NA
0x40023000
AHB1
AHB
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AN4088 Peripheral migration
Table 5. IP bus mapping differences between STM32F0 and STM32F1 series
STM32 F0 series STM32 F1 series
Peripheral
Bus Base address Bus Base address
GPIOF
GPIOD 0x48000C00 0x40011400
GPIOC 0x48000800 0x40011000
GPIOB 0x48000400 0x40010C00
GPIOA 0x48000000 0x40010800
DBGMCU
TIM17 0x40014800 NA NA
TIM16 0x40014400 NA NA
TIM15 0x40014000 NA NA
USART1 0x40013800
SPI1 / I2S1 0x40013000 0x40013000
TIM1 0x40012C00 0x40012C00
ADC / ADC1 0x40012400 0x40012400
EXTI
AHB2
APB2
APB2
(through
SYSCFG)
0x48001400
APB2
0x40015800 NA NA
APB2
0x40010400 0x40010400
0x40011800
0x40013800
SYSCFG + COMP APB2 0x40010000 NA NA
CEC
DAC 0x40007400 0x40007400
PWR 0x40007000 0x40007000
I2C2 0x40005800 0x40005800
I2C1 0x40005400 0x40005400
USART2 0x40004400 0x40004400
SPI2 0x40003800 0x40003800
IWWDG / IWDG Own Clock 0x40003000 0x40003000
WWDG APB1 0x40002C00 0x40002C00
RTC
APB1
APB1
(through
PWR)
Doc ID 023072 Rev 1 11/60
0x40007800
0x40002800 (inc.
BKP registers)
0x40007800
APB1
0x40002800
Peripheral migration AN4088
Table 5. IP bus mapping differences between STM32F0 and STM32F1 series
STM32 F0 series STM32 F1 series
Peripheral
Bus Base address Bus Base address
TIM14
TIM6 0x40001000
APB1
TIM3 0x40000400 0x40000400
TIM2 0x40000000 0x40000000
USB device FS SRAM NA NA
USB device FS NA NA 0x40005C00
USART3 NA NA 0x40004800
TIM7 NA NA 0x40001400
TIM4 NA NA 0x40000800
FSMC Registers NA NA
USB OTG FS NA NA 0x50000000
ETHERNET MAC NA NA 0x40028000
DMA2 NA NA 0x40020400
GPIOG NA NA APB2 0x40012000
0x40002000 NA NA
0x40001000
APB1
0x40006000
APB1
0xA0000000
AHB
SDIO NA NA AHB 0x40018000
TIM11 NA NA
TIM10 NA NA 0x40015000
TIM9 NA NA 0x40014C00
APB2
ADC2 NA NA 0x40012800
ADC3 NA NA 0x40013C00
TIM8 NA NA 0x40013400
0x40015400
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AN4088 Peripheral migration
Table 5. IP bus mapping differences between STM32F0 and STM32F1 series
STM32 F0 series STM32 F1 series
Peripheral
Bus Base address Bus Base address
CAN2 NA NA
CAN1 NA NA 0x40006400
UART5 NA NA 0x40005000
UART4 NA NA 0x40004C00
SPI3/I2S3 NA NA 0x40003C00
TIM13 NA NA 0x40001C00
TIM12 NA NA 0x40001800
TIM5 NA NA 0x40000C00
BKP registers NA NA 0x40006C00
AFIO NA NA APB2 0x40010000
APB1
Note: NA = feature not available.
3.4 Reset and clock controller (RCC) interface
0x40006800
The main differences related to the RCC (Reset and clock controller) in the STM32F0 series
versus STM32F1 series are presented in Tab l e 6.
Table 6. RCC differences between STM32F1 and STM32F0 series
RCC STM32 F1 series STM32 F0 series
HSI 14 NA
HSI 8 MHz RC factory-trimmed Similar
LSI 40 KHz RC Similar
HSE
LSE 32.768 KHz Similar
PLL
System clock
source
3 - 25 MHz depending on the product
line used
- Connectivity line: main PLL +
2 PLLs for I2S, Ethernet and OTG FS
clock
- Other product lines: main PLL
HSI, HSE or PLL Similar
High speed internal oscillator dedicated to
ADC
4 - 32 MHz
Main PLL
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Peripheral migration AN4088
Table 6. RCC differences between STM32F1 and STM32F0 series (continued)
RCC STM32 F1 series STM32 F0 series
System clock
frequency
APB1/APB
frequency
RTC clock
source
MCO clock
source
Internal
oscillator
measurement /
calibration
- Up to 72 MHz depending on the
product line used
- 8 MHz after reset using HSI
Up to 36 MHz Up to 48 MHz
LSI, LSE or HSE/128 LSI, LSE or HSE clock divided by 32
- MCO pin (PA8)
- Connectivity line: HSI, HSE, PLL/2,
SYSCLK, PLL2, PLL3 or XT1
- Other product lines: HSI, HSE,
PLL/2 or SYSCLK
LSI connected to TIM5 CH4 IC: can
measure LSI with respect to HSI/HSE
clock
Up to 48 MHz
MCO(PA8): SYSCLK, HSI, HSE, HSI14,
PLLCLK/2, LSE, LSI
- LSE & LSI clocks are indirectly measured
through MCO by the timer TIM14 with
respect to HSI/HSE clock
- HSI14/HSE are indirectly measured
through MCO by means of the TIM14
channel 1 input capture with respect to HSI
clock.
In addition to the differences described in the table above, the following additional
adaptation steps may be needed for the migration.
1. S
ystem clock configuration: when moving from F1 series to F0 series, only a few
settings need to be updated in the system clock configuration code; mainly the Flash
settings (configure the right wait states for the system frequency, prefetch
enable/disable) or/and the PLL parameters configuration:
a) In case HSE or HSI is used directly as the system clock source, only the Flash
parameters should be modified.
b) In case PLL (clocked by HSE or HSI) is used as the system clock source, the
Flash parameters and PLL configuration need to be updated.
Ta bl e 7 below provides an example of porting a system clock configuration from F1 to F0
series:
– STM32F100x value line running at maximum performance: system clock at
24 MHz (PLL, clocked by the HSE (8 MHz), used as the system clock source),
Flash with 0 wait states and Flash prefetch queue enabled.
– F0 series running at maximum performance: system clock at 48 MHz (PLL,
clocked by the HSE (8 MHz), used as the system clock source), Flash with 1 wait
state and Flash prefetch enabled.
As shown in Ta bl e 7 , only the Flash settings and PLL parameters (code in Bold Italic) need
to be rewritten to run on F0 series. However, HSE, AHB prescaler and the system clock
source configuration are left unchanged, and APB prescalers are adapted to the maximum
APB frequency in the F0 series.
14/60 Doc ID 023072 Rev 1
AN4088 Peripheral migration
Note: 1 The source code presented in Tab le 7 is intentionally simplified (timeout in wait loop
removed) and is based on the assumption that the RCC and Flash registers are at their
reset values.
2 For STM32F0xx, you can use the clock configuration tool,
STM32F0xx_Clock_Configuration.xls, to generate a customized system_stm32f0xx.c file
containing a system clock configuration routine, depending on your application
requirements.
Table 7. Example of migrating system clock configuration code from F1 to F0
STM32F100x Value Line running at 24 MHz (PLL as
clock source) with 0 wait states
/* Enable HSE ----------------------------*/
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready */
while((RCC->CR & RCC_CR_HSERDY) == 0)
{
}
/* Flash configuration -------------------*/
/* Prefetch ON, Flash 0 wait state */
FLASH->ACR |= FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_0;
/* AHB and APB prescaler configuration --*/
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
/* PLL configuration = (HSE / 2) * 6 = 24 MHz */
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source ----*/
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) !=
(uint32_t)0x08)
{
}
STM32F0xx running at 48 MHz (PLL as clock source)
with 1 wait state
/* Enable HSE ----------------------------*/
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready */
while((RCC->CR & RCC_CR_HSERDY) == 0)
{
}
/* Flash configuration -------------------*/
/* Prefetch ON, Flash 1 wait state */
FLASH->ACR |= FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
/* AHB and APB prescaler configuration --*/
/* HCLK = SYSCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
/* PCLK = HCLK */
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
/* PLL configuration = HSE * 6 = 48 MHz -*/
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 |
RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
/* Enable PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Select PLL as system clock source ----*/
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) !=
(uint32_t)RCC_CFGR_SWS_PLL)
{
}
2. Peripheral access configuration: since the address mapping of some peripherals has
been changed in F0 series versus F1 series, you need to use different registers to
[enable/disable] or [enter/exit] the peripheral [clock] or [from reset mode].
Doc ID 023072 Rev 1 15/60
Peripheral migration AN4088
Table 8. RCC registers used for peripheral access configuration
Bus Register Comments
AHB
APB1
APB2
RCC_AHBRSTR Used to [enter/exit] the AHB peripheral from reset
RCC_AHBENR Used to [enable/disable] the AHB peripheral clock
RCC_APB1RSTR Used to [enter/exit] the APB1 peripheral from reset
RCC_APB1ENR Used to [enable/disable] the APB1 peripheral clock
RCC_APB2RSTR Used to [enter/exit] the APB2 peripheral from reset
RCC_APB2ENR Used to [enable/disable] the APB2 peripheral clock
To configure the access to a given peripheral, you have first to know to which bus this
peripheral is connected; refer to Ta bl e 5 then, depending on the action needed, program
the right register as described in Ta bl e 8 above. For example, if USART1 is connected to the
APB2 bus, to enable the USART1 clock you have to configure APB2ENR register as follows:
RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
3. Peripheral clock configuration: some peripherals have a dedicated clock source
independent from the system clock, and used to generate the clock required for their
operation:
a) A
DC: in STM32F0 series, the ADC features two possible clock sources:
– The first one is based on the PCLK; a prescaler allows you to reduce the ADC
input frequency by a factor 2 or 4 before getting to the ADC.
– The other one is a completely new feature on stingray; a dedicated 14 MHz
oscillator (HSI14) is integrated on the chip and can be used for the ADC input
frequency.
b) RTC:
in STM32F0 series, the RTC features three possible clock sources:
– The first one is based on the HSE Clock; a prescaler divides its frequency by 32
before going to the RTC.
– The second one is the LSE oscillator.
– The third clock source is the LSI RC with a value of 40 KHz.
3.5 DMA interface
STM32F1 and STM32F0 series use the same fully compatible DMA controller.
The STM32F0 series uses one 5-channel DMA controller when STM32F1 uses two. Each
channel is dedicated to managing memory access requests from one or more peripherals.
The table below presents the correspondence between the DMA requests of the peripherals
in STM32F1 series and STM32F0 series.
16/60 Doc ID 023072 Rev 1
AN4088 Peripheral migration
Table 9. DMA request differences between STM32F1 series and STM32F0 series
Peripheral DMA request STM32F1 series STM32F0 series
ADC1/ADC ADC1/ADC DMA1_Channel1
DMA_Channel1
DMA_Channel2
ADC3 ADC3 DMA2_Channel5 NA
DAC
SPI1
SPI2
SPI3
USART1
USART2
USART3
UART4
UART5
I2C1
I2C2
DAC_Channel1/
DAC
DAC_Channel2
SPI1_Rx
SPI1_Tx
SPI2_Rx
SPI2_Tx
SPI3_Rx
SPI3_Tx
USART1_Rx
USART1_Tx
USART2_Rx
USART2_Tx
USART3_Rx
USART3_Tx
UART4_Rx
UART4_Tx
UART5_Rx
UART5_Tx
I2C1_Rx
I2C1_Tx
I2C2_Rx
I2C2_Tx
DMA2_Channel3 / DMA1_Channel3
DMA2_Channel4 / DMA1_Channel4
DMA1_Channel2
DMA1_Channel3
DMA1_Channel4
DMA1_Channel5
DMA2_Channel1
DMA2_Channel2
DMA1_Channel5
DMA1_Channel4
DMA1_Channel6
DMA1_Channel7
DMA1_Channel3
DMA1_Channel2
DMA2_Channel3
DMA2_Channel5
DMA2_Channel4
DMA2_Channel1
DMA1_Channel7
DMA1_Channel6
DMA1_Channel5
DMA1_Channel4
(1)
DMA_Channel3
(1)
DMA_Channel2
DMA_Channel3
DMA_Channel4
DMA_Channel5
NA
DMA_Channel3/DMA_Channel5
DMA_Channel2/DMA_Channel4
DMA_Channel6
DMA_Channel7
NA
NA
NA
DMA_Channel7
DMA_Channel6
DMA_Channel5
DMA_Channel4
SDIO SDIO DMA2_Channel4 NA
TIM1
TIM1_UP
TIM1_CH1
TIM1_CH2
TIM1_CH3
TIM1_CH4
TIM1_TRIG
TIM1_COM
DMA1_Channel5
DMA1_Channel2
DMA1_Channel3
DMA1_Channel6
DMA1_Channel4
DMA1_Channel4
DMA1_Channel4
DMA_Channel5
DMA_Channel2
DMA_Channel3
DMA_Channel6
DMA_Channel4
DMA_Channel4
DMA_Channel4
Doc ID 023072 Rev 1 17/60
Peripheral migration AN4088
Table 9. DMA request differences between STM32F1 series and STM32F0 series (continued)
Peripheral DMA request STM32F1 series STM32F0 series
TIM8
TIM2
TIM3
TIM4
TIM5
TIM8_UP
TIM8_CH1
TIM8_CH2
TIM8_CH3
TIM8_CH4
TIM8_TRIG
TIM8_COM
TIM2_UP
TIM2_CH1
TIM2_CH2
TIM2_CH3
TIM2_CH4
TIM3_UP
TIM3_CH1
TIM3_TRIG
TIM3_CH3
TIM3_CH4
TIM4_UP
TIM4_CH1
TIM4_CH2
TIM4_CH3
TIM5_UP
TIM5_CH1
TIM5_CH2
TIM5_CH3
TIM5_CH4
TIM5_TRIG
DMA2_Channel1
DMA2_Channel3
DMA2_Channel5
DMA2_Channel1
DMA2_Channel2
DMA2_Channel2
DMA2_Channel2
DMA1_Channel2
DMA1_Channel5
DMA1_Channel7
DMA1_Channel1
DMA1_Channel7
DMA1_Channel3
DMA1_Channel6
DMA1_Channel6
DMA1_Channel2
DMA1_Channel3
DMA1_Channel7
DMA1_Channel1
DMA1_Channel4
DMA1_Channel5
DMA2_Channel2
DMA2_Channel5
DMA2_Channel4
DMA2_Channel2
DMA2_Channel1
DMA2_Channel1
TIM6 TIM6_UP DMA2_Channel3 / DMA1_Channel3
NA
DMA_Channel2
DMA_Channel5
DMA_Channel3
DMA_Channel1
DMA_Channel4
DMA_Channel3
DMA_Channel4
DMA_Channel4
DMA_Channel2
DMA_Channel3
NA
NA
(1)
DMA_Channel3
TIM7 TIM7_UP DMA2_Channe4 / DMA1_Channel4
TIM15_UP
TIM15
TIM15_CH1
TIM15_TRIG
TIM15_COM
TIM16
TIM17
1. For high-density value line devices, the DAC DMA requests are mapped respectively on DMA1 Channel 3 and DMA1
Channel 4.
TIM16_UP
TIM16_CH1
TIM17_UP
TIM17_CH1
DMA1_Channel5
DMA1_Channel5
DMA1_Channel5
DMA1_Channel5
DMA1_Channel6
DMA1_Channel6
DMA1_Channel7
DMA1_Channel7
(1)
NA
DMA_Channel5
DMA_Channel5
DMA_Channel5
DMA_Channel5
DMA_Channel3/DMA_Channel4
DMA_Channel3/DMA_Channel4
DMA_Channel1/DMA_Channel2
DMA_Channel1/DMA_Channel2
18/60 Doc ID 023072 Rev 1
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