SPC560Pxx, SPC56APxx power up HW guideline
INTRODUCTION
AN4057
Application note
This application note is addressed to system hardware designers using
STMicroelectronics
ensure a reliable microcontroller power up sequence also in the condition of an offset
voltage on the high voltage regulator supply pin V
The use of the SPC560Pxx/SPC56APxx internal voltage regulator requires a specific design
ST approved ballasts with the recommended supporting network described in the latest
revision of the device data sheet (for further details see Section Appendix A: Additional
information). It is important to respect the power on sequence conditions, ensuring a
monotonic supply ramp starting at ground level and respecting the min and max slew rate
on V
DD_HV_REG
This application note covers:
■ Recommended power on sequence conditions
■ Possible deviations injecting an offset voltage on V
microcontroller power up
■ Optional proposals to eliminate the effect of offset voltage on V
®
SPC560Pxx/SPC56APxx microcontrollers It gives design references to
DD_HV_REG
.
at power up.
DD_HV_REG
and its impact on
DD_HV_REG
pin
March 2012 Doc ID 022842 Rev 1 1/13
www.st.com
Contents AN4057
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Power up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Offset voltage on V
2.1 Offset voltage on V
2.1.1 Possible application paths to induce a V
2.1.2 Battery short to pin on connector of microcontroller board . . . . . . . . . . . 6
DD_HV_REG
DD_HV_REG
and voltage regulator circuitry . . . . . . . 6
: problem description . . . . . . . . . . . . . . . . . 6
DD_HV_REG
offset voltage . . . . . 6
2.2 HW guidelines for high/low voltage supply of the internal regulator with offset
voltage on V
2.2.1 Resistors partition network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2.2 V
DD_HV_REG 7
DD_HV_REG
pin active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 SPC560Pxx/SPC56APxx devices affected . . . . . . . . . . . . . . . . . . . . . . 10
Appendix A Additional information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
A.1 Reference document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13 Doc ID 022842 Rev 1
AN4057 List of tables
List of tables
Table 1. Resistor partition network values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. SPC560Pxx/SPC56APxx device affected from V
Table 3. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DD_HV_REG
offset issue . . . . . . . . . . . . . 10
Doc ID 022842 Rev 1 3/13
List of figures AN4057
List of figures
Figure 1. Offset voltage on V
Figure 2. Battery short to pin on connector of microcontroller board . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Resistors partition network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DD_HV_REG
from SPC560Pxx/SPC56APxx input pin . . . . . . . . . . . . . . . 6
4/13 Doc ID 022842 Rev 1
AN4057 Overview
1 Overview
These SPC560Pxx /SPC56APxx microcontrollers are members of a new microcontroller
family built on the Power Architecture
voltage supply, which can be either 5 V or 3.3 V depending on application requirements.
Internally the chip operates with 2 supply voltages, namely the main supply (5 V or 3.3 V)
and the core logic supply (1.2 V).
This document provides guideline for the recommended configuration of the high and low
voltage supply for the internal regulator in order to ensure the correct power up sequence of
the microcontroller.
The note describes application fault conditions that may offset V
mitigating circuitries to ensure reliable power up in case of these fault conditions. The
standard supply circuitry and sequence that use in the recommended conditions of initial
power up on V
DD_HV_REG
pin starting from ground level are described in the
SPC560Pxx/SPC56APxx data sheet (for further details see Section Appendix A: Additional
information).
Possible causes of fault conditions injecting an offset voltage on V
described in the following list:
● Supply microcontrollers I/O V
supply for V
● Offset voltage injected on V
DD_HV_REG
and V
1.1 Power up sequencing
®
. The device is supplied externally with a single
DD_HV_REG
DD_HV_REG
while the microcontroller is switched off with shorted
IN
DD_HV_IO
DD_HV_REG
pins
by external signal(s) shorted to battery.
significantly and
pin are
Preventing an overstress event or a malfunction within and outside the device, the
SPC560Pxx/SPC56APxx implements a specific power up sequence, as described in the
data sheet, to ensure each module is started only when all conditions for switching it ON are
available.
In case of a fault condition on the application board, that sequence may not be respected,
causing the device not to exit the power up.
Two possible fault conditions are described in the following sections. However, if the fault
cause is removed, the device (while within the absolute maximum ratings) works again,
without getting damaged, powering up properly.
Doc ID 022842 Rev 1 5/13
Offset voltage on V
DD_HV_REG
and voltage regulator circuitry AN4057
2 Offset voltage on V
DD_HV_REG
circuitry
2.1 Offset voltage on V
V
DD_HV_REG
offset on the devices SPC560Pxx/SPC56APxx, before the module is powered
DD_HV_REG
up, may in some cases prevent the power up device correctly.
A V
DD_HV_REG
offset before a correct power up supply sequence can set the POR device
logic to an undefined state, preventing the internal logic to switch correctly and initialize the
internal V
circuitry. The internal regulator remains in power down. The consequence is
DD_LV
that the microcontroller is not able to exit reset.
2.1.1 Possible application paths to induce a V
Figure 1 describes a GPIO configuration with the pin connected to an externally supplied
signal (V
If V
batt
induces a voltage on V
In the case V
propagated to the internal regulator. The same consideration is done when using an
external diode, D1 in Figure 1, connecting GPIO V
).
batt
is powered while MCU VDD is not yet provided, GPIO protection circuitry (diode)
.
DD_HV_IO
DD_HV_IO
is directly connected to V
: problem description
DD_HV_REG
and voltage regulator
DD_HV_REG
to VDD.
IN
offset voltage
, the induced voltage is
Figure 1. Offset voltage on V
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DD_HV_REG
from SPC560Pxx/SPC56APxx input pin
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2.1.2 Battery short to pin on connector of microcontroller board
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Another possible cause of an initial offset on V
DD_HV_REG
board connector.
6/13 Doc ID 022842 Rev 1
is battery short to any pin of the
AN4057 Offset voltage on V
DD_HV_REG
and voltage regulator circuitry
The short to battery can be propagated through various components (ASSP, ASICs, Com
Drivers) to the V
DD_HV_REG
as these components typically share the same supply.
Figure 2. Battery short to pin on connector of microcontroller board
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2.2 HW guidelines for high/low voltage supply of the internal
regulator with offset voltage on V
In general an offset voltage must be avoided to pre-charge V
paths. The MCU supply must power on from GND to power supply with a monotonic ramp
rate, minimum and maximum value as described in the data sheet (T
condition, injecting an offset to V
modifications on the module can prevent the device to remain in reset. The supply voltage
conditions are still respected.
DD_HV_REG
DD_HV_REG
DD_HV_REG
while the MCU is not supplied, the following
through parasitic
). In case of a fault
vdd
Possible HW solutions on the supplying circuitry of the microcontroller to allow a correct
power up sequence, in case of an offset build up on V
● Resistive network between V
● Active discharge on V
● Other application means to prevent the presence of an offset on V
DD
or V
DD_HV_REG
DD_HV_REG
power up
2.2.1 Resistors partition network
This solution with two partitioning resistors, shown in Figure 3, enables V
pre- conditioned and the internal V
the ballast regulator turns-on.
DD_LV_REG
Doc ID 022842 Rev 1 7/13
pin are:
and GND
, V
DD_LV_REG
DD_HV_REG
at power up
DD_HV_REG
DD_LV_REG
during
to be
to be forced into a defined state as soon as
Offset voltage on V
\
Table 1. Resistor partition network values
DD_HV_REG
and voltage regulator circuitry AN4057
Symbol Parameter Value Unit
V
DD_HV_REG
V
DD_HV_REG
R1
@ 5 V
R2
R1
@ 3.3 V
R2
Resistor between V
DD_HV_REG
/ballast
emitter and ballast collector
Resistor between ballast emitter and
ground
Resistor between V
DD_HV_REG
/ballast
emitter and ballast collector
Resistor between ballast emitter and
ground
910 Ω
300 Ω
510 Ω
300 Ω
Static consumption has to be considered into the board voltage regulator design.
Figure 3. Resistors partition network
9,*1
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63&3[[
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2.2.2 V
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GHF
63&33LFWXV
DD_HV_REG
pin active path to ground
Another solution is to add a controlled active path to ground on V
5
("1(3*
DD_HV_REG/VDD_HV_IO
forces these pins to ground when the microcontroller is switched off or discharges the
V
DD_HV_REG
at start up.
Figure 4 describes a generic configuration that uses the enable signal of an external
regulator, VIGN, to drive the gate of NFET to force V
DD_HV_REG/VDD_HV_IO
pin to ground.
When the external regulator is off there is a discharge path of the current from the
V
DD_HV_REG/VDD_HV_IO
It has to be granted that the V
condition can build up an offset on V
.
rises with the required monotonic slew rate before any fault
DD
DD_HV_REG
, prior to the release of the active discharge
circuit.
that
8/13 Doc ID 022842 Rev 1
AN4057 Offset voltage on V
Figure 4. Active path to ground
9,*1
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9''B+9B5(*
%&75/
63&3[[
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9''B/9B&25
DD_HV_REG
&
GHF
%-7
and voltage regulator circuitry
9''B+9B5(*9''B+9B,2
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Doc ID 022842 Rev 1 9/13
SPC560Pxx/SPC56APxx devices affected AN4057
3 SPC560Pxx/SPC56APxx devices affected
Ta bl e 2 lists the STMicroelectronics SPC560Pxx/SPC56APxx devices and revisions that are
affected by the previously described phenomenon.
Table 2. SPC560Pxx/SPC56APxx device affected from V
Package device
Part number
marking mask identifier
and silicon version
DD_HV_REG
MIDR1 register
offset issue
SPC560P34xx/P40xx AB - cut 1.1 (and older)
SPC560P50xx/P44xx BD - cut 3.4 (and older)
SPC560P60xx/P54xx
SPC56AP60xx/AP54xx
AA - cut 1.0
MAJOR_MASK[3:0]: 4'b0000
MINOR_MASK[3:0]: 4'b0001
MAJOR_MASK[3:0]: 4’b0001
MINOR_MASK[3:0]: 4’b0101
MAJOR_MASK[3:0]: 4’b0000
MINOR_MASK[3:0]: 4’b0000
10/13 Doc ID 022842 Rev 1
AN4057 Additional information
Appendix A Additional information
A.1 Reference document
● 32-bit Power Architecture
for automotive chassis and safety applications (SPC560P54x, SPC560P60L3,
SPC56AP54L3, SPC56AP60x, Doc ID 18340)
● 32-bit Power Architecture
automotive chassis and safety applications (SPC560P34L1, SPC560P34L3,
SPC560P40L1, SPC560P40L3, Doc ID 16100)
● 32-bit Power Architecture
for automotive chassis and safety applications (SPC560P44L3, SPC560P44L5,
SPC560P50L3, SPC560P50L5, Doc ID 14723)
®
based MCU with 1088 KB Flash memory and 80 KB RAM
®
based MCU with 320 KB Flash memory and 20 KB RAM for
®
based MCU with 576 KB Flash memory and 40 KB SRAM
Doc ID 022842 Rev 1 11/13
Revision history AN4057
Revision history
Table 3. Document revision history
Date Revision Changes
01-Mar-2012 1 Initial release.
12/13 Doc ID 022842 Rev 1
AN4057
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Doc ID 022842 Rev 1 13/13
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