ST AN4057 Application note

SPC560Pxx, SPC56APxx power up HW guideline

INTRODUCTION

AN4057

Application note

This application note is addressed to system hardware designers using STMicroelectronics ensure a reliable microcontroller power up sequence also in the condition of an offset voltage on the high voltage regulator supply pin V

The use of the SPC560Pxx/SPC56APxx internal voltage regulator requires a specific design ST approved ballasts with the recommended supporting network described in the latest revision of the device data sheet (for further details see Section Appendix A: Additional

information). It is important to respect the power on sequence conditions, ensuring a

monotonic supply ramp starting at ground level and respecting the min and max slew rate on V

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This application note covers:

■ Recommended power on sequence conditions

■ Possible deviations injecting an offset voltage on V

microcontroller power up

■ Optional proposals to eliminate the effect of offset voltage on V

SPC560Pxx/SPC56APxx microcontrollers It gives design references to

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at power up.

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and its impact on

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March 2012 Doc ID 022842 Rev 1 1/13

www.st.com

Contents AN4057

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1 Power up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Offset voltage on V

2.1 Offset voltage on V

2.1.1 Possible application paths to induce a V

2.1.2 Battery short to pin on connector of microcontroller board . . . . . . . . . . . 6

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and voltage regulator circuitry . . . . . . . 6

: problem description . . . . . . . . . . . . . . . . . 6

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offset voltage . . . . . 6

2.2 HW guidelines for high/low voltage supply of the internal regulator with offset voltage on V

2.2.1 Resistors partition network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.2 V

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pin active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 SPC560Pxx/SPC56APxx devices affected . . . . . . . . . . . . . . . . . . . . . . 10

Appendix A Additional information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

A.1 Reference document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2/13 Doc ID 022842 Rev 1

AN4057 List of tables

List of tables

Table 1. Resistor partition network values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. SPC560Pxx/SPC56APxx device affected from V

Table 3. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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offset issue . . . . . . . . . . . . . 10

Doc ID 022842 Rev 1 3/13

List of figures AN4057

List of figures

Figure 1. Offset voltage on V

Figure 2. Battery short to pin on connector of microcontroller board . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Resistors partition network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Active path to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

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from SPC560Pxx/SPC56APxx input pin . . . . . . . . . . . . . . . 6

4/13 Doc ID 022842 Rev 1

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