ST AN3961 APPLICATION NOTE

AN3961

Application note

STEVAL-IME003V1 demonstration board based on the STHV748 high voltage pulser

Introduction

The STEVAL-IME003V1 demonstration board is designed around the STHV748 4-channel high voltage pulser, a state-of-the-art device designed for ultrasound imaging applications.

The output waveforms can be displayed directly on an oscilloscope by connecting the scope probe to the relative BNCs. 16 preset waveforms are available to test the HV pulser under varying conditions.

Figure 1. Photo of the STEVAL-IME003V1

Warning: Beware before applying any voltage supply to the STEVALIME003V1 please read carefully the instructions contained in this document.

January 2012

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www.st.com

Contents	AN3961

Contents

1	Board features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
2	Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
	2.1	Programming waveform description, flagged by LED (D6-D9) . . . . . . . . . .	5
3	Hardware layout and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .		17
	3.1	Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	3.2	MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.3	SPI Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	3.4	FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20

3.4.1 Stored patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5 STHV748 stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.6 Operating supply conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4	Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31
	4.1	Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
	4.2	MCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	32
	4.3	SPI Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	33
	4.4	FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
5	Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		36
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		45

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AN3961	List of figures

List of figures

Figure 1. Photo of the STEVAL-IME003V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Scheme of program “0”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Scheme of program “1”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Scheme of program “2”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Scheme of program “3”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Scheme of program “4”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Scheme of program “5”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Hardware block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. STEVAL-IME003V1 board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10. Acquisition by program “0” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11. Acquisition by program “1” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12. Acquisition by program “2” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13. Acquisition by program “3” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 14. Acquisition by program “4” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 15. Acquisition by program “5” CHA/C/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16. Acquisition by program “5” CHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17. STHV748 single channel block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 18. Power supply connector J4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 19. Power supply connector J1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 20. Power supply connector J2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 21. Power supply connector J3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 22. USB mini-B connector (CN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 23. SWD (J40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 24. Memory expansion connector (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 25. STHV748 I/O connector (J6) not mounted on the board . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 26. STEVAL-IME003V1 hierarchical blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 27. STEVAL-IME003V1 FPGA bank 0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 28. STEVAL-IME003V1 FPGA bank 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 29. STEVAL-IME003V1 FPGA bank 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 30. STEVAL-IME003V1 FPGA bank 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 31. STEVAL-IME003V1 FPGA bank 3 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 32. STEVAL-IME003V1 FPGA power and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 33. STEVAL-IME003V1 STHV748 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 34. STEVAL-IME003V1 STM32 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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Board features	AN3961

1Board features

●Based on the STHV748 device for ultrasound imagine applications

●4 monolithic channels, 5 level high voltage pulser

●Integrated T/R switch

●On-board equivalent piezoelectric load implemented by means of:

–R/C equivalent network

–SMD landing areas available for a customized output load

●USB interface available to upload customized output waveforms

●4 Mb serial Flash memory available for storing customized waveforms

●Memory expansion connector is available to expand serial Flash size

●High voltage and low voltage connectors to power the STHV748

●25 LEDs to check the board status and proper operation

●Human machine interface to select, start and stop the stored output waveforms

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AN3961	Getting started

2 Getting started

To use the STEVAL-IME003V1, perform the following steps:

1.Connect the power supply to the board (see Section 3.1)

2.Connect the BNC to the oscilloscope.

3.Check that switch SW1 is set to the FPGA position.

4.Check that the LED indicator DONE (D23) turns on.

5.Check that FPGA is in the idle state (LED D4 is on)

6.Select the waveform with the PROGRAM button. The corresponding program LED (D6D29) turns on.

7.Press the START button to run the selected program; the START LED (D2) turns on. After program ends, the FPGA returns to the idle state (LED D4 is on).

8.If a continuous wave program has been selected (Program “2”), the button STOP must be pressed to stop program execution. The FPGA returns to the idle state and the STOP LED (D3) turns on.

9.To run the same program again, restart from step 7. To run a different program, restart from step 6.

2.1Programming waveform description, flagged by LED (D6-D9)

Program “0” (see Figure 2)

–XDCR_A: pulse wave mode, TX0 switching, 5 pulses, time-period TP=400 ns and PRF=150 µs

–XDCR_B: pulse wave mode, TX0 switching, 5 pulses in counter phase respect to XDCR_A, time-period TP=400 ns and PRF=150 µs

–XDCR_C: pulse wave mode, TX1 switching, 5 pulses, time-period TP=200 ns and PRF=150 µs

–XDCR_D: pulse wave mode, TX1 switching, 5 pulses in counter phase respect to XDCR_C, time-period TP=200 ns and PRF=150 µs

Note:

TX0 means H-bridge supplied by HVP/M0, while TX1 means H-bridge supplied by HVP/M1.

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Getting started	AN3961

Figure 2. Scheme of program “0”

7S QV

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35) V

;'&5B$

+90

7S QV

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;'&5B %

35) V

+90

7S QV

+93

35) V

;'&5B &

+90

+93

7S QV

;'&5B '

35) V

+90

!-V

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AN3961	Getting started

Program “1” (see Figure 3)

–XDCR_A: pulse wave mode, TX0&TX1 (half-bridges in parallel) switching, 5 pulses, time-period TP=200 ns and PRF=150 µs.

–XDCR_B: pulse wave mode, TX0&TX1 (half-bridges in parallel) switching, 5

pulses in counter phase respect to XDCR_A, time-period TP=200 ns and PRF=150 µs.

–XDCR_C: pulse wave mode, TX0&TX1 (half-bridges in parallel) switching, 5 pulses, time-period TP=100 ns and PRF=150 µs.

–XDCR_D: pulse wave mode, TX0&TX1 (half-bridges in parallel) switching, 5

pulses in counter phase respect to XDCR_C, time-period TP=100 ns and PRF=150 µs.

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Getting started	AN3961

Figure 3. Scheme of program “1”

	7S QV
+93	+93
	35) V
;'&5B$
+90 +90
	7S QV
+93	+93
;'&5B%
	35) V
+90 +90
+93	7S QV
	+93
	35) V
;'&5B&
+90 +90
+93	+93
	7S QV
;'&5B'
	35) V
+90 +90
	!-V

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AN3961	Getting started

Program “2” (see Figure 4)

–XDCR_A: continuous wave mode, TX-CW switching, time-period TP=400 ns.

–XDCR_B: continuous wave mode, TX-CW switching in counter-phase respect to XDCR_A, time-period TP=400 ns.

–XDCR_C: continuous wave mode, TX-CW switching, time-period TP=200 ns.

–XDCR_D: continuous wave mode, TX-CW switching in counter-phase respect to XDCR_C, time-period TP=200 ns.

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Getting started

Figure 4. Scheme of program “2”

7S QV +93

;'&5B$

+90

7S QV

+93

;'&5B%

+90

7S QV

+93

;'&5B&

+90

7S QV

+93

;'&5B'

+90

AN3961

!-V

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AN3961	Getting started

Program “3” (see Figure 5)

–XDCR_A: pulse wave mode, TX0 switching, 1.5 pulses, time-period TP=400 ns and PRF=100 µs.

–XDCR_B: pulse Wave mode, TX0 switching, 1.5 pulses, time-period TP=200 ns and PRF=100 µs.

–XDCR_C: pulse wave mode, TX0 switching 1pulses and consequently TX1 switching 1pulses, time-period TP=400 ns and PRF=100 µs.

–XDCR_D: pulse wave mode, TX0 switching 1pulses and consequently TX1 switching 1pulses both in counter phase respect to XDCR_C, time-period TP=400 ns and PRF=100 µs.

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Getting started	AN3961

Figure 5. Scheme of program “3”

7S QV

+93

35) V

;'&5B$

+90

7S QV

+93

35) V

;'&5B%

+90
+93	7S QV
	+93

35) V

;'&5B&

+90	+90
+93	+93
	7S QV

;'&5B'

35) V

+90

+90

!-V

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AN3961	Getting started

Program “4” (see Figure 6)

–XDCR_A: 5 level mode example, STATE sequence; clamp-->HVP0-->HVM0-- >HVP0-->clamp (1 µs)-->HVP1-->HVM1-->HVP1-->HVM1-->HVP1-->HVM1--

>HVP1-->HVM1-->clamp, Tp=200 ns and PRF=150 µs.

–XDCR_B: 5 level mode example, STATE sequence; clamp-->HVM0-->HVP0-- >HVM0-->clamp (1 µs)-->HVP1-->HVM1-->HVP1-->HVM1-->HVP1-->HVM1--

>HVP1-->HVM1-->clamp, Tp=200 ns and PRF=150 µs.

–XDCR_C: 5 level mode example, STATE sequence; clamp-->HVP0-->HVM0-- >HVP0-->clamp (1 µs)-->HVP1-->HVM1-->HVP1-->HVM1-->HVP1-->HVM1--

>HVP1-->HVM1-->clamp, Tp=100 ns and PRF=150 µs.

–XDCR_D: 5 level mode example, STATE sequence; clamp-->HVM0-->HVP0-- >HVM0-->clamp (1 µs)-->HVP1-->HVM1-->HVP1-->HVM1-->HVP1-->HVM1-- >HVP1-->HVM1-->clamp, Tp=100 ns and PRF=150 µs.

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Getting started	AN3961

Figure 6. Scheme of program “4”

+93

35) V

+93

V

;'&5B$

7S QV

+90

7S QV

+90

+93

35) V

+93

V

;'&5B%

7S QV

+90

7S QV

+90

+93

35) V

+93

V

;'&5B&

7S QV

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7S QV

+90

+93

35) V

+93

V

;'&5B'

7S QV

+90

7S QV

+90

!-V

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