The SPV1040 is a high efficiency, low power and low voltage DC-DC converter that provides
a single output voltage up to 5.2 V. Startup is guaranteed at 0.3 V and the device operates
down to 0.45 V when coming out from MPPT mode. It is a 100 kHz fixed frequency PWM
step-up (or boost) converter able to maximize the energy generated by few solar cells
(polycrystalline or amorphous). The duty cycle is controlled by an embedded unit running an
MPPT algorithm with the goal of maximizing the power generated from the panel by
continuously tracking its output voltage and current.
The SPV1040 guarantees the safety of overall application and of converter itself by stopping
the PWM switching in the case of an overcurrent or overtemperature condition.
The IC integrates a 120 mΩ N-channel MOSFET power switch and a 140 mΩ P-channel
MOSFET synchronous rectifier.
Figure 1 shows the typical architecture of a boost converter based solar battery charger:
Figure 1.Boost application schematic
!-V
The SPV1040 adapts the characteristics of load to those of panel. In fact, a PV panel is
made up of a series of PV cells. Each PV cell provides voltage and current which depend on
the PV cell size, on its technology, and on the light irradiation power. The main electrical
parameters of a PV panel (typically provided at light irradiation of 1000 W/m
are:
●V
●V
●I
●I
(open circuit voltage)
OC
(voltage at maximum power point)
MP
(short-circuit current)
SC
(current at maximum power point)
MP
Figure 2 shows the typical characteristics of a PV cell:
2
, T
=25 °C)
amb
Figure 2.PV cell curve
,
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MPP (maximum power point) is the working point of the PV cell at which the product of the
extracted voltage and current provides the maximum power.
4/25Doc ID 18265 Rev 7
HU>:@
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03
9
2&
!-V
AN3319Boost switching application
2 Boost switching application
A step-up (or boost) converter is a switching DC-DC converter able to generate an output
voltage higher than (or at least equal to) the input voltage.
Referring to Figure 1, the switching element (S
) is typically driven by a fixed frequency
w
square waveform generated by a PWM controller.
When S
is closed (ton) the inductor stores energy and its current increases with a slope
w
depending on the voltage across the inductor and its inductance value. During this time the
output voltage is sustained by C
and the diode does not allow any charge transfer from
OUT
the output to input stage.
When S
is open (t
w
), the current in the inductor is forced, flowing toward the output until
off
voltage at the input is higher than the output voltage. During this phase the current in the
inductor decreases while the output voltage increases.
Figure 3 shows the behavior of inductor current.
Figure 3.Inductor current in continuous mode
,
/;
,
,
/[PLQ
/[SN
6
).
,
(
RQ
(
RQ
6
6
/54
).
,
(
RII
(
RII
W
RQ
W
RII
The energy stored in the inductor during t
t
, therefore the relation between ton and t
off
D
is ideally equal to the energy released during
on
can be written as follows:
off
t
on
--------------------------=
tont
+()
off
WLPH
!-V
where “D” is the duty cycle of the square waveform driving the switching element.
Boost applications can work in two different modes depending on the minimum inductor
current within the switching period, that is if it is not null or null respectively:
●Continuous mode (CM)
●Discontinuous mode (DCM)
Doc ID 18265 Rev 75/25
Boost switching applicationAN3319
¥
Figure 4.Inductor current in discontinuous mode
)
,X
)
,XPK
6
).
,
%
ON
%
OFF
6
/54
6
).
,
T
ON
T
OFF
T
IDLE
Obviously the efficiency is normally higher in CM.
Inductance and switching frequency (F
) impact the working mode. In fact, in order to have
sw
the system working in CM, the rule below should be followed:
L
V
OUT
--------------
P
IN
2
D1D–()⋅()
---------------------------------- -
⋅>
2FSW⋅
2
According to the above, L is minimum for D = 50 %.
TIME
!-V
6/25Doc ID 18265 Rev 7
AN3319SPV1040 description
MPP
SET
,
,
5
9
9
3 SPV1040 description
The following is a quick overview of SPV1040 functions, features, and operating modes.
Figure 5.Typical application schematic using the SPV1040
L
Lx
V
PV
R
C
IN
XSHUT
3
GND
-
C
INsns
The SPV1040 acts as an impedance adapter between the input source and output load
which is:
Figure 6.SPV1040 equivalent circuit
*/
&
*/
*/
39
3DQHO
V
OUT
I
CTRL_PLUS
I
CTRL_MINUS
V
CTRL
C
OUTsns
639
JP9
'&
=
*/
R
S
R
F1
R
C
F2
F
065
&
065
R
R
065
1
D
OUT
2
V
C
OUT
AM06700v1
065
BATT
!-V
Through the MPPT algorithm, it sets up the DC working point properly by guaranteeing
Z
= Zm (assuming Zm is the impedance of the supply source). In this way, the power
IN
extracted from the supply source (P
= VIN * IIN) is maximum (PM = VM * IM).
IN
The voltage-current curve shows all the available working points of the PV panel at a given
solar irradiation. The voltage-power curve is derived from the voltage-current curve by
plotting the product V*I for each voltage generated.
Doc ID 18265 Rev 77/25
SPV1040 descriptionAN3319
W
R
START SIGNAL
ZERO CROSSING
g
-
g
Figure 7.MPPT working principle
3
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Figure 7 shows the logical sequence followed by the device which proceeds for successive
approximations in the search for the MPP. This method is called “Perturb and Observe”. The
diagram shows that a comparison is made between the digital value of the power Pn
generated by the solar cells and sampled at instant n, and the value acquired at the previous
sampling period Pn-1. This allows the MPPT algorithm to determine the sign of duty cycle
and to increment or decrement it by a predefined amount. In particular, the direction of
adjustment (increment or decrement of duty cycle) remains unchanged until condition
Pn≥Pn-1 occurs, that is, for as long as it registers an increase of the instantaneous power
extracted from the cells string. On the contrary, when it registers a decrease of the power
Pn<Pn-1, the sign of duty cycle adjustment is inverted.
In the meantime, SPV1040 sets its own duty cycle according to the MPPT algorithm, other
controls are simultaneously executed in order to guarantee complete application safety.
These controls are mainly implemented by integrated voltage comparators whose
thresholds are properly set.
Figure 8.SPV1040 internal block diagram
Lx
DETECTOR
PWM
CONTROL
DRIVERS
IoutReg
Vin Reg
VoutReg
V
MPP-REF
CLOCK
DAC CODE
Vbg
OVER CURRENT
OVER TEMPERATURE
REVERSE POLARITY
DIGITAL
CORE
XSHUT
MPP-SET
GND
ANALOG BLOCK
Burst Ref
CLOCK
MPP BLOCK
BURST MODE
8/25Doc ID 18265 Rev 7
V
OUT
-
+
I
CTRL_PLUS
+
-
I
CTRL_MINUS
V
MPP-REF
+
MPP-SET
-
V
+
Vb
CTRL
AM06703v1
AN3319SPV1040 description
The duty cycle set by the MPPT algorithm can be overwritten if one of the following is
triggered:
●Overcurrent protection (OVC), peak current on low side switch ≥ 1.8 A
●Overtemperature protection (OVT), internal temperature ≥ 155 °C
●Output voltage regulation, V
●Output current regulation R
●MPP-SET voltage V
MPP-SET
pin triggers 1.25 V
CTRL
s
* (I
CTRL_PLUS
- I
CTRL_MINUS
≤ 300 mV at the start-up and V
) ≥ 50 mV
MPP-SET
≤ 450 mV in
working mode.
Application components must be carefully selected to avoid any undesired trigger of the
above thresholds.
In order to improve the overall system efficiency, and to reduce the BOM, the SPV1040 also
integrates a zero crossing block whose role is to turn-off the synchronous rectifier to prevent
reverse current flowing from output to input.
Doc ID 18265 Rev 79/25
Application exampleAN3319
4 Application example
Figure 9 and 10 show the demonstration board of a solar battery charger based on
SPV1040 and on a status of charge indication circuit.
Figure 9.STEVAL-ISV006V2 top view
Figure 10. STEVAL-ISV006V2 bottom view
STEVAL-ISV006V2 has been designed to recharge any type of battery (except lithium
compound) which maximum voltage (V
panels (constrained by V
OC<VBATT_max
BATT_max
).
) ≤ 5.2 V and supplied by up to 5 W PV
By default STEVAL-ISV006V2 is set as follows:
●Loaded by a 220 mF super capacitor
●Supplyed by a 200 mW PV panel (V
●Maximum output current 1 A
= 1.65 V, ISC = 150 mA)
OC
The output trimmer VR
allow regulating V
2
CTRL
Maximum output current can be regulated by replacing R
according to application requirements.
Please refer to Section 6: external component selection for details about the whole
application set-up.
10/25Doc ID 18265 Rev 7
across battery.
current sensing resistor
s
AN3319Application example
Further, STEVAL-ISV006V2 provides a simple charge status circuit with 2 LEDs:
●Red LED on and green LED off, if the battery voltage is lower than charge threshold
●Red LED off and green LED on, if the battery voltage is higher than charge threshold
Charge threshold can be regulated by trimmer VR
by opening jumper J1.
. Charge status circuit can be bypassed
10
Doc ID 18265 Rev 711/25
Schematic and bill of materialAN3319
X
MPP-SET
(
)
LOAD
5 Schematic and bill of material
Figure 11. STEVAL-ISV006V2 schematic
PV+
PV-
optional
L1
Lx
SHUT
XSHUT
R
5
R
3
C
IN1
VR
DNM
GND
C
4
4
V
OUT
I
CTRL_PLUS
I
CTRL_MINUS
V
CTRL
C
R
F1
R
C
F2
F
2
R
S1
R
1
C
D
OUT
C
OUT2
VR
2
R
11
Ta bl e 1 shows the list of external components used in the demonstration board.
SPV1040 requires a set of external components and their proper selection guarantees both
the best chip functionality and system efficiency.
Input voltage capacitor
CIN is the input capacitor connected to the input rail in order to reduce the voltage ripple.
According to the maximum current (I
) provided by the PV panel connected at the input,
SC
the following formula should be considered to select the proper capacitance value for a
specified maximum input voltage ripple (V
C
IN
I
-------------------------
≥
FSWVIN⋅
SC
_rp_max
IN_rp_max
):
Maximum voltage of this capacitor is strictly dependent on the input source (typically
between 1 V and 3 V).
Low-ESR capacitors are a good choice to increase the whole system efficiency. In order to
reduce the ESR effect, it is suggested to split the input capacitance into two capacitors
placed in parallel.
Input voltage partitioning
V
MPP-SET
The V
With regard to the V
●When SPV1040 is off, V
●When SPV1040 is in operating mode, it enters BURST MODE if V
is the pin used to monitor the voltage generated by the solar cells.
MPP-SET
pin can be directly connected to PV+ rail through a 1 kΩ R3 resistor.
MPP-SET
pin, two constraints must be taken into account:
MPP-SET
voltage must be ≥0.3 to turn-on the device
triggering the 450 mV threshold.
MPP-SET
decreases
Input voltage sensing capacitor
C4 is placed as close as possible to the V
However, V
MPP-SET
must be able to follow the VIN waveform to allow SPV1040 to monitor
MPP-SET
input voltage variations.
It means that the time constant R
which is the MPPT tracking time (T
select C
C4T
Assuming R3= 1 kΩ then:
14/25Doc ID 18265 Rev 7
capacitance:
4
1
------ -
MPP
R
3
10
3–1
---------
⋅=⋅≤
10
3
C410μ F≤
must be chosen according to system properties,
3*C4
≅1 ms). The rule below must be followed in order to
MPP
pin to reject noise on V
MPP-SET
voltage.
AN3319External component selection
Inductor selection
Inductor selection is a crucial point for this application. The following application constraints
must be taken into account:
●Maximum input current (i.e. I
●Maximum input voltage (i.e. V
●Overcurrent threshold of SPV1040 (1.8 A)
●Maximum duty cycle of SPV1040 (90 %).
The input current from the PV panel flows into the inductor, so:
I
LxrmsIMPISC
<≅
According to Figure 3, during the charge phase (switch on), peak current on the inductor
depends on the applied voltage (V
Considering the maximum duty cycle (90 %):
9106–V
⋅
I
LXpeakILXrms
-------------------------------+=
2L
MP
x
Taking into account the overcurrent threshold:
and ISC of PV panel)
MP
and Voc of PV panel)
MP
) on the inductance (Lx), and on the duty cycle (ton).
IN
I
LXpeak
1.8A<
Finally, inductance should be chosen according to the following formula:
6–
910
1
-- -
X
-------------------------------
2
L
⋅
–
2I
LXrms
V
1
MP
-- -
⋅=⋅>
2
6–
910
-------------------------------
⋅
–
2I
V
MP
MP
A safer choice is to replace VMP with VOC.
Usually, inductances ranging between 10 µH to 100 µH satisfy most application
requirements.
Other critical parameters for the inductor choice are Irms, saturation current, and size.
Irms is the self rising temperature of the inductor, affecting the nominal inductance value. In
particular, the inductance decreases with Irms and the temperature increases. As a
consequence the inductor current peak can reach or surpass 1.8 A.
Inductor size also affects the maximum current deliverable to the load. In any case, the
saturation current of the choke should be higher than the peak current limit of the input
source. Hence, the suggested saturation current must be > 1.8 A.
At the same size, small inductance values guarantee both faster response to load transients
and higher efficiency.
Inductors with low series resistance are suggested in order to guarantee high efficiency.
Output voltage capacitor
A minimum output capacitance must be added at the output in order to reduce the voltage
ripple.
Critical parameters for capacitors are: capacitance, maximum voltage, and ESR.
Doc ID 18265 Rev 715/25
External component selectionAN3319
According to the maximum current (ISC) provided by the PV panel connected at the input,
the following formula can be used to select the proper capacitance value (C
specified maximum output voltage ripple (V
I
SC
OUT
------------------- -
≥
FSWV⋅
OUT_rp_max
C
OUT_rp_max
):
OUT
) for a
Maximum voltage of this capacitor is strictly dependent on the output voltage range.
SPV1040 can support up to 5.2 V, so the suggested maximum voltage for these capacitors
is 10 V.
Low-ESR capacitors are a good choice to increase the whole system efficiency.
Output voltage partitioning
R1 and R2 are the two resistors used for partitioning the output voltage.
The said V
OUT_max
the maximum output voltage of the battery, R1 and R2 must be selected
according to the following rule:
R
V
--------------=
1.25
OUT
_max
-1
------ -
R
1
2
Also, in order to optimize the efficiency of the whole system, when selecting R
power dissipation must be taken into account.
Assuming a negligible current flowing into the V
series R
P
VCTRL
As an empirical rule, R
P
VCTRLsns
1+R2
_sns
is:
V
()
OUTmax
------------------------------- -=
R1R2+
0.01V
2
_
and R2 should be selected to get:
1
OUTmaxIOUTmax
__
⋅()⋅«
_
Note:In order to guarantee proper functionality of the V
R
should be in the range between 2 µA and 20 µA.
1+R2
Output voltage sensing capacitor
C2 is placed in parallel to R2 and as close as possible to the V
Its role is to reject the noise on the voltage sensed by the V
Capacitance value depends on the time constant resulting from R
from the system switching frequency (100 kHz), as follows:
and R2, their
1
pin, maximum power dissipation on the
CTRL
pin, the current flowing into the series
CTRL
pin.
CTRL
pin.
CTRL
(τ
2
= C2*R1//R2) and
OUT
τ
out
10
2
1
∗≅
F
ssw
1
*10C ≅
F
1
*
R//R
21ssw
16/25Doc ID 18265 Rev 7
AN3319External component selection
Output current sensing filter
Rs is placed in the output rail between the I
Its role is to sense the output current (I
sensed by the I
CTRL_MINUS
and I
OUT
CTRL_PLUS
CTRL_MINUS
) flowing toward the load. Voltage drop on Rs is
pins and compared with the 50 mV internal
and I
CTRL_PLUS
pins.
threshold.
50m V
--------------------- -
≅
R
S
I
OUTmax
_
The triangular waveform of the current and noise may cause unexpected triggering of the
50 mV threshold. This can be avoided with a filter such as the one shown below:
Figure 12. STEVAL-ISV006V2 I
V
OUT
I
CTRL_PLUS
I
CTRL_MINUS
OUT
C
F
filter
R
R
F1
F2
R
S
V
BAT+
AM06707v1
Suggested values are:
R
F1=RF2
C
F
= 1 kΩ
= 1 µF
Output protection diode
If the load is not a battery, D
is to protect the devices in case a PV cell providing I
load is connected.
In fact, SPV1040 is supplied by the V
when the PV cell is connected and a voltage spike can occur damaging the converter and
the battery.
In order to guarantee the best system performance and reliability, D
as follows:
V
> V
BR
OUT_max
VCL ≤ 5.5 V
D
must be able to dissipate the following maximum power:
OUT
P
= ISC*V
max
CL
is required and placed in parallel to the output load. Its role
OUT
pin, so in the above condition the device is still off
OUT
> 0.5 A is connected when very low
MP
should be selected
OUT
XSHUT resistor
The XSHUT pin controls SPV1040 turn-on (0.3 V ≤ XSHUT ≤ 5.2 V) or turn-off (XSHUT <
0.3 V).
Doc ID 18265 Rev 717/25
External component selectionAN3319
R5 is a 0 Ω pull-up resistor shorting the XSHUT and MPP-SET pins.
Removing R5 enables the external control of the XSHUT pin to turn the SPV1040 on/off.
6.1 Optional Schottky
An external Schottky diode between Lx and V
with V
BATT_max
In fact, voltage on L
> 4.8 V.
pin can go above the maximum absolute voltage threshold (5.5 V) due
x
pins is mandatory in all the applications
OUT
to the voltage drop on the high side integrated switch when this is off (discontinuous mode)
and current needs to flow from input to output.
This Schottky diode should be chosen according to the following criteria:
VF5.5V≤
V
-
BATT_max
and
IFI≥
Lmax
For setting up the application and simulating the related test results please go to
www.st.com/edesignstudio.
18/25Doc ID 18265 Rev 7
AN3319Layout
7 Layout
Figure 13. STEVAL-ISV006V2 PCB top view
Figure 14. STEVAL-ISV006V2 PCB bottom view
Layout guidelines
PCB layout is very important in order to minimize voltage and current ripple, high frequency
resonance problems, and electromagnetic interference. It is essential to keep the paths
where the high switching current circulates as small as possible in order to reduce radiation
and resonance problems.
Large traces for high current paths and an extended ground plane reduce noise and
increase efficiency.
The output and input capacitors should be placed as close as possible to the device.
The external resistor dividers, if used, should be as close as possible to the V
V
pins of the device, and as far as possible from the high current circulating paths, in
CTRL
order to avoid picking up noise.
Doc ID 18265 Rev 719/25
MPP-SET
and
SPV1040 parallel and series connectionAN3319
PV2
SPV1040
Appendix A SPV1040 parallel and series connection
Output pins of many SPV1040s can be connected either in parallel or in series. In both
cases the output power (Pout) depends on light irradiation of each panel, on application
efficiency, and on the specific constraints of the selected topology.
The objective of this section is to explain how the output power is impacted by the selected
topology.
An example with 3 PV panels (panel1, panel2, panel3) is presented, but the conclusion can
be extended to a larger number of PV panels.
If the panel is lighted and the SPV1040 is on (it means that light irradiation intensity is such
that V
MPP-SET
P
OUTx
If the panel is completely shaded: P
SPV1040 parallel connection
This topology guarantees the desired output voltage even when only one panel is irradiated.
The obvious constraint of this topology is that V
output voltage.
=
≥ 0.3 V):
ηP
INx
]3..1x[ =
=0
OUTx
is limited to the SPV1040 maximum
OUT
Figure 15 shows the parallel connection topology:
Figure 15. SPV1040 output parallel connection
PV3
PV2
PV1
The output partitioning (R
) of each SPV1040 must be coherent with the desired V
1/R2
PV3+
SPV1040
PV3-
PV2+
SPV1040
-
According to the topology:
V
OUT=VOUT1=VOUT2=VOUT3
I
OUT=IOUT1+IOUT2+IOUT3
Vo3+
Vo3-
Vo2+
Vo2-
Vo1+PV1+
Vo1-PV1-
V
OUT+
V
OUT-
AM06711v1
OUTX
.
20/25Doc ID 18265 Rev 7
AN3319SPV1040 parallel and series connection
PV2
SPV1040
According to the light irradiation on each panel and to the system efficiency (η), the output
power results:
I*VP=
OUT xOUTxOUTx
I*VP=
INxINxINx
PPPP++=
3OU T2OU T1OUTOUT
]3..1x[ =
]3..1x[ =
Therefore:
Each SPV1040 contributes to the output power providing I
Finally, the desired V
is guaranteed if at least one of the 3 PV panels provides enough
OUT
PPP)III(VPη+η+η=++=
3IN2IN1IN3OU T2OUT1OUTOUTOUT
.
OUTX
power to turn-on the SPV1040 relating to it.
SPV1040 series connection
This topology provides an output voltage that is the sum of the output voltages of the
SPV1040 connected in series. The objective of this section is to explain how the output
power is impacted by the selected topology.
Figure 16 shows the series connection topology:
Figure 16. SPV1040 output series connection
V
OUT+
PV3
PV2
PV1
PV3+
PV2+
In this case, the topology imposes:
IIII===
3OUT2OUT1OUTOUT
VVVV++=
3OU T2OUT1OUTOUT
In case irradiation is the same for each panel:
P=
1
3
PPP==
3OUT2OUT1OUT
P*3P=
OUTxOUT
P
OUTOUTx
]3..1x[ =
I*VI*VP==
OUT1OUTOUTxOUTxOUTx
SPV1040
PV3-
SPV1040
-
Vo3+
Vo3-
Vo2+
Vo2-
Vo1+PV1+
Vo1-PV1-
V
OUT-
AM06710v1
Doc ID 18265 Rev 721/25
SPV1040 parallel and series connectionAN3319
Therefore:
V=
1
V
OUTOUTx
3
For example, assuming P
= 4 V.
V
OUTx
= 3 W and V
OUT
= 12 V, then
OUT
Lower irradiation for one panel, for example on panel 2, causes lower output power, so lower
V
OUT2
V=
OUTx
due to the I
P
OUTx
I
OUT
imposed by the topology:
OUT
The output voltage required by the load can be provided by the 1st and the 3rd SPV1040 but
only up to the limit imposed by each of their R
Some examples can help in understanding the various scenarios assuming that each R
limits V
OUTx
to 4.8 V.
partitionings.
1/R2
1/R2
Example 1:
Panel 2 has 75 % irradiation of panels 1 and 3:
V==
P
3
V*
4
3OUT1OUT
3
4
3
V*
4
W1PP
==
==
1OU T2OUT
3OU T1OUT2OUT
W75.0P
W75.2PPPP
=++=
3OUT2OUT1OUTOUT
I
OUT
P
V
OUT
OUT
12
75.2
A23.0
===
V
VV
75.0
2OUT
23.0
Two SPV1040s (1
1
3OUT1OUT
23.0
V26.3
==
st
and 3rd) supply the voltage drop caused by the lower irradiation on
V35.4
===
panel 2.
Warning:SPV1040 is a boost controller, so V
V
, otherwise the SPV1040 turns off and the input power is
INx
transferred to the output stage through the integrated Pchannel MOS without entering the switching mode.
22/25Doc ID 18265 Rev 7
must be higher than
OUTx
AN3319SPV1040 parallel and series connection
Example 2:
Panel 2 has 50 % irradiation of panels 1 and 3:
P
OUT2
1
-- -
P
2
OUT1
1
-- -
P
⋅=⋅=
OUT3
2
P
OUT1POUT3
1
P
P
I
V
V
OUT2
OUT
OUT
OUT1
OUT2
-- -
2
P
P
OUT
--------------
V
OUT
V
0.5
-----------
0.21
P
OUT1POUT2POUT3
OUT3
OUT1
2.5
------- -
12
2.38V==
1W==
0.5W==
0.21A===
1
-----------
0.21
2.5W=++=
4.76V===
In this case the system is close to its maximum voltage limit, in fact, a lower irradiation on
panel 2 impacts V
threshold (4.8 V) imposed by R
OUT1
and/or V
which are very close to the maximum output voltage
OUT3
partitioning.
1/R2
Example 3:
Panel 2 completely shaded.
In this case the maximum V
can be 9.6 V (V
OUT
OUT1+VOUT3
).
The current flow is guaranteed by the body diodes of the power MOSFETs integrated in the
SPV1040 (or by the bypass diodes, if any, placed between V
OUT-
and V
OUT+
).
Doc ID 18265 Rev 723/25
Revision historyAN3319
Revision history
Table 2.Document revision history
DateRevisionChanges
02-Feb-20111Initial release
– Demonstration board changed: from STEVAL-ISV006V1 to
STEVAL-ISV006V2
18-Apr-20112
04-May-20113Modified: Ta b le 1
08-Sep-20114
12-Sep-20115Minor text changes
21-Sep-20116
18-Nov-20117Modified: value of the component RS1 in Ta bl e 1
– Figure 9, 10, 11, 13 and 14 modified
– Section 4 modified
– Tab l e 1 modified
– Modified: Section 3 and 4
– Changed: Tab le 1: B OM
– Changed: Figure 5, 8, 9 and 11
– Modified: Input voltage partitioning, Input voltage sensing
capacitor
– Modified: Figure 5, 8 and 11
– Modified: text and equation for Input voltage sensing capacitor in
Section 6: External component selection
24/25Doc ID 18265 Rev 7
AN3319
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