ST AN3275 APPLICATION NOTE

AN3275

Application note

Improving the performance of smartcard interfaces using the ST8024L

Introduction

The ST8024L is a smartcard interface offered as a drop-in replacement for the ST8024 device. Enhancements and changes to the ST8024L device include:

●Improved performance by reducing the noise sensitivity in the charge pump

●Incorporated 1.8 V VCC output

●Lower VTH threshold voltage

This application note provides information and suggestions for the optimal use and performance of the ST8024L smartcard interface, including PCB layout, external component placement, and connections (see ST8024L application hardware guidelines on page 18). The implementation of all the blocks and procedures for card activation and deactivation (see Figure 1) of the smartcard are also explained.

The ST8024L is a smartcard interface designed to minimize microprocessor hardware and software complexity in all applications that require a smartcard (e.g., set-top box, electronic payment, pay TV, and identification cards). The electrical characteristics of the ST8024L are in accordance with New Digital Systems (NDS) and compliant with ISO7816-3, GSM11.11, and EMV 4.0. Two devices (ST8024LCDR and ST8024LCTR) in the ST8024L family have been certified by NDS.

Figure 1.	ST8024L internal block diagram
		VDD			VDDP
			100nF		100nF		100nF
							C1–	C1+
			21		6		7	5
			SUPPLY		STEP-UP CONVERTER				4	PGND
	VDD		INTERNAL
				Vref
			REFERENCE		INTERNAL OSCILLATOR
	R1(1)		VOLTAGE SENSE			2.5 MHz			8	VUP
	PORADJ/1.8V 18
	R2(1)			ALARM	EN1 CLKUP					100nF
					POWER_ON
		23					EN2	VCC	17	VCC
	OFF
										100nF
		20					PVCC GENERATOR		14
	RSTIN									CGND
	CMDVCC	19					EN5		16	RST
								RST
	5V/3V	3					BUFFER
					SEQUENCER
	CLKDIV2(1)	1	HORSEQ				EN4		15
										CLK
							CLOCK
	CLKDIV2(2)	2	CLOCK				BUFFER
			CIRCUITRY						10	PRES
			CLK
									9
										PRES(2)
	XTAL1	24			EN3
		25	OSCILLATOR
	XTAL2(2)
						THERMAL
						PROTECTION
			ST8024L
	AUX1UC(2)	27					I/O		13	AUX1(2)
							TRANSCEIVER
	AUX2UC(2)	28					I/O		12	AUX2(2)
							TRANSCEIVER
	I/OUC	26					I/O		11	I/O
							TRANSCEIVER
			22
			GND							CS18100

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Contents	AN3275

Contents

1	Activation/deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 5
2	Card clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 8
3	Emergency deactivation/fault detection . . . . . . . . . . . . . . . . . . . . . . . . .		9
	3.1	PORADJ VDD undervoltage without external resistor bridge . . . . . . . . . . .	9
	3.2	PORADJ VDD undervoltage with external divider . . . . . . . . . . . . . . . . . . .	11
	3.3	Fault on card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	14
	3.4	VCC short-circuit fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	3.5	VDDP drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
	3.6	Overtemperature fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
4	ST8024L application hardware guidelines . . . . . . . . . . . . . . . . . . . . . .		18
	4.1	Power supply optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	4.2	Clock section optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	23
	4.3	Smartcard connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
	4.4	Input and output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	30
5	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		31

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AN3275	List of tables

List of tables

Table 1. CLK division factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Resistor values for VTH(ext)fall trip point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. VPORADJ trip point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4. VCC selection settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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List of figures	AN3275

List of figures

Figure 1. ST8024L internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. ST8024L activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Card activation/deactivation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. CLKDIV change clock duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. ST8024L automatic deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. External resistor bridge applied to PORADJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. VTH(ext) rise (external rising threshold voltage on VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 9. VTH(ext) fall (external falling threshold on VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10. Card extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11. ST8024L activation sequence (after tdebounce) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12. ST8024L current supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13. ISC short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14. Deactivation caused by VDDP drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 15. ST8024L application PCB top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16. ST8024L application PCB bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17. Step-up converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 18. ST8024L application PCB storage and pumping capacitors . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 19. ST8024L application PCB crystal (XTAL) connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 20. ST8024L application PCB smartcard connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 21. Ripple on VCC output voltage, 80 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 22. Ripple on VCC output voltage, 65 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 23. Ripple on VCC output voltage, 50 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 24. ST8024L application PCB schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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AN3275	Activation/deactivation sequence

1 Activation/deactivation sequence

The core of the ST8024L is the sequencer (shown in Figure 1 on page 1) that must coordinate the Enable signals for the activation and deactivation sequence as well as check for possible fault conditions. The smart card is basically a microcontroller and needs to be activated/deactivated by a correct sequence as required by the ISO/IEC7816 standard. The ST8024L activation and deactivation sequences are shown in Figure 2 and Figure 3 on page 6, respectively. Please refer to the ST8024L datasheet for details.

Figure 2 shows the activation sequence (the card is active) and CMDVcc taken from high to low. The activation sequence starts and the first block to be enabled is the step-up converter (VUP), linked to En1 (see Figure 1), while the last enabled signal is RST that allows the card software to start.

Figure 3 shows the deactivation sequence (when CMDVcc goes high). The circuit executes an automatic deactivation sequence, finishing in the inactive state after tde (deactivation time).

Figure 2. ST8024L activation sequence

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Activation/deactivation sequence	AN3275

Figure 3. Deactivation sequence

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AN3275	Activation/deactivation sequence

Figure 4. Card activation/deactivation flowchart

Start
OFF pin = VDD	No
	Error message
	“No Card”
Set CMDVcc
from high to low
	End
Initiate activation
Charge pump is ON
Regulator is ON
I/O is enabled
CLK is active
	Fault detection	No
	OFF pin = GND
Set RSTIN
from low to high	Yes
Start card	Alarm error message	No alarm
	“Error during
communication
	communication”
Completed
	Initiate deactivation
	RST goes high
Set CMDVcc	CLK is disabled
from low to high	I/O is disabled
	Regulator is OFF
	Charge pump is OFF
Initiate deactivation
RST goes low
CLK is disabled	Set CMDVcc
I/O is disabled
	from low to high
Regulator is OFF
Charge pump is OFF
	End
End
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Card clock	AN3275

2 Card clock

The card clock signal (CLK) is present on the CLK pin when the ST8024L is activated. It is linked to the internal En4 signal (see Figure 1 on page 1) and its frequency is obtained according to the settings in Table 1.

According to the ISO/IEC7816 specifications, the CLK duty cycle must be guaranteed between 45% and 55%, even when the status of CLKDIV1 or CLKDIV2 changes. Figure 5 shows how the ST8024L ensures duty cycle accuracy by waiting for completion of a whole clock cycle before changing the frequency (CLKDIV1 change, rising edge of CH2). The output duty cycle is 50% ±5%, even if the clock division changes.

The card clock signal (CLK) can be established by connecting a crystal (“XTAL”) between the XTAL1 and XTAL2 pins, or by an external signal applied to the XTAL1 pin. In this case, the XTAL2 pin must be left floating. The external signal voltage level must be limited between GND and VDD voltage.

Table 1.	CLK division factor
	CLKDIV1		CLKDIV2	fclk
	0		0	1/8 fXTAL
	0		1	1/4 fXTAL
	1		1	1/2 fXTAL
	1		0	fXTAL

Figure 5. CLKDIV change clock duty cycle

CH1 = output CLK waveform

CH2 = CLKDIV1 pin

Conditions: VDD = 3.3 V; VDDP = 5 V; 5/3V = H

Mode: ACTIVE

fXTAL = 10 MHz; CLKDIV2 = 0 V

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AN3275	Emergency deactivation/fault detection

3 Emergency deactivation/fault detection

ST8024L is equipped with a fault detection circuitry which monitors the following conditions (see Figure 1 on page 1):

●VDD undervoltage

●Fault on card removal

●VCC short-circuit

●VDDP drop, and

●Overtemperature

3.1PORADJ VDD undervoltage without external resistor bridge

	The PORADJ pin can be used to provide early detection of power failure on VDD. The
	ST8024L logic circuitry is supplied by VDD. In order to avoid voltage spikes that could cause
	damage or malfunction of the device and/or card, a voltage supervisor block is embedded
	(see Figure 1). This block monitors VDD and when it gets lower than VTH2 (falling threshold
	voltage on VDD, 2.45 V, typ), the supervisor immediately starts the deactivation sequence
	and VCC goes low.
	As VDD goes higher than VTH2 + VHYS2, (VHYS2 is the hysteresis of threshold voltage,
	100 mV, typ), after a certain amount of time (tw + tdebounce, where tw is the internal power-on
	reset pulse width, 8 ms typ, see Figure 6 on page 10), CMDVcc goes low. The activation
	sequence starts and VCC goes high. The PORADJ pin can be left floating, but connecting it
	to GND to avoid capturing noise is recommended.
Note:	See Fault on card removal on page 14 for tdebounce feature details.

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Emergency deactivation/fault detection	AN3275

Figure 6. ST8024L automatic deactivation sequence

	CH1 = CMDVcc
	CH2 = VCC
	CH3 =
		OFF
	CH4 = VDD
	Conditions: VDD = 3.3 V; VDDP = 5 V; 5/3V = H
	Mode: ACTIVE
	fXTAL = 10 MHz; CLKDIV2 = 0 V
Note:	Deactivation: VTH2 ≈2.393 V.
	Activation: As VDD ≥ VTH2 + VHYS2 (≈2.498 V) and				goes low, VCC goes high.
				CMDVcc

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