ST AN3275 APPLICATION NOTE

AN3275

Application note

Improving the performance of smartcard interfaces

using the ST8024L

Introduction

The ST8024L is a smartcard interface offered as a drop-in replacement for the ST8024
device. Enhancements and changes to the ST8024L device include:

● Improved performance by reducing the noise sensitivity in the charge pump

● Incorporated 1.8 V V

● Lower V

threshold voltage

TH

This application note provides information and suggestions for the optimal use and
performance of the ST8024L smartcard interface, including PCB layout, external component
placement, and connections (see ST8024L application hardware guidelines on page 18).
The implementation of all the blocks and procedures for card activation and deactivation
(see Figure 1) of the smartcard are also explained.

The ST8024L is a smartcard interface designed to minimize microprocessor hardware and
software complexity in all applications that require a smartcard (e.g., set-top box, electronic
payment, pay TV, and identification cards). The electrical characteristics of the ST8024L are
in accordance with New Digital Systems (NDS) and compliant with ISO7816-3, GSM11.11,
and EMV 4.0. Two devices (ST8024LCDR and ST8024LCTR) in the ST8024L family have
been certified by NDS.

CC

output

Figure 1. ST8024L internal block diagram

V

DD

100nF

21 6

18

23

20

19

3

1

2

24

25

27

28

26

SUPPLY

INTERNAL

REFERENCE

VOLTAGE SENSE

CLOCK

CIRCUITRY

OSCILLATOR

ST8024L

22

GND

HORSEQ

CLK

V

ALARM

ref

POWER_ON

SEQUENCER

V

OFF

RSTIN

CMDVCC

CLKDIV2

CLKDIV2

XTAL1

XTAL2

AUX1U C

AUX2U C

I/OUC

DD

5V/3V

(1)

R

1

PORADJ/1.8V

(1)

R

2

(1)

(2)

(2)

(2)

(2)

V

DDP

100nF 100nF

STEP-UP CONVERTER

INTERNAL OSCILLATOR

2.5 MHz

CLKUP

EN1

EN3

THERMAL

PROTECTION

C1–

7

EN2

PV

CC

GENERATOR

EN5

BUFFER

EN4

CLOCK

BUFFER

I/O

TRANSCEIVER

I/O

TRANSCEIVER

I/O

TRANSCEIVER

C1+

5

4

PGND

V

8

UP

100nF

V

CC

V

CC

RST

17

100nF

14

CGND

16

RST

15

CLK

10

PRES

9

(2)

PRES

13

(2)

AUX1

12

11

AUX2

I/O

(2)

CS18100

October 2010 Doc ID 17962 Rev 1 1/32

www.st.com

Contents AN3275

Contents

1 Activation/deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Card clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Emergency deactivation/fault detection . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 PORADJ VDD undervoltage without external resistor bridge . . . . . . . . . . . 9

3.2 PORADJ V

3.3 Fault on card removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 V

3.5 V

3.6 Overtemperature fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

short-circuit fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CC

drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DDP

undervoltage with external divider . . . . . . . . . . . . . . . . . . . 11

DD

4 ST8024L application hardware guidelines . . . . . . . . . . . . . . . . . . . . . . 18

4.1 Power supply optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Clock section optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.3 Smartcard connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.4 Input and output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 Doc ID 17962 Rev 1

AN3275 List of tables

List of tables

Table 1. CLK division factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Resistor values for V
Table 3. V
Table 4. V

Table 5. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PORADJ

CC

trip point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

selection settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

TH(ext)fall

trip point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Doc ID 17962 Rev 1 3/32

List of figures AN3275

List of figures

Figure 1. ST8024L internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. ST8024L activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. Deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Card activation/deactivation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. CLKDIV change clock duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. ST8024L automatic deactivation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. External resistor bridge applied to PORADJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. V
Figure 9. V

TH(ext) rise

TH(ext) fall

Figure 10. Card extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 11. ST8024L activation sequence (after t

Figure 12. ST8024L current supply sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 13. I

short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SC

Figure 14. Deactivation caused by V

Figure 15. ST8024L application PCB top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16. ST8024L application PCB bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 17. Step-up converter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 18. ST8024L application PCB storage and pumping capacitors . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19. ST8024L application PCB crystal (XTAL) connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20. ST8024L application PCB smartcard connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 21. Ripple on V
Figure 22. Ripple on V
Figure 23. Ripple on V

Figure 24. ST8024L application PCB schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

(external rising threshold voltage on VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

(external falling threshold on VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

debounce

drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DDP

output voltage, 80 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

CC

output voltage, 65 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

CC

output voltage, 50 mA pulsed load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

CC

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4/32 Doc ID 17962 Rev 1

AN3275 Activation/deactivation sequence

1 Activation/deactivation sequence

The core of the ST8024L is the sequencer (shown in Figure 1 on page 1) that must
coordinate the Enable signals for the activation and deactivation sequence as well as check
for possible fault conditions. The smart card is basically a microcontroller and needs to be
activated/deactivated by a correct sequence as required by the ISO/IEC7816 standard. The
ST8024L activation and deactivation sequences are shown in Figure 2 and Figure 3 on

page 6, respectively. Please refer to the ST8024L datasheet for details.

Figure 2 shows the activation sequence (the card is active) and CMDVcc

low. The activation sequence starts and the first block to be enabled is the step-up converter
(V

), linked to En1 (see Figure 1), while the last enabled signal is RST that allows the card

UP

software to start.

Figure 3 shows the deactivation sequence (when CMDVcc

an automatic deactivation sequence, finishing in the inactive state after t
time).

Figure 2. ST8024L activation sequence

goes high). The circuit executes

taken from high to

(deactivation

de

Doc ID 17962 Rev 1 5/32

Activation/deactivation sequence AN3275

Figure 3. Deactivation sequence

6/32 Doc ID 17962 Rev 1

AN3275 Activation/deactivation sequence

Figure 4. Card activation/deactivation flowchart

Start

OFF pin = V

Set CMDVcc

from high to low

Initiate activation

Charge pump is ON

Regulator is ON

I/O is enabled

CLK is active

Set RSTIN

from low to high

Start card

communication

Completed

Set CMDVcc

from low to high

DD

No

Error message

“No Card”

End

Fault detection

OFF pin = GND

Ye s

Ala

rm error message

“Error during

communication”

Initiate deactivation

RST goes high

CLK is disabled

I/O is disabled

Regulator is OFF

Charge pump is OFF

No

No alarm

Initiate deactivation

RST goes low

CLK is disabled

I/O is disabled

Regulator is OFF

Charge pump is OFF

End

Set CMDVcc

from low to high

End

AM04943v1

Doc ID 17962 Rev 1 7/32

Card clock AN3275

2 Card clock

The card clock signal (CLK) is present on the CLK pin when the ST8024L is activated. It is
linked to the internal En4 signal (see Figure 1 on page 1) and its frequency is obtained
according to the settings in Tab le 1 .

According to the ISO/IEC7816 specifications, the CLK duty cycle must be guaranteed
between 45% and 55%, even when the status of CLKDIV1 or CLKDIV2 changes. Figure 5
shows how the ST8024L ensures duty cycle accuracy by waiting for completion of a whole
clock cycle before changing the frequency (CLKDIV1 change, rising edge of CH2). The
output duty cycle is 50% ±5%, even if the clock division changes.

The card clock signal (CLK) can be established by connecting a crystal (“XTAL”) between
the XTAL1 and XTAL2 pins, or by an external signal applied to the XTAL1 pin. In this case,
the XTAL2 pin must be left floating. The external signal voltage level must be limited
between GND and V

Table 1. CLK division factor

voltage.

DD

CLKDIV1 CLKDIV2 f

0 0 1/8 f

0 1 1/4 f

1 1 1/2 f

10f

Figure 5. CLKDIV change clock duty cycle

clk

XTAL

XTAL

XTAL

XTAL

CH1 = output CLK waveform

CH2 = CLKDIV1 pin

Conditions: V

= 3.3 V; V

DD

= 5 V; 5/3V = H

DDP

Mode: ACTIVE

f

= 10 MHz; CLKDIV2 = 0 V

XTAL

8/32 Doc ID 17962 Rev 1

AN3275 Emergency deactivation/fault detection

3 Emergency deactivation/fault detection

ST8024L is equipped with a fault detection circuitry which monitors the following conditions
(see Figure 1 on page 1):

● V

● Fault on card removal

● V

● V

● Overtemperature

3.1 PORADJ VDD undervoltage without external resistor bridge

The PORADJ pin can be used to provide early detection of power failure on VDD. The
ST8024L logic circuitry is supplied by V
damage or malfunction of the device and/or card, a voltage supervisor block is embedded
(see Figure 1). This block monitors V
voltage on V
and V

As V
100 mV, typ), after a certain amount of time (t
reset pulse width, 8 ms typ, see Figure 6 on page 10), CMDVcc
sequence starts and V
to GND to avoid capturing noise is recommended.

undervoltage

DD

short-circuit

CC

drop, and

DDP

, 2.45 V, typ), the supervisor immediately starts the deactivation sequence

DD

goes low.

CC

goes higher than V

DD

. In order to avoid voltage spikes that could cause

DD

TH2

+ V

and when it gets lower than V

DD

HYS2

, (V

is the hysteresis of threshold voltage,

HYS2

w

+ t

debounce

, where tw is the internal power-on

(falling threshold

TH2

goes low. The activation

goes high. The PORADJ pin can be left floating, but connecting it

CC

Note: See Fault on card removal on page 14 for t

debounce

feature details.

Doc ID 17962 Rev 1 9/32

Emergency deactivation/fault detection AN3275

Figure 6. ST8024L automatic deactivation sequence

CH1 = CMDVcc

CH2 = V

CC

CH3 = OFF

CH4 = V

DD

Conditions: VDD = 3.3 V; V

Mode: ACTIVE

f

= 10 MHz; CLKDIV2 = 0 V

XTAL

Note: Deactivation: V

Activation: As V

≈2.393 V.

TH2

≥ V

DD

TH2

= 5 V; 5/3V = H

DDP

+ V

(≈2.498 V) and CMDVcc goes low, VCC goes high.

HYS2

10/32 Doc ID 17962 Rev 1