ST AN3267 Application note

AN3267

Application note

Impact of power MOSFET VGS on buck converter performance

Introduction

DC-DC buck converters are widely used in the computer and peripherals industry due to their high efficiency and simple electrical topology. In synchronous buck converter design and semiconductor device choice, converter efficiency maximization and switching behavior immunity to voltage stresses and fast transients are mandatory.

This document presents the simulation and experimental test results on a single-phase synchronous buck converter, highlighting the power MOSFET gate driving voltage impact on converter power management and switching behavior. In the latest generation of microprocessors for desktops and mobile equipment, ever increasing switching frequency and output current delivered to the CPU have become necessary.

These features push converter and system designers to critical choices for overall performance optimization. In fact, fast transients, together with high load currents, may degrade the converter thermal and power management. Therefore, a deep and accurate fine tuning of the main electrical parameters is mandatory. In this document, based on the single-phase synchronous buck converter topology, the impact of different power MOSFET gate-source voltages on converter efficiency and waveforms of main circuit nodes is thoroughly analyzed through OrCAD® simulations and bench test results, highlighting a perfect match between these two experiments.

August 2011

Doc ID 17890 Rev 1

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Contents	AN3267

Contents

1	Synchronous buck converter basic principles . . . . . . . . . . . . . . . . . . . .	4
2	Power MOSFET gate driving voltage requirements in real applications
	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6
3	Synchronous buck converter testing demonstration board . . . . . . . . .	7

3.1HS/LS switching behavior evaluation and phase node spike measurements

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Converter efficiency calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4	Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
5	References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	17
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18

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AN3267	List of figures

List of figures

Figure 1. Single-phase synchronous buck converter topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Testing demonstration board schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Power MOSFET waveforms @ 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Power MOSFET waveforms @ 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Phase node overshoot comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. Phase node vs. power MOSFET gate driving voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. Phase node @ 5 V / 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8. HS / LS signal comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. HS turn-on waveform @ 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 10. HS turn-on waveform @ 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11. Clamped inductive switching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 12. Rise time vs. power MOSFET G-S voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 13. Impact of VGS on power MOSFET RDS(on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 14. Efficiency comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 15. Thermal capture @ 16 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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Synchronous buck converter basic principles	AN3267

1 Synchronous buck converter basic principles

The synchronous buck converter is the most common electrical topology used for DC-DC converters which supply a CPU. In Figure 1, the basic schematic is depicted, where:

●S1 is the control FET (or high side FET)

●S2 is the synchronous FET (or low side FET).

In Figure 1 it is also possible to see that the power MOSFET’s gate signals are provided by the “control unit” in a synchronous way: S1 and S2 cannot be in an on-state simultaneously, avoiding the creation of a low-resistance path between the input voltage (VIN) and GND (shoot-through or cross-conduction), and generating a spurious power dissipation which worsens overall efficiency.

Figure 1. Single-phase synchronous buck converter topology

AM07212v1

L and Co form the output filter (low-pass filter), which generates a DC voltage from a square-wave signal on the low side drain (so-called phase node). The synchronous buck converter is a closed-loop topology as the output voltage is compared firstly with a reference voltage, producing an error signal; this voltage is then compared to a sawtooth signal, at the desired switching frequency (fsw) (integrated in the control unit) to switch the power MOSFETs on and off. In this way, the output voltage is stable when line or load changes occur.

Together with the output voltage regulation, the control unit provides complete logic control and various protections such as overcurrent, overvoltage, undervoltage, etc.

When S1 is ON, the current in the output coil increases linearly (dI/dt = (VIN-VOUT)/L and

VL = VIN - VOUT. During dead time (tdf), the energy store in L discharges through the bodydrain diode of S2 until its gate-source signal becomes high. Therefore, the load current

diverts from the body-drain diode to the channel (VDS,ON << VF, DIODE). Finally, both gate signals are low and the body-drain diode is forward-biased, allowing the load current flow.

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AN3267	Synchronous buck converter basic principles

During dead time and before HS turn-on, the LS device must remove the charge stored in the LS body-drain diode (reverse recovery charge process) before sustaining drain-source voltage. Therefore, the body-drain characteristics, in terms of reverse recovery current and charge, heavily impact the power MOSFET’s switching behavior and converter power losses, especially when the converter switching frequency rises.

In a synchronous buck converter, the low side drain is subjected to fast positive/negative slopes and high voltage spikes, which can exceed the low side absolute maximum voltage, degrading power MOSFET reliability up to its failure. For this reason, the right power MOSFET choice and system configuration, placing of the device on the board and the optimization of the stray inductances and parasitic, allow important phase node spike reduction, improving converter performance.

The input-output relationship of a buck converter is given by:

Equation 1

VOUT = DVIN

D is the converter duty cycle, defined as the ratio between the ON time of the HS and the switching period.

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Power MOSFET gate driving voltage requirements in real applications	AN3267

2Power MOSFET gate driving voltage requirements in real applications

In common synchronous buck converter topologies, two different solutions are widely used for the power MOSFET gate signal generation: driver and PWM logic controller integration in a single package or separately mounting the PWM logic controller and power MOSFET driver to turn the power switches on and off. The main controller suppliers provide a large number of products for both solutions.

The gate-source voltages, needed to turn the high side and low side devices on and off, are generated by the driver section, formed by a common push-pull circuit. Typically, these voltages are chosen in the range of 5 V to 10 V, depending on application features: switching frequency, converter efficiency target, maximum load current, power MOSFET number and electrical characteristics, driver DC power consumption minimization, and system power limitations. Typically, desktop applications need 10 V as the power MOSFET gate driving voltage, because currents delivered to the load are high and the output voltage becomes lower and lower (up to 1 V). In these operating conditions, low side devices are in the onstate for the majority of a switching period, so the conduction losses must be minimized to

improve the system power management: lower on-state losses mean lower RDS(on) and higher VGS (up to 10-12 V).

It is the contrary in the mobile segment, 5 V power MOSFET gate-source voltage choice is due to 5 V supply rail availability (it also feeds USB and HDD sections). In fact, the input voltage, which varies from 8 V to 19 V, is not suitable for driving power MOSFETs, while other voltages in the system are lower than 3.3 V and so cannot switch the devices on and off. In this way, the power MOSFET gate driving voltage is obtained “free”, without additional active and passive components.

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