Impact of power MOSFET VGS on buck converter performance
Introduction
DC-DC buck converters are widely used in the computer and peripherals industry due to
their high efficiency and simple electrical topology. In synchronous buck converter design
and semiconductor device choice, converter efficiency maximization and switching behavior
immunity to voltage stresses and fast transients are mandatory.
This document presents the simulation and experimental test results on a single-phase
synchronous buck converter, highlighting the power MOSFET gate driving voltage impact on
converter power management and switching behavior. In the latest generation of
microprocessors for desktops and mobile equipment, ever increasing switching frequency
and output current delivered to the CPU have become necessary.
These features push converter and system designers to critical choices for overall
performance optimization. In fact, fast transients, together with high load currents, may
degrade the converter thermal and power management. Therefore, a deep and accurate
fine tuning of the main electrical parameters is mandatory. In this document, based on the
single-phase synchronous buck converter topology, the impact of different power MOSFET
gate-source voltages on converter efficiency and waveforms of main circuit nodes is
thoroughly analyzed through OrCAD
perfect match between these two experiments.
®
simulations and bench test results, highlighting a
The synchronous buck converter is the most common electrical topology used for DC-DC
converters which supply a CPU. InFigure 1, the basic schematic is depicted, where:
●S1 is the control FET (or high side FET)
●S2 is the synchronous FET (or low side FET).
In Figure 1 it is also possible to see that the power MOSFET’s gate signals are provided by
the “control unit” in a synchronous way: S1 and S2 cannot be in an on-state simultaneously,
avoiding the creation of a low-resistance path between the input voltage (V
) and GND
IN
(shoot-through or cross-conduction), and generating a spurious power dissipation which
worsens overall efficiency.
L and Co form the output filter (low-pass filter), which generates a DC voltage from a
square-wave signal on the low side drain (so-called phase node). The synchronous buck
converter is a closed-loop topology as the output voltage is compared firstly with a reference
voltage, producing an error signal; this voltage is then compared to a sawtooth signal, at the
desired switching frequency (f
) (integrated in the control unit) to switch the power
sw
MOSFETs on and off. In this way, the output voltage is stable when line or load changes
occur.
Together with the output voltage regulation, the control unit provides complete logic control
and various protections such as overcurrent, overvoltage, undervoltage, etc.
When S1 is ON, the current in the output coil increases linearly (dI/dt = (V
VL = V
- V
IN
. During dead time (tdf), the energy store in L discharges through the body-
OUT
drain diode of S2 until its gate-source signal becomes high. Therefore, the load current
diverts from the body-drain diode to the channel (V
signals are low and the body-drain diode is forward-biased, allowing the load current flow.
4/19 Doc ID 17890 Rev 1
DS,ON
<< V
F, D IO D E
AM07212v1
IN-VOUT
)/ L a nd
). Finally, both gate
AN3267Synchronous buck converter basic principles
During dead time and before HS turn-on, the LS device must remove the charge stored in
the LS body-drain diode (reverse recovery charge process) before sustaining drain-source
voltage. Therefore, the body-drain characteristics, in terms of reverse recovery current and
charge, heavily impact the power MOSFET’s switching behavior and converter power
losses, especially when the converter switching frequency rises.
In a synchronous buck converter, the low side drain is subjected to fast positive/negative
slopes and high voltage spikes, which can exceed the low side absolute maximum voltage,
degrading power MOSFET reliability up to its failure. For this reason, the right power
MOSFET choice and system configuration, placing of the device on the board and the
optimization of the stray inductances and parasitic, allow important phase node spike
reduction, improving converter performance.
The input-output relationship of a buck converter is given by:
Equation 1
V
OUT
DV
=
IN
D is the converter duty cycle, defined as the ratio between the ON time of the HS and the
switching period.
Doc ID 17890 Rev 15/19
Power MOSFET gate driving voltage requirements in real applicationsAN3267
2 Power MOSFET gate driving voltage requirements in
real applications
In common synchronous buck converter topologies, two different solutions are widely used
for the power MOSFET gate signal generation: driver and PWM logic controller integration in
a single package or separately mounting the PWM logic controller and power MOSFET
driver to turn the power switches on and off. The main controller suppliers provide a large
number of products for both solutions.
The gate-source voltages, needed to turn the high side and low side devices on and off, are
generated by the driver section, formed by a common push-pull circuit. Typically, these
voltages are chosen in the range of 5 V to 10 V, depending on application features: switching
frequency, converter efficiency target, maximum load current, power MOSFET number and
electrical characteristics, driver DC power consumption minimization, and system power
limitations. Typically, desktop applications need 10 V as the power MOSFET gate driving
voltage, because currents delivered to the load are high and the output voltage becomes
lower and lower (up to 1 V). In these operating conditions, low side devices are in the onstate for the majority of a switching period, so the conduction losses must be minimized to
improve the system power management: lower on-state losses mean lower R
higher V
(up to 10-12 V).
GS
It is the contrary in the mobile segment, 5 V power MOSFET gate-source voltage choice is
due to 5 V supply rail availability (it also feeds USB and HDD sections). In fact, the input
voltage, which varies from 8 V to 19 V, is not suitable for driving power MOSFETs, while
other voltages in the system are lower than 3.3 V and so cannot switch the devices on and
off. In this way, the power MOSFET gate driving voltage is obtained “free”, without additional
active and passive components.
DS(on)
and
6/19 Doc ID 17890 Rev 1
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