ST AN3250 Application note

AN3250

Application note

M24LR64-R Multi-bank reference design description and settings

1 Introduction

The M24LR64-R multi-bank reference design has been created to help users increase the memory density of their Dual Interface EEPROM, and has been designed in a way that will minimize the antenna size and the I²C interface footprint on the PCB.

STMicroelectronics has prepared two reference designs:

●ANT4-M24LR-A is a 2-bank reference design with a 128-Kbit EEPROM user memory

●ANT5-M24LR-A is a 4-bank reference design with a 256-Kbit EEPROM user memory

Figure 1. ANT4-M24LR-A design

Figure 2. ANT5-M24LR-A design

The basic principle is to connect several M24LR64-R devices in parallel on the same I²C bus (in compliance with I²C specifications) and for them to share one single antenna.

This application note describes how the M24LR64-R Multi-Bank reference design works from the schematics and design perspective, and explains how to configure and use it.

Figure 3. Design overview

July 2010

Doc ID 17761 Rev 1

1/16

www.st.com

Contents	AN3250

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		1
2	Designing an M24LR64-R multi-bank application . . . . . . . . . . . . . . . . .		3
	2.1	Accessing several EEPROMs on the same I2C bus . . . . . . . . . . . . . . . . .	3
	2.2	Connecting several M24LR64-R devices on the same inductive antenna . 5
3	Setting up a Multi-Bank application . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	3.1	Basic principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8

3.1.1 Microcontroller's perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.2 RF reader's perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.3 Overall perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

	3.2	Setting up the Multi-Bank design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		12
		3.2.1	Microcontroller only is available during setup . . . . . . . . . . . . . . . . . . . .	12
		3.2.2	RFID reader only is available during setup . . . . . . . . . . . . . . . . . . . . . .	13
		3.2.3	Both Microcontroller and RFID reader are available during setup . . . . .	14
4	Conclusion .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
5	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			15

2/16	Doc ID 17761 Rev 1

AN3250	Designing an M24LR64-R multi-bank application

2 Designing an M24LR64-R multi-bank application

2.1Accessing several EEPROMs on the same I2C bus

The I2C specification allows the use of several devices on the same I2C bus, and this reference design follows this specification. Please refer to the I2C specification and to the M24LR64-R datasheet for more details.

Each device is accessed according to its value defined by the Device Select code.

Table 1.

Device Select code description

Device type identifier(1)

Chip Enable address(2)

Device Select code

E2(3)

1.The most significant bit (b7) is sent first.

2.E0 and E1 are compared against the respective external pins on the memory device.

3.E2 is not connected to any external pin. It is however used to address the M24LR64-R system area as described in the datasheet.

The M24LR64-R offers two Chip Enable pins, E0 and E1. These signals are used to set the values that are to be looked for on bits b2 and b1 of the 7-bit Device Select code.

Figure 4. Logic diagram

		VCC
		2
	E0-E1	SDA
		AC0
	SCL	M24LR64-R
	SCL	AC1
		AC1
		VSS

AI15106b

Table 2.	Signal descriptions
	Signal name	Function	Direction

E0, E1		Chip Enable	Input

SDA		Serial Data	I/O

SCL		Serial Clock	Input

AC0, AC1		Antenna coils	I/O

Doc ID 17761 Rev 1

3/16

Designing an M24LR64-R multi-bank application				AN3250

	Table 2.	Signal descriptions (continued)

		Signal name	Function	Direction

	VCC		Supply voltage
	VSS		Ground

E0 and E1 inputs must be tied to VCC (‘1’) or VSS (‘0’) to establish the Device Select code. When not connected (left floating), these inputs are read as low (‘0’). Using bits E0 and E1 of the Device Select code, up to four M24LR64-R devices can be accessed on the same I2C bus. This enables emulation of up to 256 Kbits of EEPROM.

In the configuration example shown in Figure 5, in order to access 256 Kbits of EEPROM, four 64-Kbit M24LR64-R devices are connected to the same I2C bus and the E0 and E1 signals of each device are assigned in a way to create an unique I2C address for each specific device.

Figure 5. Configuration example

VCC

M24LR64

VSS

I2C Bus	Ai12807a

M24LR64-R #0 (Bank 0)

Device addressed as (0,0): pin E0 connected to VSS and pin E1 connected to VSS.


		Device type identifier				Chip Enable address			RW

	b7		b6	b5	b4	b3	b2	b1	b0

Device Select code	1		0	1	0	E2	0	0
Device Select code	1		0	1	0	E2	0	0	RW

M24LR64-R #1 (Bank 1)

Device addressed as (0,1): pin E0 connected to VCC and pin E1 connected to VSS.


		Device type identifier				Chip Enable address			RW

	b7		b6	b5	b4	b3	b2	b1	b0

Device Select code	1		0	1	0	E2	0	1
Device Select code	1		0	1	0	E2	0	1	RW

4/16	Doc ID 17761 Rev 1

AN3250	Designing an M24LR64-R multi-bank application

M24LR64-R #2 (Bank 2)

Device addressed as (1,0): pin E0 connected to VSS and pin E1 connected to VCC.


		Device type identifier				Chip Enable address			RW

	b7		b6	b5	b4	b3	b2	b1	b0

Device Select code	1		0	1	0	E2	1	0
Device Select code	1		0	1	0	E2	1	0	RW

M24LR64-R #3 (Bank 3)

Device addressed as (1,1): pin E0 connected to VCC and pin E1 connected to VCC.


		Device type identifier				Chip Enable address			RW

	b7		b6	b5	b4	b3	b2	b1	b0

Device Select code	1		0	1	0	E2	1	1
Device Select code	1		0	1	0	E2	1	1	RW

To emulate a 256-Kbit device using four M24LR64-R devices, the 256 Kbits are dispatched as follows:

●M24LR64 #0 will store the 1st block of 64-Kbit EEPROM memory area.

●M24LR64 #1 will store the 2nd block of 64-Kbit EEPROM memory area.

●M24LR64 #2 will store the 3rd block of 64-Kbit EEPROM memory area.

●M24LR64 #3 will store the 4th block of 64-Kbit EEPROM memory area.

2.2Connecting several M24LR64-R devices on the same inductive antenna

The RF interface of M24LR64 devices is based on a passive RFID technology operating at 13.56 MHz in compliance with ISO/IEC 15693 standards. The basic principles of this RF technology and antenna design considerations are described in the following two application notes:

●AN2972: Designing an antenna for the M24LR64-R dual interface I²C/RFID device

●AN3178: Using a surface mount inductor as an M24LRxx antenna

The basic principle of the M24LR64-R's antenna is very simple; the external antenna

inductance (LINDUCTOR) that must be integrated on the PCB should match the M24LRxx's internal tuning capacitance (CTUNING_IC) in order to create a circuit resonating at 13.56 MHz. This is because ISO/IEC 15693 RFID readers operate in the 13.56 MHz high

frequency band.

fTUNING = ----Π------•-----------------------------------------•--------------------------------

2 LINDUCTOR CTUNINGIC

In this reference design, we connect a number n of M24LR64-R devices in parallel on the

same antenna. The resulting equivalent tuning capacitance (CTUNING_MULTI-BANK) is n times the tuning capacitance of a single M24LR64-R.

CTUNING_MULTI-BANK = n x CTUNING_IC

Doc ID 17761 Rev 1

5/16

+ 11 hidden pages