AN3244
Application note
EVAL6230QR demonstration board
Introduction
This application note describes the demonstration board of the DMOS driver for the threephase brushless DC motor driver L6230Q. The board implements a typical application
which can be used as a reference design to drive three-phase brushless DC motors with
currents up to 1 A DC.
Thanks to the small footprint of the L6230Q (QFN 5x5 mm) the PCB is very compact (32x31
mm).
Figure 1. EVAL6230QR demonstration board
November 2010 Doc ID 17742 Rev 1 1/9
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Demonstration board description AN3244
1 Demonstration board description
Table 1. EVAL6230QR: pin connections
Name Type Function
VS Power supply Power supply voltage.
PGND Ground Power ground terminal.
VS_FB Analog output Supply voltage feedback (1/115 divider ratio)
EN Logic input
IN1 Logic input Logic input half bridge 1.
EN1 Logic input Enable input half bridge 1.
IN2 Logic input Logic input half bridge 2.
EN2 Logic input Enable input half bridge 2.
IN3 Logic input Logic input half bridge 3.
EN3 Logic input Enable input half bridge 3.
DIAG Open-drain output
CPOUT Open-drain output Open-drain output of internal comparator.
CP- Analog input Inverting input of internal comparator.
CP+ Analog input Non-inverting input of internal comparator.
SENSE1 Analog output Half bridge 1 source pin.
SENSE2 Analog output Half bridge 2 source pin.
SENSE3 Analog output Half bridge 3 source pin.
OUT1 Power output Output half bridge 1.
OUT2 Power output Output half bridge 2.
OUT3 Power output Output half bridge 3.
Chip enable (active ‘H’). When ‘L’ switches OFF all power
DMOS.
Diagnostic pin. When ‘L’ signals an overcurrent or
overtemperature event.
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AN3244 Demonstration board description
Figure 2. EVAL6230QR connector description
The EN pin is chip enable (active high). The ENx pins enable the corresponding half-bridge.
When low logic level is applied, the half bridge output is in high-impedance status (both high
and low side MOS turned off).
The INx input pins drive the corresponding half bridge. When low logic level is applied, the
low side MOS is switched on, whereas a high logic level turns on the high side MOS.
A general purpose comparator is integrated in the IC, its inputs and open-drain output are
available on CP-, CP+, and CPOUT. It can be used for the current control or BEMF zero
crossing detection (refer to the L6230; DMOS driver for three-phase brushless DC motor,
datasheet for more details).
The power supply feedback and sensing signals are available for external conditioning, for
example, to perform a field oriented control driving method.
Ta bl e 2 summarizes the electrical specification of the application, Figure 3 shows the
electrical schematic and Tab le 3 contains the parts list.
Table 2. EVAL6230QR: electrical specification (recommended values)
Parameter Value
Supply voltage range (VS) 8 to 52 Vdc
RMS output current rating (OUTx) up to 1.4 A
Switching frequency up to 100 kHz
Input and enable voltage range 0 to +5 V
Comparator input voltage range 0 to +5 V
Operating temperature range -25 °C to +125 °C
L6230Q thermal resistance junction to ambient 42 °C/W
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Demonstration board description AN3244
Figure 3. EVAL6230QR board schematic
VS_FBVS_FB
R14
8k2
R14
8k2
VS
R12
R12
470k
470k
R13
R13
470k
470k
VS
C4
C4
VSVS
220nF/25V
220nF/25V
D1
D1
PGNDPGND
C2
C2
100uF/63V
100uF/63V
12
Bat46SW
Bat46SW
3
C1
C1
220nF/100V
220nF/100V
C3
C3
10nF/25V
10nF/25V
20
22
24
17
21
1
2
NC - EPAD
VSB
VSA
VCP
VBOOT
GND
GND
OUT2OUT2
OUT1OUT1
OUT3OUT3
31
23
6
3
5
8
4
7
NC - EPAD
NC - EPAD
NC - EPAD
NC - EPAD
NC - EPAD
NC - EPAD
19
OUT1
OUT3
OUT2
L6230Q
L6230Q
18
NC10NC
SENSE3
SENSE2
SENSE1
CP+
CP-
CPOUT
SENSE1SENSE1
SENSE2SENSE2
SENSE3SENSE3
R11
0.47/0.5W
R11
N.O.
N.O.
N.O.
N.O.
R10
R10
R9
R9
0.47/0.5W
0.47/0.5W
0.47/0.5W
0.47/0.5W
0.47/0.5W
12
JP2
JP2
25
29
30
15
11
JP1
JP1
1 2
1 2
EN2
IN1
DIAGDIAG
C5
U1
U1
5.6nFC55.6nF
R1 100kR1 100k
DIAG-EN
9
ENEN
27
EN1EN1
EN1
26
IN1IN1
14
EN2EN2
13
IN2IN2
IN2
EN3
16
EN3EN3
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28
IN3IN3
IN3
L6230Q
L6230Q
R8
100kR8100k
R7
100kR7100k
R6
100kR6100k
R5
100kR5100k
R4
100kR4100k
R3
100kR3100k
R2
100kR2100k
CPOUTCPOUT
CP-CP-
CP+CP+
AN3244 Demonstration board description
Table 3. EVAL6230QR parts list
Part reference Part value Part description
C1 220 nF/100 V Capacitor
C2 100 µF/63 V Capacitor
C3 10 nF/25 V Capacitor
C4 220 nF/25 V Capacitor
C5 5.6 nF Capacitor
D1 BAT46SW Diodes
R1 ÷ R8 100 kΩ 5 % 0.25 W Resistor
R9, R10, R11 0.47 Ω - 0.5 W Resistor
R12, R13 470 kΩ 5 % 0.25 W Resistor
R14 8.2 kΩ 5 % 0.25 W Resistor
U1 L6230Q
Three-phase BLDC motor driver in
VFQFPN5x5
D1, C3, and C4 realize a charge pump circuit, which generates the supply voltage for the
high side integrated MOSFETs. Due to voltage and current switching at relatively high
frequency, these components are connected together through short paths in order to
minimize induced noise on other circuitries.
R2 and C5 are used by the overcurrent protection integrated circuitry to set the protection
timings (disable time, t
DISABLE
, is about 200 µs and delay time, t
, is about 1 µs with the
DELAY
values in Ta bl e 3 ).
Figure 4, Figure 5, and Figure 6 show the component placement and the two layer layout of
the EVAL6230QR demonstration board. A GND area has been used for the IC power
dissipation.
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Demonstration board description AN3244
Figure 4. EVAL6230QR component placement
32 mm
Figure 5. Top layer layout
31 mm
AM02585v1
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AN3244 Demonstration board description
Figure 6. Bottom layer layout
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Revision history AN3244
2 Revision history
Table 4. Document revision history
Date Revision Changes
26-Nov-2010 1 Initial release
8/9 Doc ID 17742 Rev 1
AN3244
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Doc ID 17742 Rev 1 9/9
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