ST AN3216 Application note
AN3216
Application note
Getting started with STM32L1xxx hardware development
Introduction
This application note is intended for system designers who require a hardware
implementation overview of the development board features such as the power supply, the
clock management, the reset control, the boot mode settings and the debug management. It
shows how to use STM32L1xxx product families and describes the minimum hardware
resources required to develop an STM32L1xxx application.
Detailed reference design schematics are also contained in this document with descriptions
of the main components, interfaces and modes.
Table 1. Applicable products
Type Product sub-class
Microcontroller STM32L1xxx
May 2012 Doc ID 17496 Rev 6 1/31
www.st.com
Contents AN3216
Contents
1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7
1.1.2 Independent LCD supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.1 Power-on reset (POR)/power-down reset (PDR),
brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.3 Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.4 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 15
2.3 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.1 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 16
2.4 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/10 Doc ID 17496 Rev 1
AN3216 Contents
4.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.3 Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 22
4.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 22
5 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 Ground and power supply (V
, VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SS
5.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 17496 Rev 1 3/10
List of tables AN3216
List of tables
Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3. Debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4. SWJ I/O pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/4 Doc ID 17496 Rev 6
AN3216 List of figures
List of figures
Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. External clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Crystal/ceramic resonators
Figure 11. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Typical layout for V
Figure 15. STM32L152VB(T6) microcontroller reference schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 27
DD/VSS
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Doc ID 17496 Rev 1 5/10
Power supplies AN3216
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1 Power supplies
1.1 Introduction
The device requires a 2.0 V to 3.6 V operating voltage supply (VDD), to be fully functional at
full speed. This maximum frequency is only achieved when the digital power voltage V
is equal to 1.8 V (product voltage range 1).
CORE
Product voltage range 2 (V
V
operates from 1.65 V to 3.6 V. Frequency is limited to 16 MHz and 4 MHz when the
DD
= 1.5 V) and 3 (V
CORE
= 1.2 V) can be selected when the
CORE
device is in product voltage range 2 and 3 respectively.
When the ADC and brownout reset (BOR) are not used, the device can operate at power
voltages below 1.8 V down to 1.65 V.
Digital power voltage (V
) is provided with an embedded linear voltage regulator with
CORE
three different programmable ranges from 1.2 to 1.8 V (typical).
Figure 1. Power supply overview
Note: V
6/10 Doc ID 17496 Rev 6
DDA
and V
must be connected to VDD and VSS, respectively.
SSA
AN3216 Power supplies
1.1.1 Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC and the DAC have an independent power supply
that can be filtered separately, and shielded from noise on the PCB.
● The ADC voltage supply input is available on a separate V
● An isolated supply ground connection is provided on the V
V
DDA
(see I
and V
(ADCx), IDD(DAC), IDD(COMPx), I
DD
require a stable voltage. The consumption on V
REF
VDDA
, and I
VREF
in the product datasheets for
further information).
pin
DDA
pin
SSA
can reach several mA
DDA
When available (depending on the package), V
must be tied to V
REF¨
SSA
.
On BGA 64-pin and all 100-pin or more packages
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
V
, a separate external reference voltage which is lower than VDD. V
REF+
is the highest
REF+
voltage, represented by the full scale value, for an analog input (ADC) or output (DAC)
signal.
● For ADC
– 2.4 V V
– 1.8 V V
– 2.4 V V
– 1.8 V V
– When product voltage range 3 is selected (V
REF+
REF+
REF+
REF+
= V
= V
V
< V
for full speed (ADCCLK = 16 MHz, 1 Msps)
DDA
for medium speed (ADCCLK = 8 MHz, 500 Ksps)
DDA
for medium speed (ADCCLK = 8 MHz, 500 Ksps)
DDA
for low speed (ADCCLK = 4 MHz, 250 Ksps)
DDA
= 1.2 V), the ADC is low speed
CORE
(ADCCLK = 4 MHz, 250 Ksps)
● For DAC
– 1.8 V V
REF+
< V
DDA
On packages with 64 pins or less (except BGA package)
V
and V
REF+
supply (V
DDA
pins are not available. They are internally connected to the ADC voltage
REF-
) and ground (V
SSA
).
Doc ID 17496 Rev 6 7/10
Power supplies AN3216
1.1.2 Independent LCD supply
The V
pin is provided to control the contrast of the glass LCD. This pin can be used in
LCD
two ways:
● It can receive, from an external circuitry, the desired maximum voltage that is provided
on the segment and common lines to the glass LCD by the microcontroller.
● It can also be used to connect an external capacitor that is used by the microcontroller
for its voltage step-up converter. This step-up converter is controlled by software to
provide the desired voltage to the segment and common lines of the glass LCD.
The voltage provided to the segment and common lines defines the contrast of the glass
LCD pixels. This contrast can be reduced when the dead time between frames is
configured.
● When an external power supply is provided to the V
to 3.6 V. It does not depend on V
● When the LCD is based on the internal step-up converter, the V
connected to a capacitor (see the product datasheets for further information).
1.1.3 Voltage regulator
The internal voltage regulator is always enabled after reset. It can be configured to provide
the core with three different voltage ranges. Choosing a range with low V
consumption but lowers the maximum acceptable core speed. Consumption ranges in
decreasing consumption order are as follows:
● Range 1, available only for V
● Range 2 allows CPU frequency up to 16 MHz
● Range 3 allows CPU frequency up to 4 MHz
pin, it should range from 2.5 V
.
DD
above 2.0 V, allows maximum speed
DD
LCD
pin should be
LCD
reduces the
core
Voltage regulator works in three different modes depending on the application modes.
● In Run mode, the regulator supplies full power to the V
domain (core, memories and
core
digital peripherals).
● In Stop mode, Low power run and Low power wait modes, the regulator supplies low
power to the V
● In Standby mode, the regulator is powered off. The contents of the registers and SRAM
domain, preserving the contents of the registers and SRAM.
core
are lost except for those concerned with the Standby circuitry.
8/10 Doc ID 17496 Rev 6
AN3216 Power supplies
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OPTIONAL
1.2 Power supply schemes
The circuit is powered by a stabilized power supply, VDD.
● The V
single Tantalum or Ceramic capacitor (minimum 4.7 µF typical 10 µF) for the package +
one 100 nF Ceramic capacitor for each V
● The V
Ceramic capacitor + 1 µF Tantalum or Ceramic capacitor).
● The V
external reference voltage is applied on V
connected on this pin. To compensate peak consumption on Vref, the 1 µF capacitor
may be increased up to 10µF when the sampling speed is low. When ADC or DAC is
used, VREF+ must remain between 1.8 V and VDDA. VREF+ can be grounded when
ADC and DAC are not active; this enables the user to power down an external voltage
reference.
● Additional precautions can be taken to filter analog noise: V
V
DD
pins must be connected to VDD with external decoupling capacitors; one
DD
pin).
DD
pin must be connected to two external decoupling capacitors (100 nF
DDA
pin can be connected to the V
REF+
external power supply. If a separate,
DDA
, a 100 nF and a 1 µF capacitor must be
REF+
can be connected to
DDA
through a ferrite bead.
Figure 2.
1. Optional. If a separate, external reference voltage is connected on V
1 µF) must be connected.
2. V
REF
3. N is the number of V
Power supply scheme
+ is either connected to V
and V
DD
DDA
SS
or to V
inputs.
REF
.
1.3 Reset and power supply supervisor
The input supply to the main and low power regulators is monitored by a power-on/powerdown/brownout reset circuit. Power-on/power-down reset are a null power monitoring with
fixed threshold voltages, whereas brownout reset gives the choice between several
thresholds with a very low, but not null, power consumption.
, the two capacitors (100 nF and
REF+
In addition, the STM32L1xxx embeds a programmable voltage detector that compares the
power supply with the programmable threshold. An interrupt can be generated when the
power supply drops below the V
the V
threshold. The interrupt service routine then generates a warning message and/or
PVD
threshold and/or when the power supply is higher than
PVD
puts the MCU into a safe state.
Doc ID 17496 Rev 6 9/10
Power supplies AN3216
VDD/V
DDA
PVD output
100 mV
hysteresis
V
PVD
V
BOR
hysteresis
100 mV
IT enabled
BOR reset
(NRST)
POR/PDR reset
(NR ST)
PVD
BOR always active
POR/PDR (BOR not available)
ai17211b
POR
V
/
PDR
V
BOR/PDR reset
(NRST)
BOR disabled by option byte
(Note 1)
(Note 2)
(Note 3)
(Note 4)
Figure 3. Power supply supervisors
1. The PVD is available on all STM32L devices and it is enabled or disabled by software.
2. The BOR is available only on devices operating from 1.8 to 3.6 V, and unless disabled by option byte it
masks the POR/PDR threshold.
3. When the BOR is disabled by option byte, the reset is asserted when V
4. For devices operating from 1.65 to 3.6 V, there is no BOR and the reset is released when V
POR level and asserted when V
goes below PDR level.
DD
goes below PDR level.
DD
DD
goes above
10/10 Doc ID 17496 Rev 6
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