ST AN3206 Application note

	AN3206
	Application note
	PCB design guidelines for the STM32W108 platform
1	Introduction
	STMicroelectronics provides a IEEE 802.15.4 product design engineer with a number of
	paths towards the successful design of a IEEE 802.15.4-compliant solution based on the
	STMicroelectronics STM32W108 family of system-on-chip (SoC) platforms. The
	STM32W108xx kits contain software, hardware, and documentation designed for
	developers to create applications efficiently on a tested and controlled platform. Once the
	design team is familiar with ST's STM32W108xx products and the available IEEE 802.15.4
	software libraries and stacks, the next step in the design path involves designing application-
	specific hardware to meet product requirements.
	This application note is intended to accompany the reference designs and provide detailed
	information regarding the design decisions employed within STMicroelectronics designs. In
	addition, it details the design guidelines for developing an application-specific IEEE 802.15.4
	design using an STM32W108xx device.
	After reading this document, developers should be able to successfully implement a design
	with an STM32W108xx device. For further information, visit the STMicroelectronics web site
	at www.st.com/stm32w.
	Due to the application-specific nature of STMicroelectronics reference designs, ST
	recommends that hardware designers familiarize themselves with the most recent reference
	design available. This document is applicable to the following STM32W108xx kits:
	● STM32W108xx starter kit (part number: STM32W-SK)
	● STM32W108xx extension kit (part number: STM32W-EXT)
	● STM32W108xx low-cost RF control kit (part number: STM32W-RFCKIT)
Note:	The STM32W108 Reference Design is built on a 4-layer, FR-4 epoxy PCB.
	The STM32W108-based Reference Design includes the following elements:
	■ Schematics (in PDF format)
	■ Bill of materials (BOM)
	■ Gerber files
	While the Reference Design includes most of the information required to start an
	application-specific design, if additional items needed, please contact STMicroelectronics
	Customer Support on the STMicroelectronics web site www.st.com/stm32w.

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Contents	AN3206

Contents

1	Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		1
2	Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3
	2.1	RF design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4

2.1.1 STM32W108 RF ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.2 Optimizing for TX (Boost mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.3 Matching network circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.4 Harmonic filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.5 Band-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.6 Antenna matching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 RF layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 PCB tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Other design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3	Non-RF design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		10
	3.1	High-frequency (24-MHz) crystal reference (X1, C5, and C6) . . . . . . . . .	10
	3.2	Optional Low-frequency crystal reference (X2, C27 and C26) . . . . . . . . .	11
	3.3	1.8V regulator load capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.4	1.2V regulator loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.5	1.8V net decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.6	1.8V analog to 1.8V digital filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	12
	3.7	RF test connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13
4	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13

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2 Reference design

Figure 1 shows a block diagram of the reference design.

Figure 1. Block diagram of STM32W108 reference design (48-pin package)

The STM32W108 reference design uses an external 50/100 Balun as its primary RF component. It provides an unbalanced to differential 50-to-100 Ohms conversion to present the STM32W108 with its optimal load. A single inductor makes up the matching network and optimizes RF performance. A band pass filter keeps the conducted harmonics within FCC and ETSI limits.

Due to the market demand that IEEE 802.15.4 software maximize their communication range, this design has been optimized accordingly. In Boost mode, the STM32W108 reference design achieves a high transmit output power across the 16 channels. This section describes the design decisions behind each of the items shown in Figure 1.

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2.1RF design guidelines

2.1.1STM32W108 RF ports

	The STM32W108's bi-directional RF port (pins RF_P and RF_N) provides access to a low
	noise amplifier (LNA) and a power amplifier (PA) through a shared differential interface. The
	disabled high-Z state of either the PA or the LNA enables transmitting and receiving through
	the shared port without the need for a conventional T/R switch.
	An ‘alternate’ PA-only port (pins RF_TX_ALT_P and RF_TX_ALT_N) is also provided. This
	function is achieved via an additional PA. Design considerations for this alternate PA are not
	covered in this document.
Note:	The on-chip parasitic capacitance is different between the two ports and will slightly alter the
	off-chip matching component values.

2.1.2 Optimizing for TX (Boost mode)

The STM32W Reference Design has been optimized for maximum transmitter (TX) output power in Boost mode using practical components and readily available printed circuit board (PCB) substrates. The optimum load at the PA on the silicon die is approximately 700Ω when the PA/LNA device capacitance is resonated-out. This maximizes the voltage swing at the drains of the PA devices within the available supply voltage. Too large a load causes voltage limiting whereas too small a load does not make full use of the available supply voltage. Figure 2 illustrates a die-level simulation of the load impedance and its effect on PA output power.

Figure 2. Simulated Boost output power with PA load resistance

Optimizing the TX output performance in Boost mode does not cause degradation in either Normal mode or RX sensitivity. Because the receiver is CMOS-based, it amplifies the input signal voltage, rather than its current. The receiver noise is a fixed value of noise voltage that may be referred to its input. It might be expected that increasing the transformation

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would yield higher signal voltage swings at the LNA input, making the input referred noise less significant and thereby improving sensitivity. However, this also increases the source resistance, thereby increasing the source noise voltage. In practice at the 700Ω level, the improvement gradient is very small and the transmit output power exhibits far greater sensitivity to load variation than receiver sensitivity. The main objective for receive sensitivity is to minimize network loss, which is a common objective when transmitting.

The optimum load presented to the pins of the STM32W108 device must take into consideration not only the optimum PA load but also on-chip parasitic capacitance and package bond-wire inductance. It is estimated that the optimum load presented to the pins is 27 + j95Ω (series impedance). This is equivalent to a parallel resistance of 368Ω combined with a parallel inductance of 6.6 nH.

Optimal Load for STM32W (series impedance)	27 + j95	Ohms

2.1.3Matching network circuit design

The term “matching” typically implies conjugate power matching. It is important to understand that the STM32W PA is not power matched according to the traditional definition. The term is used in this document to describe the design of an optimal PA impedance.

The best way to understand ST's approach towards optimizing the STM32W “matching” is to plot on the Smith chart the impedance of the ideal 700Ω PA load transformed by the chip/package parasitic elements. The combination of the ideal load with the parasitic elements is the conjugate of the ideal load presented to the package pins. Knowing the combined load and its conjugate allows the designer to approach matching in a more traditional sense, namely, “How do we get to 50Ω?”

It is also necessary at some point in the network to include a balanced-to-unbalanced (balun) conversion. Use of a ‘proper’ balun has performance benefits related to commonmode suppression both on transmit and receive sides.

There are a variety of balun architectures and solutions available. The primary objective of any of ST's reference designs is to minimize design complexity and maximize time to market. Therefore, ST decided to implement its primary reference design with a ceramic balun. The cost of ceramic baluns is low, and they are available from a number of vendors.

Ceramic baluns are available in 1:1 (50 to 50Ω), 2:1 (100 to 50Ω), and 4:1 ratios (200 to 50Ω).

The magnitude of the reflection coefficient, | L |, in these three cases is:

●1:1 (50Ω) → 0.8

●2:1 (100Ω) → 0.76

●4:1 (200Ω) → 0.8

This implies that a 2:1 ceramic balun should offer the lowest network loss, assuming identical balun loss because it requires the least transformation.

Investigation into ceramic balun performance from various vendors reveals that 1:1 and 2:1 ratio baluns often have an approximate 0.3 dB insertion loss advantage over a 4:1 ratio. Thus the use of a 2:1 ceramic balun is preferred.

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