This application note describes the characteristics and performance of a 250 W wide range
input and power factor corrected power supply designed to be used in an ATX application.
Good electrical performance allows meeting the most demanding efficiency targets.
The converter consists of four main blocks:
■ A PFC front-end stage using the L6563S PFC controller which generates the +400 V bus
voltage.
■ An AHB (Asymmetrical half bridge) stage using the L6591 ZVS half bridge controller
which performs the conversion from the high voltage bus to the +12 V output providing
insulation.
■ Two DC-DC post-regulator stages using the L6727 which obtain the +5 V and +3.3 V
outputs from the +12 V bus.
■ An auxiliary power supply (STANDBY) stage using the VIPer27H in isolated flyback
configuration which provides the +5 V_SB output with 10 W power capability.
AN3203Main characteristics and circuit description
1 Main characteristics and circuit description
Here are the main characteristics of the power supply:
●Input mains range:
–Vin: 88 ~ 264 Vrms
–f: 45 ~ 66 Hz
●Outputs:
–+12 Vdc ± 2 % - 13.5 A
–+5 Vdc ± 2 % - 12 A
–+3.3 Vdc ± 2 % - 8 A
–+5 V_SB ± 2 % - 2 A
●Standby consumption: < 0.2 W
●Protection:
–Short-circuit
–Overload
–Output overvoltage
–Brownout
●PCB type and size:
–FR4
–Double side CU 70 µm
–148 x 120 mm
●Safety: according to EN60950
●EMI: according to EN55022 - class B
The EVL250W-ATX80PL demonstration board is made up of four main blocks, the
schematics are shown in Figure 2, 3, 4, and 5.
The front-end PFC stage is realized using a boost topology working in line modulated fixed
off time (LM-FOT) mode, described in STMicroelectronics’ application notes, AN1792;
Design of Fixed-Off-Time controlled PFC pre-regulators with the L6562 andAN3142;
Solution for designing a 400 W Fixed-Off-Time controlled PFC preregulator with the L6563S
and L6563H. The LM-FOT operation offers the advantage of having CCM operation (with
lower rms current with respect to TM mode) without the need to use a complex and
expensive controller. Therefore, it is possible to use the simple L6563S, enhanced TM PFC
controller, which integrates all the functions and protection, needed to control the stage, and
an interface with the downstream DC-DC converter.
The power stage of the PFC is realized with inductor L4, MOSFET Q1 and Q2, diode D3,
and capacitor C1. The LM-FOT operation is obtained with components D6, R15, C10, R14,
C9, R13, and Q3.
The PFC delivers a stable high voltage bus (+400 V nominal) to the downstream converters
(AHB and flyback) and provides for the reduction of the current harmonics drawn from the
mains, in order to meet the requirements of the European EN61000-3-2 norm and the
Japanese JEITA-MITI norm.
The second stage is an asymmetrical half bridge converter, driven by the L6591, a
STMicroelectronics controller dedicated to this topology. This IC integrates all the functions
Doc ID 17402 Rev 25/49
Main characteristics and circuit descriptionAN3203
and protection needed by the AHB stage and an interface for the PFC controller. The L6591
includes two gate drivers for the half bridge MOSFETs and a fixed frequency
complementary PWM logic with 50 % maximum duty cycle with programmable dead time
and current mode control technique.
Other features of this IC are pulse-by-pulse overcurrent protection, transformer saturation
detection, overload protection (latched or auto-restart), and programmable soft-start. There
is also a high voltage startup circuit, a burst mode logic for low load operation, and the
adaptive UVLO onboard, which are not used in this design as they are designed for adapter
applications (see AN2852).
The following is a description of the power circuit of this stage. The half bridge switches
Q101 and Q102 are connected to the output voltage of the PFC. The half bridge node drives
the series of C101 (DC blocking capacitor) and the primary side of the transformer T1. This
transformer has two secondary windings with a center tap connected to the secondary
ground. The other ends are connected to the sources of MOSFETs Q201 and Q202, which
replace output diodes in order to perform the synchronous rectification. Two extra windings
allow, with few external passive components, a self driven synchronous rectification to be
obtained. This solution allows efficiency to be increased without the extra cost of a
dedicated SR controller IC.
Q201 and Q202 drains are connected to the output inductor L201 that, together with output
capacitors C201 and C202, acts as a low pass filter. The signal +12 VA is then post filtered
(with L5 and C207) to obtain the +12 V output voltage.
The design of transformer T1 is a trade-off between ZVS operation and the required
electrical performance/efficiency. ZVS can be obtained acting on the magnetizing
inductance or on the primary side leakage inductance. In more detail, ZVS could be met by:
●Decreasing the magnetizing inductance
●Increasing the leakage inductance
Low values of magnetizing inductance generate high magnetizing current. This helps to
reach ZVS but it also increases the total primary side rms current and therefore the related
losses. In this design a value of 500 µH has been selected.
On the other hand, ZVS could be obtained by increasing the leakage inductance. If such a
parameter is increased, the primary side current takes more time before reversing its
direction and therefore ZVS is more easily met. A high leakage inductance value leads to
duty cycle losses, reducing the effective range of duty cycle usable. This creates problems
with hold-up requirements and makes it necessary to work with very narrow duty cycles with
nominal input voltage generating high rms currents in the circuit.
A value of 12 µH has been selected as the leakage inductance.
Because of these reasons, in this design ZVS is always met at low side MOSFET turn-on
while it is met only for medium-high loads at high side MOSFET turn-on. Even at mediumlow loads Q101 is turned on with a Vds well below the half bridge input voltage.
The L6591 LINE pin is used for startup sequencing. It shares with the L6563S the voltage
divider made up of R20, R21, R22, R29, and R26 that senses the PFC output voltage. The
AHB stage is activated when the bulk voltage reaches about 380 V.
The DISABLE pin (latched protection) is driven by the L6563S PWM_LATCH pin and stops
the AHB stage in case of PFC feedback disconnection.
The oscillator is programmed in order to have a switching frequency of about 80 KHz and to
use the minimum dead time (about 310 ns).
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AN3203Main characteristics and circuit description
The PFC_STOP pin is the interface for the PFC controller, it is connected to the L6563S
RUN pin through R104 and it stops the PFC operation (not latched) in case of overload,
output short-circuit or transformer saturation detection.
The +5 V and +3.3 V are obtained from the +12 VA bus (AHB output) thanks to two DC-DC
converters mounted on two daughter boards. These stages are driven by the L6727, single
phase PWM controller. The topology is a standard step down. For more information please
refer to the L6727; Single phase PWM controller datasheet.
The last stage is the auxiliary power supply that provides the +5 V_SB output (2A capability)
and the VCC supply for the L6563S and L6591. It is realized with a standard flyback
topology operating in CCM/DCM with fixed frequency using the VIPer27H. This stage takes
the PFC output voltage as input and is always working when the mains is plugged in. The
VIPer27H has all the protection needed to safely drive the standby stage. It protects the
circuitry in case of overload, output short-circuit, or output overvoltage.
All the other stages (and therefore the outputs +12 V, +5 V and +3.3 V) can be turned on /
off using the signal PS_ON. If it is disconnected or connected to GND, the OPTO2 current is
zero, Q601 is open and the VCC of the L6563S and L6591 is zero. If PS_ON is connected to
+5 V_SB, the OPTO2 current turns Q601 on. This BJT, together with the Zener diode
ZD601, acts as a linear regulator and provides the supply to the PFC and AHB controllers.
The same optocoupler is used to turn off the PFC and AHB stages in case of an overvoltage
on one of the three main outputs. Such protection is realized with three Zener diodes (one
for each output) that set the OVP thresholds. If one of the three output voltages goes over its
threshold, the Zener diode conducts and turns on the latch realized with Q604 and Q605.
The current in OPTO2 is reduced to zero (overriding the PS_ON information) and the
L6563S and L6591 are turned off.
Only the +5 V_SB stays on and continues to keep the protection latched.
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Main characteristics and circuit descriptionAN3203
Figure 2.Electrical diagram: input EMI filter and PFC stage
8/49Doc ID 17402 Rev 2
AN3203Main characteristics and circuit description
Figure 3.Electrical diagram: AHB stage
!-V
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Main characteristics and circuit descriptionAN3203
Figure 4.Electrical diagram: DC-DC stage
10/49Doc ID 17402 Rev 2
!-V
AN3203Main characteristics and circuit description
Figure 5.Electrical diagram: standby stage
!-V
Doc ID 17402 Rev 211/49
Asymmetrical half bridge operationAN3203
2 Asymmetrical half bridge operation
2.1 AHB typical waveforms
In Figure 6 the primary side key waveforms during steady-state operation with full load
applied are shown. Figure 7 shows the detail of the two transitions during one switching
cycle.
The AHB stage has been designed to operate at about 80 kHz with a nominal input voltage
of 400 V (PFC output bus). The transformer design is the result of a trade-off between the
half bridge MOSFETs zero voltage switching (ZVS) operation requirements, the primary rms
current, and duty cycle losses. In fact, ZVS can be achieved by reducing the magnetizing
inductance or increasing the leakage inductance. With the output power of this board, the
first solution implies having very high rms primary current which leads to high losses. The
second solution introduces the so called “duty cycle losses”. When the leakage inductance
is de-magnetizing, the voltages on the secondary side windings are zero and therefore the
output mean value is reduced with respect to the same half bridge duty cycle and negligible
leakage inductance. Duty cycle losses limit the hold-up capability of the power supply
because they increase the minimum input voltage that guarantees output regulation.
In this design the system works with ZVS for both MOSFETs at full load. Because of the
intrinsic asymmetry of the topology the behavior of the two switches is different. When the
load is reduced the low side MOSFET always operates in ZVS while the high side one starts
loosing ZVS. The high side MOSFET never turns on with full bus voltage applied between its
drain and source. As shown in Figure 8, even at 20 % of rated load the Vds at turn-on is
about 100 V, definitely lower compared with the 400 V of a hard switching solution.
This design can therefore meet both efficiency and dynamic requirements.
Figure 6.AHB primary side key waveforms @ full load
Ch1: LVG pin voltage (yellow)
Ch3: HVG pin voltage (purple)
Ch4: Primary winding current (green)
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AN3203Asymmetrical half bridge operation
The signal HVG is the sum of the half bridge node (FGND pin of L6591) and the high side
gate driver voltages. This peculiarity allows both waveforms and the ZVS operation for the
high side MOSFET to be checked. The driver activation is visible on the HVG signal when
there is a small voltage step on the high part of the waveform.
Figure 7.AHB zero voltage switching detail @ full load
Ch1: LVG pin voltage (yellow)
Ch3: HVG pin voltage (purple)
Ch4: Primary winding current (green)
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Asymmetrical half bridge operationAN3203
Figure 8.AHB transitions detail @ 20 % rated load
Ch1: LVG pin voltage (yellow)
Ch3: HVG pin voltage (purple)
Ch4: Primary winding current (green)
The key waveforms at the secondary side are shown in Figure 9. It is interesting to note that,
while the current is swapped between the two SR MOSFETs, the voltage at their drain is
nearly zero. The time required for current swap is directly proportional to the primary
leakage inductance. As mentioned before, the effect of this phenomenon is the duty cycle
losses.
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AN3203Asymmetrical half bridge operation
Figure 9.AHB secondary side key waveforms @ full load
Ch2: Q201 and Q202 drain pin (blue)
Ch3: FGND pin voltage (purple)
Ch4: Diode D13 current (green)
In order to improve the overall efficiency of the power supply, synchronous rectification has
been used. The two AHB output diodes have been replaced with two MOSFETs. A self
driven technique has been used to obtain a cheap solution. Two extra windings at the
secondary side generate the two square waves that, opportunely shifted, drive the two SR
MOSFETs gates directly. Referring to Q201, the extra winding (realized with just one turn)
starts from transformer pin 10 and ends in TON_DR_FLYWIRE. C210, D204, and R216 are
used to shift the voltage at the correct level to drive the MOSFET. R202 helps to keep the
MOSFET off if no driving signal is applied. A similar circuit drives the gate of Q202 starting
from the TOFF_DR_FLYWIRE signal.
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Asymmetrical half bridge operationAN3203
2.2 Short-circuit protection
In case of a short-circuit at the AHB output the overload protection (OLP) is activated.
Figure 10 shows the pins involved in this function. When the short-circuit is applied, the
COMP pin saturates high. The IC detects this condition and starts charging the SS
capacitor. When the SS voltage reaches 5 V the system is shut down, when it reaches 6.4 V
the IC is latched. The PFC controller is also stopped: when the L6591 activates the
protection, the PFC_STOP signal pulls the L6563S RUN pin down to below the 0.8V
threshold. The latch is kept thanks to the auxiliary stage that remains active and provides
the VCC voltage.
In order to restart the system it is necessary to recycle the L6591 VCC voltage between the
UVLO thresholds. This can be done by removing the PS_ON signal in the auxiliary stage.
Figure 10. Short-circuit behavior detail
Ch1: SS pin voltage (yellow)
Ch2: COMP pin voltage (blue)
Ch3: FGND pin voltage, (purple)
Ch4: L6563S RUN pin voltage (green)
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AN3203Complete system
3 Complete system
3.1 Overvoltage protection
Every output is protected against overvoltage. The +12 V, +5 V and +3.3 V are monitored on
the auxiliary power supply schematic page. They use three Zener diodes to fix the three
overvoltage thresholds. In case one of the three voltages exceeds its threshold the latch
realized with Q604 and Q605 is turned on and the VCC for the L6591 and L6563S is
removed.
The two outputs +5 V and +3.3 V also have an overvoltage protection integrated into the
L6727 controller.
The +5 V_SB output is protected using the OVP protection of the VIPer27H that senses its
output voltage through the auxiliary winding. A threshold on the CONT pin detects the OVP
condition and stops the IC operation. This protection has an auto-restart behavior.
3.2 Load transients
The following figures show the behavior of the outputs during load transients. Each image
shows the transition from 20 % to 100 % of rated current and vice versa for a single output
voltage. The current slope is 0.5 A/µs for all the current variations.
Figure 11. Load transient on +12 V output
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Complete systemAN3203
Figure 12. Load transient on +5 V output
Figure 13. Load transient on +3.3 V output
3.3 Standby operation
When the PS_ON is not high, the system is in standby mode. Good performance is obtained
thanks to the VIPer27H high voltage converter. Efficiency and no-load consumption values
are shown in the next chapter.
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AN3203Electrical performance
4 Electrical performance
4.1 Efficiency measurement and no-load consumption
The efficiency measurements taken at the two nominal voltages are seen in the following
tables. The +5 V_SB output was unloaded during these measurements.
Table 1.Efficiency @ 115 Vrms
Load+12 V @load[A]+5 V @load[A]+3.3 V @load[A]Pout [W]Pin [W]Eff [%]
program fixes several efficiency levels that describe how energy-efficient a
computer power supply is. The program defines the minimum efficiency requirements at 20
%, 50 %, 100 % of rated load and a minimum power factor requirement.
According to the program a power supply could be classified in 4 or 5 levels:
Table 3.80 PLUS® program efficiency levels (115Vac)
LevelEff @ 20 %Eff @ 50 %Eff @ 100 %PF (@ load %)
80 PLUS> 80 %> 80 %> 80 %> 0.9 @ 100 %
80 PLUS Bronze> 82 %> 85 %> 82 %> 0.9 @ 50 %
80 PLUS Silver> 85 %> 88 %> 85 %> 0.9 @ 50 %
80 PLUS Gold> 87 %> 90 %> 87 %> 0.9 @ 50 %
80 PLUS Platinum> 90 %> 92 %> 89 %> 0.95 @ 50 %
Note:This table refers to power supplies for desktops, workstations, and non-redundant server
applications with 115 Vac mains
Doc ID 17402 Rev 219/49
Electrical performanceAN3203
®
Table 4.80 PLUS
LevelEff @ 20%Eff @ 50%Eff @ 100%PF (@ load%)
80 PLUS Bronze> 81%> 85%> 81%> 0.9 @ 50%
80 PLUS Silver> 85%> 89%> 85%> 0.9 @ 50%
80 PLUS Gold> 88%> 92%> 88%> 0.9 @ 50%
80 PLUS Platinum> 90%> 94%> 91%> 0.95 @ 50%
program efficiency levels (230 Vac)
Note:This table refers to power supplies for redundant, data center applications with 230Vac
mains
This demonstration board is compliant with the 80 PLUS
please refer to Tab l e 9 ). Since this is basically a desktop PC power supply, the tests were
performed at 115 Vac. Certification report and other details can be found on the 80 PLUS
®
Silver specifications (for PF data
®
web site.
Similar levels of efficiency and power factor are defined also by the Climate Savers
Computing Initiative. According to the measurements carried out, the demonstration board
is compliant with “Climate Savers Computing Silver” level.
Ta bl e 6 shows the no-load consumption. These values are taken with the signal PS_ON
kept low, therefore only the auxiliary stage is active and only the +5 V_SB output is present.
The board showed very good values (below 200 mW over the whole input voltage range),
especially when considering that the inactive stages have a certain residual consumption
(only the voltage dividers in the input stage waste about 100 mW @ 230 Vac).
Table 6.No-load consumption
Vin [Vac]90115135180230264
Pin [mW]597082113161199
Figure 14 and Figure 15 show the graph of the efficiency vs. output power at the two
nominal input voltages while Figure 16 shows the graph of the input power vs. input voltage
with no load applied. It is clearly visible that the power supply is compliant with the 80
®
PLUS
SILVER specification and it is very close to the GOLD one.
20/49Doc ID 17402 Rev 2
AN3203Electrical performance
Figure 14. Efficiency vs. O/P power @ 115 Vac
Figure 15. Efficiency vs. O/P power @ 230 Vac
Figure 16. No-load consumption
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Electrical performanceAN3203
Some measurements with low output loads were also taken. They refer only to the operation
of the auxiliary stage, while the other stages are off. Results are shown in Table 7 and
Ta bl e 8 and plotted in Figure 17. The standby consumption allows the US Executive Order
13221 - “1-Watt Standby” to be met. To be more precise, when the output power is reduced
to 0.5 W, the input power is lower than 1 W (efficiency greater than 50 %). This is a very
common requirement for power supply manufacturers.
Table 7.Low load efficiency @ 115 Vrms
Vout [V]Iout [A]Pout [W]Pin [W]Eff [%]
4.9930.10.4990.68872.6 %
4.9930.20031.0001.31276.2 %
4.9930.30071.5011.93377.7 %
4.9930.39961.9952.54478.4 %
4.9930.52.4973.16378.9 %
4.9930.60022.9973.81278.6 %
4.9930.70063.4984.50177.7 %
4.9930.79943.9915.11478.0 %
4.9930.89984.4935.66479.3 %
4.9931.00014.9936.20980.4 %
Table 8.Low load efficiency @ 230 Vrms
Vout [V]Iout [A]Pout [W]Pin [W]Eff [%]
4.9940.10.4990.82660.5 %
4.9940.20021.0001.47168.0 %
4.9940.30061.5012.1370.5 %
4.9940.39951.9952.79871.3 %
4.9940.49992.4973.48671.6 %
4.9940.60012.9974.16172.0 %
4.9940.70063.4994.80672.8 %
4.9940.79943.9925.30475.3 %
4.9940.89974.4935.93475.7 %
4.99414.9946.66774.9 %
22/49Doc ID 17402 Rev 2
AN3203Electrical performance
Figure 17. Efficiency at low loads
Low load eciency (AUX only)
85.0%
80.0%
75.0%
70.0%
65.0%
60.0%
55.0%
50.0%
0.01.02.03.04.05.0
115Vac
230Vac
Output power [W]
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Electrical performanceAN3203
4.2 Thermal considerations
This demonstration board has been designed for operation with forced air cooling, very
common in ATX power supply applications. As the component temperatures depend on the
type of fan used and on the airflow path inside the board housing, a thermal map of the
board isn’t significant and has not been taken. When the system works at 25 °C with full
load and no forced air, temperatures are not so high. If a heatsink with lower thermal
resistance for MOSFETs Q201 and Q202 is used, fanless operation may be achieved. For
example, the same shape of the heatsink used for D1, Q1, Q2, D3, Q101, and Q102 could
be used for fanless operation. A picture of this application is shown in Figure 18.
Figure 18. Fanless board
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AN3203Electrical performance
4.3 Harmonic content measurement
The front-end PFC stage provides the reduction of the mains harmonic, allowing European
EN61000-3-2 and Japanese JEITA–MITI standards for class D equipment to be met.
Figure 19 shows the harmonic contents of the mains current at full load.
A measurement has also been taken with a 75 W input power which is the lowest limit for
using harmonic reduction techniques.
Figure 19. EN61000-3-2 and JEITA-MITI measurements @ full load
Figure 20. EN61000-3-2 and JEITA-MITI measurements @ 75 W in
To evaluate the performance of the PFC stage the PF and THD vs. input voltage graphs are
also shown, in Figure 21 and Figure 22, at full load and 75 W input power load conditions.
Ta bl e 9 shows the PF values at the three different load amounts defined in the 80 PLUS
and climate savers computing requirements.
®
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Electrical performanceAN3203
Vin [Vrms]
Figure 21. PF vs. input voltage
1.000
0.975
0.950
0.925
0.900
PF
0.875
0.850
0.825
0.800
80
Figure 22. THD vs. input voltage
20.00
18.00
16.00
14.00
12.00
10.00
THD [%]
8.00
6.00
4.00
2.00
0.00
80
250W out 75W in
120
120
160200
250W out 75W in
160
Vin [Vrms]
200
240
280
AM02539v1
240
280
AM02540v1
Table 9.PF vs. load
Load115 Vac230 Vac
20 %0.9720.857
50 %0.9840.954
100 %0.9920.981
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AN3203Electrical performance
4.4 Single output configuration
The power supply overall efficiency is given by the product of the efficiency of each stage. It
is interesting to take a look at the efficiency of the single +12 V output system. Such power
supply can be obtained from the complete system just removing the two daughter boards
that realize the DC-DC post regulation. The single output system can manage the same
power of the multi-output board, hence it is capable of sourcing about 21 A from the +12 V
output.
The system is now made up of input filter, PFC stage, AHB stage and Stand-by stage. The
latter is left unloaded for the following efficiency measurements:
Table 10.Single output efficiency @ 115 Vac
Load [%]Iout [A]Vout [V]Pout [W]Pin [W]Eff [%]
10 %2.08512.0625.14529.7984.41%
20 %4.1712.0650.29056.2789.37%
25 %5.20512.0662.77269.6390.15%
50 %10.42112.05125.573137.491.39%
75 %15.62312.04188.101207.490.69%
100 %20.82912.03250.573279.889.55%
Table 11.Single output efficiency @ 230 Vac
Load [%]Iout [A]Vout [V]Pout [W]Pin [W]Eff [%]
10 %2.08412.0625.13331.0281.02%
20 %4.16912.0650.27856.6588.75%
25 %5.20412.0662.76069.3990.45%
50 %10.42112.05125.573135.392.81%
75 %15.62212.04188.089203.992.25%
100 %20.82712.03250.549274.291.37%
It is interesting to compare the result obtained with the single output configuration with the
80 PLUS
®
levels (see Table 3 and Tab l e 4 ). The comparison is graphically shown in
Figure 23 and Figure 24.
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Electrical performanceAN3203
Figure 23. Single output efficiency @ 115 Vac
Figure 24. Single output efficiency @ 230 Vac
From the pictures it is immediately clear that the single output configuration is over
performing the 80 PLUS
®
GOLD efficiency targets and that it is close to the PLATINUM
ones.
Such performance has been achieved mainly thanks to the AHB stage, which is very
efficient. In Ta bl e 1 2 and Figure 25 efficiency data for the AHB stage only are given. These
measurements were taken by supplying the stage with a 400Vdc input voltage and with the
auxiliary operating without load.
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AN3203Electrical performance
Table 12.AHB efficiency with 400 Vdc input
Load [%]Iout [A]Vout [V]Pout [W]Pin [W]Eff [%]
10 %2.07812.0625.06128.6187.59%
20 %4.16312.0650.20653.7993.34%
25 %5.21312.0662.86966.694.40%
50 %10.41512.05125.501131.395.58%
75 %15.61612.04188.017197.995.01%
100 %20.82312.03250.501266.394.07%
Figure 25. AHB stage only efficiency (Vin = 400 Vdc)
When looking at these efficiency results we have also to keep in mind that the AHB stage is
a cost effective solution, thanks to a low count of components needed, no need of a
controller IC for the synchronous rectification and a small output choke.
Figure 26, 27, 28, and 29 show the conducted noise measurements with peak and average
detection taken at both nominal voltages. All the measurements are performed with full load
output and only consider the worst phase. The average measurements show good margins
with respect to the mask limit (which is the EN55022 CLASS B).
Figure 26. CE peak measurement@115 Vac and full load
Figure 27. CE peak measurement @ 230 Vac and full load
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