ST AN3203 Application note

AN3203

Application note

EVL250W-ATX80PL: 250W ATX SMPS

demonstration board

Introduction

This application note describes the characteristics and performance of a 250 W wide range
input and power factor corrected power supply designed to be used in an ATX application.

Good electrical performance allows meeting the most demanding efficiency targets.

The converter consists of four main blocks:

■ A PFC front-end stage using the L6563S PFC controller which generates the +400 V bus

voltage.

■ An AHB (Asymmetrical half bridge) stage using the L6591 ZVS half bridge controller

which performs the conversion from the high voltage bus to the +12 V output providing
insulation.

■ Two DC-DC post-regulator stages using the L6727 which obtain the +5 V and +3.3 V

outputs from the +12 V bus.

■ An auxiliary power supply (STANDBY) stage using the VIPer27H in isolated flyback

configuration which provides the +5 V_SB output with 10 W power capability.

Figure 1. 250 W ATX SMPS demonstration board

January 2011 Doc ID 17402 Rev 2 1/49

www.st.com

Contents AN3203

Contents

1 Main characteristics and circuit description . . . . . . . . . . . . . . . . . . . . . 5

2 Asymmetrical half bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 AHB typical waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Complete system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Load transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 Standby operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4 Electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1 Efficiency measurement and no-load consumption . . . . . . . . . . . . . . . . . 19

4.2 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.3 Harmonic content measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.4 Single output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Conducted noise measurements (pre-compliance test) . . . . . . . . . . . 30

6 Parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 PFC coil specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

8 AHB transformer specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.2 Mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9 AUX flyback transformer specification . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9.2 Mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

10 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2/49 Doc ID 17402 Rev 2

AN3203 List of tables

List of tables

Table 1. Efficiency @ 115 Vrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 2. Efficiency @ 230 Vrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3. 80 PLUS® program efficiency levels (115Vac). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4. 80 PLUS® program efficiency levels (230 Vac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Climate Savers Computing Initiative (for multi-output PSU) . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. No-load consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Low load efficiency @ 115 Vrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. Low load efficiency @ 230 Vrms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. PF vs. load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 10. Single output efficiency @ 115 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. Single output efficiency @ 230 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12. AHB efficiency with 400 Vdc input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 13. EVL250W-ATX80PL bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14. Winding characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 15. Winding characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 16. Winding characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Doc ID 17402 Rev 2 3/49

List of figures AN3203

List of figures

Figure 1. 250 W ATX SMPS demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2. Electrical diagram: input EMI filter and PFC stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Electrical diagram: AHB stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Electrical diagram: DC-DC stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Electrical diagram: standby stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. AHB primary side key waveforms @ full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7. AHB zero voltage switching detail @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. AHB transitions detail @ 20 % rated load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. AHB secondary side key waveforms @ full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Short-circuit behavior detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. Load transient on +12 V output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12. Load transient on +5 V output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Load transient on +3.3 V output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14. Efficiency vs. O/P power @ 115 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15. Efficiency vs. O/P power @ 230 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 16. No-load consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 17. Efficiency at low loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 18. Fanless board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 19. EN61000-3-2 and JEITA-MITI measurements @ full load . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 20. EN61000-3-2 and JEITA-MITI measurements @ 75 W in . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 21. PF vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 22. THD vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 23. Single output efficiency @ 115 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 24. Single output efficiency @ 230 Vac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 25. AHB stage only efficiency (Vin = 400 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 26. CE peak measurement@115 Vac and full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 27. CE peak measurement @ 230 Vac and full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 28. CE average measurement@115 Vac and full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 29. CE average measurement@230 Vac and full load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 30. Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 31. Mechanical drawing (unit: mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 32. Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 33. Windings position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 34. Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 35. Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 36. Windings position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 37. Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 38. Top side silk screen and copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 39. Bottom side silk screen and copper (mirror view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4/49 Doc ID 17402 Rev 2

AN3203 Main characteristics and circuit description

1 Main characteristics and circuit description

Here are the main characteristics of the power supply:

● Input mains range:

– Vin: 88 ~ 264 Vrms

– f: 45 ~ 66 Hz

● Outputs:

– +12 Vdc ± 2 % - 13.5 A

– +5 Vdc ± 2 % - 12 A

– +3.3 Vdc ± 2 % - 8 A

– +5 V_SB ± 2 % - 2 A

● Standby consumption: < 0.2 W

● Protection:

– Short-circuit

–Overload

– Output overvoltage

– Brownout

● PCB type and size:

–FR4

– Double side CU 70 µm

– 148 x 120 mm

● Safety: according to EN60950

● EMI: according to EN55022 - class B

The EVL250W-ATX80PL demonstration board is made up of four main blocks, the
schematics are shown in Figure 2, 3, 4, and 5.

The front-end PFC stage is realized using a boost topology working in line modulated fixed
off time (LM-FOT) mode, described in STMicroelectronics’ application notes, AN1792;

Design of Fixed-Off-Time controlled PFC pre-regulators with the L6562 and AN3142;
Solution for designing a 400 W Fixed-Off-Time controlled PFC preregulator with the L6563S
and L6563H. The LM-FOT operation offers the advantage of having CCM operation (with

lower rms current with respect to TM mode) without the need to use a complex and
expensive controller. Therefore, it is possible to use the simple L6563S, enhanced TM PFC
controller, which integrates all the functions and protection, needed to control the stage, and
an interface with the downstream DC-DC converter.

The power stage of the PFC is realized with inductor L4, MOSFET Q1 and Q2, diode D3,
and capacitor C1. The LM-FOT operation is obtained with components D6, R15, C10, R14,
C9, R13, and Q3.

The PFC delivers a stable high voltage bus (+400 V nominal) to the downstream converters
(AHB and flyback) and provides for the reduction of the current harmonics drawn from the
mains, in order to meet the requirements of the European EN61000-3-2 norm and the
Japanese JEITA-MITI norm.

The second stage is an asymmetrical half bridge converter, driven by the L6591, a
STMicroelectronics controller dedicated to this topology. This IC integrates all the functions

Doc ID 17402 Rev 2 5/49

Main characteristics and circuit description AN3203

and protection needed by the AHB stage and an interface for the PFC controller. The L6591
includes two gate drivers for the half bridge MOSFETs and a fixed frequency
complementary PWM logic with 50 % maximum duty cycle with programmable dead time
and current mode control technique.

Other features of this IC are pulse-by-pulse overcurrent protection, transformer saturation
detection, overload protection (latched or auto-restart), and programmable soft-start. There
is also a high voltage startup circuit, a burst mode logic for low load operation, and the
adaptive UVLO onboard, which are not used in this design as they are designed for adapter
applications (see AN2852).

The following is a description of the power circuit of this stage. The half bridge switches
Q101 and Q102 are connected to the output voltage of the PFC. The half bridge node drives
the series of C101 (DC blocking capacitor) and the primary side of the transformer T1. This
transformer has two secondary windings with a center tap connected to the secondary
ground. The other ends are connected to the sources of MOSFETs Q201 and Q202, which
replace output diodes in order to perform the synchronous rectification. Two extra windings
allow, with few external passive components, a self driven synchronous rectification to be
obtained. This solution allows efficiency to be increased without the extra cost of a
dedicated SR controller IC.

Q201 and Q202 drains are connected to the output inductor L201 that, together with output
capacitors C201 and C202, acts as a low pass filter. The signal +12 VA is then post filtered
(with L5 and C207) to obtain the +12 V output voltage.

The design of transformer T1 is a trade-off between ZVS operation and the required
electrical performance/efficiency. ZVS can be obtained acting on the magnetizing
inductance or on the primary side leakage inductance. In more detail, ZVS could be met by:

● Decreasing the magnetizing inductance

● Increasing the leakage inductance

Low values of magnetizing inductance generate high magnetizing current. This helps to
reach ZVS but it also increases the total primary side rms current and therefore the related
losses. In this design a value of 500 µH has been selected.

On the other hand, ZVS could be obtained by increasing the leakage inductance. If such a
parameter is increased, the primary side current takes more time before reversing its
direction and therefore ZVS is more easily met. A high leakage inductance value leads to
duty cycle losses, reducing the effective range of duty cycle usable. This creates problems
with hold-up requirements and makes it necessary to work with very narrow duty cycles with
nominal input voltage generating high rms currents in the circuit.

A value of 12 µH has been selected as the leakage inductance.

Because of these reasons, in this design ZVS is always met at low side MOSFET turn-on
while it is met only for medium-high loads at high side MOSFET turn-on. Even at medium­low loads Q101 is turned on with a Vds well below the half bridge input voltage.

The L6591 LINE pin is used for startup sequencing. It shares with the L6563S the voltage
divider made up of R20, R21, R22, R29, and R26 that senses the PFC output voltage. The
AHB stage is activated when the bulk voltage reaches about 380 V.

The DISABLE pin (latched protection) is driven by the L6563S PWM_LATCH pin and stops
the AHB stage in case of PFC feedback disconnection.

The oscillator is programmed in order to have a switching frequency of about 80 KHz and to
use the minimum dead time (about 310 ns).

6/49 Doc ID 17402 Rev 2

AN3203 Main characteristics and circuit description

The PFC_STOP pin is the interface for the PFC controller, it is connected to the L6563S
RUN pin through R104 and it stops the PFC operation (not latched) in case of overload,
output short-circuit or transformer saturation detection.

The +5 V and +3.3 V are obtained from the +12 VA bus (AHB output) thanks to two DC-DC
converters mounted on two daughter boards. These stages are driven by the L6727, single
phase PWM controller. The topology is a standard step down. For more information please
refer to the L6727; Single phase PWM controller datasheet.

The last stage is the auxiliary power supply that provides the +5 V_SB output (2A capability)
and the VCC supply for the L6563S and L6591. It is realized with a standard flyback
topology operating in CCM/DCM with fixed frequency using the VIPer27H. This stage takes
the PFC output voltage as input and is always working when the mains is plugged in. The
VIPer27H has all the protection needed to safely drive the standby stage. It protects the
circuitry in case of overload, output short-circuit, or output overvoltage.

All the other stages (and therefore the outputs +12 V, +5 V and +3.3 V) can be turned on /
off using the signal PS_ON. If it is disconnected or connected to GND, the OPTO2 current is
zero, Q601 is open and the VCC of the L6563S and L6591 is zero. If PS_ON is connected to
+5 V_SB, the OPTO2 current turns Q601 on. This BJT, together with the Zener diode
ZD601, acts as a linear regulator and provides the supply to the PFC and AHB controllers.

The same optocoupler is used to turn off the PFC and AHB stages in case of an overvoltage
on one of the three main outputs. Such protection is realized with three Zener diodes (one
for each output) that set the OVP thresholds. If one of the three output voltages goes over its
threshold, the Zener diode conducts and turns on the latch realized with Q604 and Q605.
The current in OPTO2 is reduced to zero (overriding the PS_ON information) and the
L6563S and L6591 are turned off.

Only the +5 V_SB stays on and continues to keep the protection latched.

Doc ID 17402 Rev 2 7/49

Main characteristics and circuit description AN3203

Figure 2. Electrical diagram: input EMI filter and PFC stage

8/49 Doc ID 17402 Rev 2

AN3203 Main characteristics and circuit description

Figure 3. Electrical diagram: AHB stage

!-V

Doc ID 17402 Rev 2 9/49

Main characteristics and circuit description AN3203

Figure 4. Electrical diagram: DC-DC stage

10/49 Doc ID 17402 Rev 2

!-V

AN3203 Main characteristics and circuit description

Figure 5. Electrical diagram: standby stage

!-V

Doc ID 17402 Rev 2 11/49

Asymmetrical half bridge operation AN3203

2 Asymmetrical half bridge operation

2.1 AHB typical waveforms

In Figure 6 the primary side key waveforms during steady-state operation with full load
applied are shown. Figure 7 shows the detail of the two transitions during one switching
cycle.

The AHB stage has been designed to operate at about 80 kHz with a nominal input voltage
of 400 V (PFC output bus). The transformer design is the result of a trade-off between the
half bridge MOSFETs zero voltage switching (ZVS) operation requirements, the primary rms
current, and duty cycle losses. In fact, ZVS can be achieved by reducing the magnetizing
inductance or increasing the leakage inductance. With the output power of this board, the
first solution implies having very high rms primary current which leads to high losses. The
second solution introduces the so called “duty cycle losses”. When the leakage inductance
is de-magnetizing, the voltages on the secondary side windings are zero and therefore the
output mean value is reduced with respect to the same half bridge duty cycle and negligible
leakage inductance. Duty cycle losses limit the hold-up capability of the power supply
because they increase the minimum input voltage that guarantees output regulation.

In this design the system works with ZVS for both MOSFETs at full load. Because of the
intrinsic asymmetry of the topology the behavior of the two switches is different. When the
load is reduced the low side MOSFET always operates in ZVS while the high side one starts
loosing ZVS. The high side MOSFET never turns on with full bus voltage applied between its
drain and source. As shown in Figure 8, even at 20 % of rated load the Vds at turn-on is
about 100 V, definitely lower compared with the 400 V of a hard switching solution.

This design can therefore meet both efficiency and dynamic requirements.

Figure 6. AHB primary side key waveforms @ full load

Ch1: LVG pin voltage (yellow)

Ch3: HVG pin voltage (purple)

Ch4: Primary winding current (green)

12/49 Doc ID 17402 Rev 2

AN3203 Asymmetrical half bridge operation

The signal HVG is the sum of the half bridge node (FGND pin of L6591) and the high side
gate driver voltages. This peculiarity allows both waveforms and the ZVS operation for the
high side MOSFET to be checked. The driver activation is visible on the HVG signal when
there is a small voltage step on the high part of the waveform.

Figure 7. AHB zero voltage switching detail @ full load

Ch1: LVG pin voltage (yellow)

Ch3: HVG pin voltage (purple)

Ch4: Primary winding current (green)

Doc ID 17402 Rev 2 13/49

Asymmetrical half bridge operation AN3203

Figure 8. AHB transitions detail @ 20 % rated load

Ch1: LVG pin voltage (yellow)

Ch3: HVG pin voltage (purple)

Ch4: Primary winding current (green)

The key waveforms at the secondary side are shown in Figure 9. It is interesting to note that,
while the current is swapped between the two SR MOSFETs, the voltage at their drain is
nearly zero. The time required for current swap is directly proportional to the primary
leakage inductance. As mentioned before, the effect of this phenomenon is the duty cycle
losses.

14/49 Doc ID 17402 Rev 2

AN3203 Asymmetrical half bridge operation

Figure 9. AHB secondary side key waveforms @ full load

Ch2: Q201 and Q202 drain pin (blue)

Ch3: FGND pin voltage (purple)

Ch4: Diode D13 current (green)

In order to improve the overall efficiency of the power supply, synchronous rectification has
been used. The two AHB output diodes have been replaced with two MOSFETs. A self
driven technique has been used to obtain a cheap solution. Two extra windings at the
secondary side generate the two square waves that, opportunely shifted, drive the two SR
MOSFETs gates directly. Referring to Q201, the extra winding (realized with just one turn)
starts from transformer pin 10 and ends in TON_DR_FLYWIRE. C210, D204, and R216 are
used to shift the voltage at the correct level to drive the MOSFET. R202 helps to keep the
MOSFET off if no driving signal is applied. A similar circuit drives the gate of Q202 starting
from the TOFF_DR_FLYWIRE signal.

Doc ID 17402 Rev 2 15/49