ST AN3202 APPLICATION NOTE

AN3202

Application note

How to configure the SPEAr600 general purpose timers (GPTs)

Introduction

This application note provides information about how to configure the general purpose timers (GPTs) integrated in the SPEAr600 embedded MPU family.

General purpose timers (GPTs) play an important role in any system as they provide a means of calculating time for controlling the execution of various operations. In case of an operating system, they are used for the system tick generation, usually every 10 ms; in other applications they can be used to get a finer granularity for controlling the timing of events.

The purpose of this application note is to explain how to read the free running timer counter and configure the clock source of the various GPTs that are integrated in the SPEAr600 architecture.

May 2010

Doc ID 17399 Rev 1

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Contents	AN3202

Contents

1	General purpose timers (GPTs) in SPEAr600 . . . . . . . . . . . . . . . . . . . .	. 3
2	Reading a free-running timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . .	5
3	Scenario with slow CNT_Clk and fast READ_Clk . . . . . . . . . . . . . . . . .	7
4	How to configure CNT_Clk and READ_Clk to be synchronous . . . . . .	8
5	Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
6	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	10

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AN3202	General purpose timers (GPTs) in SPEAr600

1 General purpose timers (GPTs) in SPEAr600

In the SPEAr600 architecture, there are five different GPT blocks located in the various subsystems. Each timer block consists of two independent channels, each one with a 16-bit counter register.

Table 1.	GPTs in SPEAr600
			Subsystem	Base address
	GPT1		ARM1	0xF000_0000
	GPT2		ARM2	0xF000_0000
	GPT3		Basic	0xFC80_0000
	GPT4		Application 1	0xD800_0000
	GPT5		Application 2	0xD808_0000

Each timer has a READ_Clk, input which is the APB clock (PCLK), and a CNT_Clk, which can be selected by the user from a list of clock sources.

●READ_Clk (PCLK): When SPEAr600 is in normal mode, it takes the input from PLL1 divided by a programmable prescaler, whose reset values impose the ratio 1:2:4 to the core_clk, HCLK and PCLK clocks. When SPEAr600 is in slow mode, it takes directly the input from the OSCI signal.

●CNT_Clk: The clock source can be selected as either a fixed 48 MHz or the PLL1 itself divided by a programmable prescaler, which is defined in the PRSC1_CLK_CFG register (0xFCA8_0044) for GPT1/GPT2/GPT3, PRSC2_CLK_CFG register (0xFCA8_0048) for GPT4 and PRSC3_CLK_CFG register (0xFCA8_004C) for GPT5. The CNT_Clk may then be further divided by a GPT internal 4-bit prescaler able to divide up to 256 times (‘/256’).

Figure 1. GPT clock sources

		HCLK/PCLK
	PLL1 (332MHz)/	prescaler	Read_CLK
	OSCI (24MHz)		(PCLK)
			GPT Ch1	GPT Ch2
PLL1 (332MHz)	PRSCx_CLK_CFG
		MUX
			int_prsc
			CNT_Clk
	PLL3 (48MHz)
		Clock_Sel

The following table describes the clock selectors (Clock_Sel) for each GPT.

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General purpose timers (GPTs) in SPEAr600						AN3202
	Table 2.	GPTx clock source selector
			Register	Address		Value
		GPT1	PRPH_CLK_CFG [08]	0xFCA8_0028 (bit8)		0: PLL3 48 MHz
						1: PLL1 (PRSC1_CLK_CFG)
		GPT2	PRPH_CLK_CFG[09]	0xFCA8_0028	(bit9)	0: PLL3 48 MHz
						1: PLL1 (PRSC1_CLK_CFG)
		GPT3	PRPH_CLK_CFG[10]	0xFCA8_0028	(bit10)	0: PLL3 48 MHz
						1: PLL1 (PRSC1_CLK_CFG)
		GPT4	PRPH_CLK_CFG[11]	0xFCA8_0028	(bit11)	0: PLL3 48 MHz
						1: PLL1 (PRSC2_CLK_CFG)
		GPT5	PRPH_CLK_CFG[12]	0xFCA8_0028	(bit12)	0: PLL3 48 MHz
						1: PLL1 (PRSC3_CLK_CFG)

The SPEAr600 GPTs always generate precise alarm interrupts, for example in the case of a system tick for a RTOS. Nevertheless, as you can see in Section 2: Reading a free-running timer counter, GPTs can return unpredictable read values when they are running and the input clock is asynchronous (or not in phase).

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