ST AN3171 APPLICATION NOTE

AN3171

Application note

Comparing the M24C64-R, M24C64-F and M24C64-W devices to the M24LR64-R dual interface EEPROM

Introduction

The purpose of this application note is to explain the differences between the M24LR64-R dual interface EEPROM when controlled from the I²C bus, and the standard M24C64-F, M24C64-R, M24C64-W EEPROMs.

For simplification purposes, the M24C64-F, M24C64-R, M24C64-W will be referred to as M24C64 in the rest of the document.

For additional information, please refer to the M24LR64-R and M24C64 datasheets.

March 2010

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Contents	AN3171

Contents

1	Hardware considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			5
	1.1	Pinout comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		5
	1.2	Two ways of accessing the M24LR64-R: RF and I²C . . . . . . . . . . . . . . . . .		6
2	Software considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			7
3	M24LR64-R memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			8
	3.1	User memory seen from the I²C bus (E2=0) . . . . . . . . . . . . . . . . . . . . . . .		8
		3.1.1	Sectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
		3.1.2	Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	8
		3.1.3	Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
		3.1.4	I²C Present Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
		3.1.5	I²C Write Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9

3.2 System memory seen from the I²C bus (E2=1) . . . . . . . . . . . . . . . . . . . . 10

3.2.1 M24LR64-R’s RF block security status . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2.2 I²C_Write_Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.3 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13

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AN3171	List of tables

List of tables

Table 1. M24LR64-R device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. M24C64 device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. RF block security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. I2C_Write_Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5. System parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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List of figures	AN3171

List of figures

Figure 1. M24LR64-R and M24C64 logic diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. M24LR64-R and M24C64 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. M24LR64-R block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. M24LR64-R’s user and system memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5. I2C Present Password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. I2C Write Password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

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AN3171	Hardware considerations

1 Hardware considerations

1.1Pinout comparison

Figure 1 and Figure 2 show the logic diagrams and the pinouts of the M24LR64-R and M24C64 devices, respectively.

Figure 1. M24LR64-R and M24C64 logic diagrams

6##

6##

	% %	3$!
		!#
	3#,	- ,2 2
		!#

% %	3$!
3#,	- #
7#

633

633

!)

M24LR64-R AC0/AC1 pins: due to its RF capability, the M24LR64-R dual interface EEPROM features two inputs (AC0 and AC1) to connect the RF antenna.

Consequently, two inputs present in the M24C64 are not offered in the M24LR64-R: these are E2 and Write Control (WC).

Practically, this means that you will be able to use up to four M24LR64-R devices (defined by E0, E1) on the same I²C bus, compared to eight devices (defined by E0, E1, E2) for the M24C64.

The Write Control input (WC) is used to write-protect the M24C64. The M24LR64-R can also be protected but in a different way, using the I2C_Write_Lock bits.

Figure 2. M24LR64-R and M24C64 pinouts

	%						6##				%								6##
!#							%			%										7#
!#									3#,	%									3#,
633								3$!		633						3$!
					-,2 2											-#					AI

Figure 2 shows that the four mandatory pins for the I²C bus (VSS, VCC, SCL, SDA) are positioned likewise in the two devices.

AC0 and AC1 are connected to pin 2 and pin 3, respectively. They have to be next to each other for RF capability requirements. As a result, E1 was moved to pin 7 in the M24LR64-R, whereas it is connected to pin 2 in the M24C64.

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