ST AN3169 APPLICATION NOTE

AN3169

Application note

Technology performance comparison of Triacs

subjected to fast transient voltages

Introduction

This paper presents an experimental comparison of several Triac devices under immunity tests, as described in the IEC 61000-4-4 standard. After a short reminder of the different Triac technologies available today (Top, mesa and planar technologies), the IEC 61000-4-4 test procedure to compare the devices is explained. The immunity results are discussed according to the device technology and the gate current sensitivities. A discussion about relevance of dV/dt parameter and die area is carried on to differentiate the devices in term of immunity capability.

Home appliances such as washing machines, refrigerators and dishwashers integrate a lot of low power loads such as valves, door lock systems, dispensers and drain pumps. These loads are usually powered by the mains in on / off mode, and are mostly controlled by Triacs.

The direct connection of the silicon switch to the mains, through the load, requires that these devices must withstand line transients to make the system compliant with the international electromagnetic compatibility (EMC) standards. The silicon devices are then subjected to fast transient voltages, as described in the IEC/EN 61000-4-4 standard.

The immunity of several Triac technologies is evaluated here experimentally. Several guidelines can then be pointed out to design high immunity appliances.

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Triac technologies and immunity AN3169

1 Triac technologies and immunity

1.1 Triac silicon structures

Triac devices are by far the most used silicon devices to drive AC loads directly connected on the mains voltage. Triacs are widely used because they present three major advantages:

● Low forward voltage drop

● Turn on by gate current pulse

● High voltage immunity

The first two advantages come from the active silicon structure of the Triac which is based on four alternatively doped silicon layers (N-P-N-P). These four layers implement two bipolar transistors which are coupled to maintain the on state even if the gate current is removed (see Figure 1).

Figure 1. Active simplified structure of a Triac

A1 G

The third advantage comes from the fact that the voltage is withstood by the silicon thickness. It's then quite easy to reach breakdown levels above 1 kV. The main issue is then the junction termination. Several low cost technologies are used since the 70’s which used a glass passivation. For example the “Mesa” technology (see Figure 2) uses glass on both sides of the die (see References 1, 2, and 3) to passivate both junctions, which hold both forward and reverse high voltages (referred to as “Cathode” or “A1” or “COM” polarity). The “Top” glass technology (see References 1, 2, and 3) uses only one glass layer (see

Figure 3). This avoids having some glass at the bottom of the die, and so it is easier to put

such dies in every kind of package.

Figure 2. “Mesa” glass technology

Glass

Cathode

Gate

Metalization

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Anode

AN3169 Triac technologies and immunity

Figure 3. “Top” glass technology

Cathode

Glass

Gate

Anode

Metalization

Both top and mesa glass technologies are very cost effective. The insulation capability of glass is very high. This helps to achieve high voltage devices with a limited periphery area. Mesa glass technology is the cheaper one as this technology uses less silicon area to withstand reverse voltage. For top technology, the reverse PN junction is terminated on the upper side of the die thanks to the deep P well. Such dies are bigger for the same active area than mesa dies. This is the reason why top technology is mainly used for low current Triacs.

Unfortunately it is not possible to ensure a good operation of a die with glass passivation when the voltage exceeds its maximum allowed value (V

DRM

or V

parameters). If the

RRM

voltage reaches the breakdown value, a current will flow through the die periphery, causing heat dissipation at the glass-silicon interface. This heat could cause mechanical stress and damage this interface. The device could then be damaged.

To develop switches able to work up to their breakdown voltage, a planar technology has to be implemented. Such a technology uses photolithography to terminate the PN junction at the top of the die, and oxide passivation instead of glass (see Figure 4). There is no more glass-silicon interface issue. ACST devices use this kind of technology (see Reference 4).

Figure 4. Planar technology

Passivation

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Oxyde

Anode

N N

Cathode

Metalization

Gate

Triac technologies and immunity AN3169

1.2 Sensitivity and dV/dt immunity

This experimental comparison on immunity level has been performed on different devices which target the same application. This application is the control of valves or pumps in white goods. The load current is usually less than 1 A. Anyway, appliances designers use, to control these loads, 1 A, 2 A and even 4 A Triacs. The use of a high current rating device is usually motivated by desire for highly immune and robust systems.

To rationally compare the different devices, we have selected devices with the same voltage and sensitivity ratings. The voltage rating is given by the V in this application note). The sensitivity is given for Triacs by the I minimum gate current that should be applied to turn on the device. The devices we have chosen all have a 10 mA maximum I

The Triac sensitivity can not be reduced too much. An appliance designer has to work with the sensitivity (supply consumption) and immunity compromise. If the I device will not be able to withstand excessive dV/dt rates across its power terminals (A1 and A2 for Triacs, or OUT and COM for ACST). Triac manufacturers then give a dV/dt parameter which is measured at the maximum junction temperature. Results of Ta b le 1 are given for dV/dt tests performed at a 125 °C junction temperature and a 400 V applied voltage. It should be noted that some values are lower than values given in constructors datasheet for the devices which are specified at 110 °C instead of 125 °C. This is a normal result as the dV/dt immunity decreases with the temperature.

DRM

and V

parameters (800 V

RRM

parameter which is the

is too low, the

Ta bl e 1 gives the I

and dV/dt parameters that we measured for the different samples we

used during IEC 61000-4-4 tests, and for the different bias polarities.

The products tested are:

● the Z0409N: a top glass 4 A Triac

● the T410-800: a mesa glass 4 A Triac

● the ACST2: a planar 2 A Triac

● the COMP.1A: a planar 1 A Triac

● the COMP.2A: a planar 2 A Triac

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