ST AN3157 APPLICATION NOTE

AN3157

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TPMS1

Application note

STEVAL-IPE010V1 poly-phase demonstration kit

for the STPMC1 and STPMS1

Introduction

This application note describes the STEVAL-IPE010V1 poly-phase demonstration kit for the STPMC1 and STPMS1.The STPMC1 is a metering ASSP implemented through an advanced 0.35 µm BCD6 technology.

The STPMC1 device functions as an energy calculator in power line systems, using the Rogowski current transformer and shunt or Hall current sensors. It is used in combination with one or more STPMS1 devices. It implements all the functions needed in a 1, 2 or 3phase energy meter, providing the effective measurement of active and reactive energies, V

, I

RMS

services, from 2 to 4 wires.

In a stand-alone configuration the STPMC1, which sends a pulse train signal with a frequency proportional to the cumulative active power, can directly drive a stepper motor, therefore implementing a simple active energy meter.

This device can also be coupled to a microprocessor for multi-function energy meters. In this case, the measured data is read at a fixed time interval from the device internal registers by the microcontroller through the SPI interface.

, instantaneous voltage and current-per-phase in 1, 2 or 3-phase wye and delta

RMS

The STPMS1 is an ASSP designed as a building block for single or multi-phase energy meters. It consists of a pre-amplifier and two 1st order ΔΣ modulators, band-gap voltage reference, a low-drop voltage regulator and DC buffers in its analog section, and a clock generator and output multiplexer in its digital section.

The demonstration kit is made up of a main board with the STPMC1 mounted, and it can be coupled with up to 5 daughterboards, each with an STPMS1 mounted to sense the voltage and current of each phase.

Note: The demonstration kit is available on request.

Figure 1. Demonstration kit block diagram

N R S T

Current

Sensor

Vol t age

Sensor

Current

Sensor

rent nsor

tage

nsor

tage nsor

STPMS1

e

STPMS1

DARDAR

SCS

LED

MOPMONVOTP

VCC

DAR

DAS

DAT

DATDATDANDAN

DAHDAH DASDAS

DAT

DAN

DAH

MOPMONVOTP

STPMC1

CLK XTAL1 XTAL2

SYN- NP

SCL-NC

SDA- TD

VSS VSSA

P1P1

VDD

April 2010 Doc ID 17105 Rev 1 1/26

www.st.com

Contents AN3157

Contents

1 Application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Motherboard circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Daughterboard circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.1 Current sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.2 Anti-aliasing filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.3 Voltage sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.4 Crosstalk cancellation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.5 Jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Clock management network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Communication with microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Layout rules for the 3-phase system design . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Motherboard layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.3 Daughterboard layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 3-phase energy measurement accuracy . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1 Test with symmetrical voltages and balanced load at PF = 1 . . . . . . . . . 12

4.2 Typical phase energy measurement accuracy . . . . . . . . . . . . . . . . . . . . . 13

4.2.1 Test with only one phase load at PF = 1 . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3 Test with only one phase load at PF = 0.5 inductive and 0.8 capacitive . . 14

Appendix A 3-phase systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

A.1 Power in 3-phase AC circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

A.2 Power measurement techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

A.2.1 Two-wattmeter method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

A.2.2 Three-wattmeter method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

A.2.3 One wattmeter method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2/26 Doc ID 17105 Rev 1

AN3157 Contents

Appendix B BOM list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Doc ID 17105 Rev 1 3/26

Application description AN3157

1 Application description

The purpose of this STEVAL-IPE010V1 demonstration kit is to provide an evaluation platform for the STPMC1 and STPMS1 devices, but it can also be used as a starting point to design a Class 1 meter for 2 to 4-wire power line systems using delta or wye service.

Each phase is monitored by an independent daughterboard, in which an autonomous power supply is provided to the board itself and, once it is connected, also to the motherboard.

In this board, the STPMS1 device senses the phase current through a CT or a shunt sensor, and the phase voltage through a voltage divider. The presence of dedicated networks reduces greatly the sampling (aliasing) noise and the crosstalk noise between voltage and current channels, increasing meter precision. The STPMS1 produces a sigma-delta stream, sent together with the supply voltage, to the STPMC1 through a card edge connector.

The motherboard receives the sigma-delta streams from the daughterboards which are further elaborated by the STPMC1. This device, from a 4.194 MHz crystal oscillator, provides a common clock with programmable frequency to all the daughterboards.

The motherboard, through a 10-pin flat cable connector (P1 in Figure 2) can be interfaced to a microprocessor board to implement advanced metering features (multi-tariff, data management and storage, communication, etc). It also has stepper motor connectors for a simple energy meter implementation (W2, W5 in Figure 2).

The STPMC1 board can also be connected to a dedicated GUI (graphical user interface) through the STPMxx parallel programmer/reader released with the application.

1.1 Operating conditions

Table 1. Operating conditions

Condition Value Unit

V

NOM

I

NOM

I

MAX

f

LIN

T

OP

230 V

NOM

MAX

= 1 = 5

= 30 = 80

CT: I Sh: I

A

RMS

50 / 60 ± 10% Hz

- 40 / + 85 °C

4/26 Doc ID 17105 Rev 1

AN3157 Circuit description

2 Circuit description

2.1 Motherboard circuit

The motherboard consists of the following sections:

● STPMC1 circuit

● Connectors

The schematic of the board is shown in Figure 2 and in Figure 3.

Figure 2. STPMC1 circuit schematics

VCC VCC VCC

D12

D10

R 62

4.7K

D11

R 63

4.7K

P1

2

4

6

8

1

3

5

7

910

4.7K

C64

10n

R 60

4.7K

D9

R 61

4.7K

U8

20

W8

20

19

18

17

16

15

14

13

12

GND

LED

SDATD

SCLNLC

CLKOUT

CLKIN

SYN

VSSA

CLK

DAN

STPMC1

VCC

D8

C66

+

1000u

MON

MOP

SCS

VDD

VCC

VOTP

DAH

DAR

DASDAT

TP2

R64

CLK

DAN

DAT

CLK

DAN

W34

R56100

R55100

1

2

1M1%

Y1

4194.304KHz

C61

C62

C61

C62

15p

VCC

C65

100n

VSS

W2 MON

1

2

W5 MOP

3

4

5

6

VCC

7

8

R16

9

R15

1011

R35

CLK NCLK

7 14

DAH

100

DAR

DASDAT

100

U9A

1 2

ST_m74hc14

U9G

GND VCC

ST_m74hc14

D7

C63

C63 1µ

1µ

DAH

DAR

DAS

VCC

Doc ID 17105 Rev 1 5/26

Circuit description AN3157

Figure 3. Motherboard connector schematics

J1

S1

VCC

S2

NCLK

S3

NCLK

S3

S4

CLK

S5

S6

S7

DAR DAS DAT

S8

S9

S10

VCC

Card_Edge_10

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

VCC VCC

NCLK

CLK

VCC VCC

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

Card_Edge_10

J2

F1

F2

NCLK

F3

NCLK

F3

F4

CLK

F5

F6

F7

F8

F9

F10

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

Card_Edge_10

J3

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

VCC VCC

NCLK

CLK

DAN DAH

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

Card_Edge_10

J4

F1

F2

F3

NCLK

F4

CLK

F5

F6

F7

F8

F9

F10

VCCVCC

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

Card_Edge_10

J5

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

2.2 Daughterboard circuit

This section describes the implementation of each phase network which performs the power measurement.

The schematic can be divided into the following subsets:

● Current sensing circuit (1) or (2)

● Anti-aliasing filter (3)

● Voltage sensing circuit (4)

● Crosstalk cancellation network (5)

2.2.1 Current sensing circuit

The STPMS1 has an external current sensing circuit using either a current transformer, in which a burden resistor is used to produce a voltage between CIN and CIP proportional to the current measured, or a shunt resistor.

2.2.2 Anti-aliasing filter

The anti-aliasing filter is a low-pass filter which has a negligible influence on the voltage drop between CIN and CIP, and VIN and VIP. The aim of which is to reduce the distortion caused by the sampling (also called aliasing) by removing the out-of-band frequencies of the input signal before sampling it with the analog-to-digital converter. Filtering is easily implemented with a resistor-capacitor (RC) single-pole circuit which obtains an attenuation of - 20 dB/dec.

2.2.3 Voltage sensing circuit

A resistor divider is used as a voltage sensor. The 600 kΩ resistor is separated into four, 4 x 150 kΩ, in-series resistors, which ensure that a high voltage transient does not bypass the resistor. This also reduces the potential across the resistors, thereby decreasing the possibility of arcing. The following resistors are used to implement the resistor divider:

● R = R13 + R2 + R3 + R4 = 600 kΩ

● R5 = 475 Ω

The L1 inductor and the C2 capacitor create a filter which prevents electromagnetic interference (EMI).

6/26 Doc ID 17105 Rev 1

AN3157 Circuit description

Figure 4. Daughterboard circuit schematic

VCC

NCLK

CLK

VCC

DAR

VCC

R18

0

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

Card_Edge_10

1

F

J1

SH1

SH1 170u

170u

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

E4622_X503

V1 460V

VCC

DAR

R14

DAR

10

C6

1u

R16

R16 0

C13 100n

19

20

19

VREG

C5

1u

C12 100n

3

R6

3.4 1%

3

R7 1K 1%

R8 1K 1%

R2 150k

R1 82

D1

R3 150k

2

4

3

TR1

3

2

1

R13 150k

12

R13 150k

L1

220u

C1 470n

C2 1n

20

18

e3

e2

17

e1

1

vdd_reg

2

gnd_reg

3

vdd_ac

4

gnd_ac

C7

C7 5n

5n

C8

C8 5n

5n

R4 150k

N

D2

0

15

16

e4

dat

vcc

stpms1

cip

cin

cip

cin

5

6

5

6

4

R5

R5 475 1%

475 1%

U1

R15

R15 0

0

14

datn

vip

7

C3 22n

CLK

13

vdd_d

vdd_av

8

clk

vin

ms1

ms0

12

11

10

9

R9

42.2k 1%

R11

R11 100 1%

100 1%

C14

1u

R10

2.2M 1%

JP1

CLK

45

CLK

45

3

6

3

6

NCLK

2

7

2

7

1

8

1

8

JP2

45

CLK

3

6

3

6

2

7

2

7

8

5

GND

C11

1u

VCC

R17

R17 10

10

NCLK

1

VCC

2.2.4 Crosstalk cancellation network

The voltage front-end handles voltages of considerable amplitude, which makes it a potential source of noise. Disturbances are readily emitted into current measurement circuitry where they interfere with the actual signal to be measured. Typically, this produces a non-linear error at small signal amplitudes and non-unity power factors. At unity power factors, voltage and current signals are in phase and crosstalk between voltage and current channels merely appears as a gain error, which can be calibrated. When voltage and current are not in phase, crosstalk has a non-linear effect on the measurements, which cannot be calibrated.

Crosstalk is minimized through good PCB planning and the proper use of filter components in the crosstalk network. Recommended filter components are shown in Figure 4. The network subtracts a signal proportional to the voltage input from the current input. This prevents crosstalk.

Doc ID 17105 Rev 1 7/26

Circuit description AN3157

2.2.5 Jumper settings

The on-board jumpers JP1 and JP2 allow the setting of the STPMS1 device according to

Ta bl e 2 and Tab le 3 below:

Table 2. Modes of operation

JP1 MS0 Description

1 1 Rogowsky mode, ampl = 32

2 NCLK ampl = 32 (reserved for future expansion)

3 0 Current transformer mode, ampl = 8

4 CLK shunt mode, ampl = 32, fclk = 8*mclk

Table 3. Changing of band-gap voltage reference

JP2 MS1 Description

1 1 TC = 190 ppm/°C

2 NCLK TC = 125 ppm/°C

3 0 TC = 100 ppm/°C

4 CLK TC = 170 ppm/°C

For further details on device configuration please refer to the device datasheet.

2.3 Clock management network

A 4.194 MHz quartz is used to supply the clock for the STPMC1 device. To set this frequency, internal configuration bits MDIV and FR1 must be kept cleared.

A synchronized clock is provided to all STPMS1 devices through the CLK pin, the frequency of which is programmable through bit HSA to 1.049 MHz or 2.097 MHz.

2.4 Communication with microprocessor

A control board with an embedded microprocessor may be connected to connector P1 using a 10-wire flat cable. Ta bl e 4 describes the pinout of the connector.

The STPMC1 has an SPI communication port implemented by four multi-purpose pins (SCS, SYN-NP, SDA-TD, SCL-NLC).

In stand-alone operating mode these multi-purpose pins produce:

● negative power direction on the SYN-NP pin

● tamper condition detected on the SDA-TD pin

● no load condition detected on the SCL-NLC pin

For this reason these pins are connected to the three LEDs D9, D10 and D11.

In this configuration, the LED pin produces a pulse train with a frequency proportional to the 3-phase power and is connected to LED D12.

8/26 Doc ID 17105 Rev 1