ST AN3142 Application note

AN3142

Application note

Solution for designing a 400 W fixed-off-time controlled PFC preregulator with the L6563S and L6563H

Introduction

In addition to the transition mode (TM) and fixed-frequency continuous conduction mode (FF-CCM) operation of PFC preregulators, a third approach is proposed that couples the simplicity and affordability of TM operation with the high-current capability of FF-CCM operation. This solution is a peak current-mode control with fixed-off-time (FOT). Design equations are given and a practical design for a 400 W board is illustrated and evaluated.

Two methods of controlling power factor corrector (PFC) preregulators based on boost topology are currently in use: the fixed-frequency (FF) PWM and the transition mode (TM) PWM (fixed on-time, variable frequency). The first method employs average current-mode control, a relatively complex technique requiring sophisticated controller ICs (e.g. the L4981A/B from STMicroelectronics) and a considerable component count. The second uses the simpler peak current-mode control, which is implemented with cheaper controller ICs (e.g. the L6561, L6562, L6562A and L6563S from STMicroelectronics), and far fewer external parts, therefore it is far less expensive. In the first method the boost inductor works in continuous conduction mode (CCM), while TM makes the inductor work on the boundary

between continuous and discontinuous mode, by definition. For a given power throughput, TM operation involves higher peak currents as compared to FF-CCM (Figure 1 and

Figure 2).

Figure 1. Line, inductor, switch and diode currents in FF-CCM PFC

Figure 2. Line, inductor, switch and diode currents in TM PFC

This demonstration, consistent with the above mentioned cost considerations, suggests the use of TM in a lower power range, while FF-CCM is recommended for higher power levels.

This criterion, though always true, is sometimes difficult to apply, especially for a midrange power level, around 150-300 W. The assessment of which approach gives the better cost/performance trade-off needs to be done on a case-by-case basis, considering the cost and the stress of not only power semiconductors and magnetic but also of the EMI filter. At the same power level, the switching frequency component to be filtered out in a TM system is twice the line current, whereas it is typically 1/3 or 1/4 in a CCM system.

February 2011

Doc ID 17005 Rev 3

1/44

www.st.com

Contents	AN3142

Contents

1	Introduction to FOT control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 4
2	Operation of an FOT-controlled PFC preregulator . . . . . . . . . . . . . . . . .		5
3	The circuit implementing the line-modulated fixed-off-time with the new
	L6563S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		6
4	Designing a fixed-off-time PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		9
	4.1	Input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	9
	4.2	Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	11
	4.3	Power section design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	13

4.3.1 Bridge rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.4 Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.5 Power MOSFET selection and power dissipation calculation . . . . . . . . 17 4.3.6 Boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.7 L6563S biasing circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5	L6563H: high voltage startup transition mode PFC . . . . . . . . . . . . . . .	34
6	Design example using the L6563S-FOT PFC Excel® spreadsheet . . .	38
7	Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	42
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	43

2/44	Doc ID 17005 Rev 3

AN3142	List of figures

List of figures

Figure 1.	Line, inductor, switch and diode currents in FF-CCM PFC. . . . . . . . . . . . . . . . . . . . . . . . .	. 1
Figure 2.	Line, inductor, switch and diode currents in TM PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 1
Figure 3.	Basic waveforms for fixed frequency PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 4
Figure 4.	Basic waveforms for fixed-off-time PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 4
Figure 5.	Block diagram of an FOT-controlled PFC pre-regulator . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 5
Figure 6.	Circuit implementing FOT control with the L6563S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 6
Figure 7.	ZCD pin signal with the fixed off-time generator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .	7
Figure 8.	Switching frequency fixing the line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16
Figure 9.	The effect of fixing off-time - boundary between DCM and CCM . . . . . . . . . . . . . . . . . . . .	16
Figure 10.	Conduction losses and total losses in the STP12NM50FP MOSFET couples for the 400W
FOT PFC	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
Figure 11.	L6563S internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
Figure 12.	Open-loop transfer function-bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 13.	Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
Figure 14.	Multiplier characteristics family for VFF =1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 15.	Multiplier characteristics family for VFF=3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	24
Figure 16. Mains detector and discharge resistor allow fast response to sudden line drops not depend-
ing on the external RC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		26
Figure 17.	Brownout function in L6563S and L6563H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
Figure 18.	Switching frequency function on the peak of the sinusoid input voltage waveform and the cor-
responding off-time value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		29
Figure 19.	Off-time vs. input mains voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 20.	Switching frequency vs. input mains voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	31
Figure 21.	L6563H and L6563S pin-out comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 22.	High-voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
Figure 23.	Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . .	35
Figure 24.	High-voltage startup behavior during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . . .	36
Figure 25.	High-voltage startup managing the DC-DC output short circuit . . . . . . . . . . . . . . . . . . . . .	37
Figure 26.	Excel spreadsheet design specification input table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 27.	Other design data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	38
Figure 28.	Excel spreadsheet FOT PFC using the L6563S (SO14-black pin out) schematic . . . . . . .	39
Figure 29.	Excel spreadsheet FOT PFC using the L6563H (SO16-red pin out) schematic. . . . . . . . .	39
Figure 30.	Excel spreadsheet BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	40
Figure 31.	L6563S 400W FOT PFC demonstration board (p/n EVL6563S-400W) . . . . . . . . . . . . . . .	41

Doc ID 17005 Rev 3

3/44

Introduction to FOT control	AN3142

1 Introduction to FOT control

In this area where the TM/CCM usability boundary is uncertain, a third approach that couples the simplicity and affordability of TM operation with the high-current capability of CCM operation may be a solution to the dilemma. Generally speaking, FF PWM is not the only alternative when CCM operation is desired. FF PWM modulates both switch ON and OFF times (their sum is constant by definition), and a given converter operates in either CCM or DCM depending on the input voltage and the loading conditions. Exactly the same

result can be achieved if the on-time only is modulated and the off-time is kept constant, in which case, however, the switching frequency is no longer fixed (Figure 3 and Figure 4).

This is referred to as “fixed-off-time” (FOT) control. Peak-current-mode control can still be used.

Figure 3. Basic waveforms for fixed	Figure 4. Basic waveforms for fixed-off-time
frequency PWM	PWM

An important factor is that FOT control does not need a specialized control IC. A simple modification of a standard TM PFC controller operation, requiring just a few additional passive parts and no significant extra cost, is all that is needed.

4/44	Doc ID 17005 Rev 3

AN3142	Operation of an FOT-controlled PFC preregulator

2 Operation of an FOT-controlled PFC preregulator

Figure 5 shows a block diagram of an FOT-controlled PFC preregulator. An error amplifier (VA) compares a portion of the preregulator's output voltage Vout with a reference VREF and generates an error signal VC proportional to their difference. VC, a DC voltage by hypothesis, is fed into an input of the multiplier block and multiplied by a portion of the rectified input voltage VMULT. At the output of the multiplier, there is a rectified sinusoid,

VCSREF, which has an amplitude proportional to that of VMULT and to VC, which represents the sinusoidal reference for PWM modulation. VCSREF is fed into the inverting input of a comparator that, on the non-inverting input, receives the voltage VCS on the sense resistor

Rsense, proportional to the current flowing through switch M (typically a MOSFET) and the L inductor during the on-time of M. When the two voltages are equal, the comparator resets the PWM latch and M, supposedly already ON, is switched OFF.

Figure 5. Block diagram of an FOT-controlled PFC pre-regulator

As a result, VCSREF determines the peak current through the M and the L inductor. As VCSREF is a rectified sinusoid, the inductor peak current is also enveloped by a rectified

sinusoid. The line current Iin is the average inductor current that is the low-frequency component of the inductor current resulting from the low-pass filtering operated by the EMI filter. The PWM latch output Q going high activates the timer that, after a predetermined time in which TOFF has elapsed, sets the PWM latch, therefore turning M on and starting another switching cycle. If TOFF is such that the inductor current does not fall to zero, the system operates in CCM. It is apparent that FOT control requires almost the same architecture as TM control, just the way the off-time of M is determined also changes. It is not a difficult task to modify externally the operation of the standard TM PFC controller so that the off-time of M is fixed. As a controller we refer to the L6563S [4], which is suitable for power applications of a few hundred watts because of its gate drive capability and its high noise immunity. For a more detailed and complex description of the fixed off-time technique and in particular the line modulated FOT, please refer to [5].

Doc ID 17005 Rev 3

5/44

The circuit implementing the line-modulated fixed-off-time with the new L6563S	AN3142

3The circuit implementing the line-modulated fixed- off-time with the new L6563S

The circuit that implements LM-FOT control with the L6563S is shown in Figure 6. During the on-time of the MOSFET the gate voltage VGD = 15 V is high, the D diode is forward

biased and the voltage at the ZCD pin is internally clamped at VZCDclamp 5.7 V. During the off-time of M VGD = 10 V is low, the D diode is reverse-biased and the voltage at the pin

decays with an exponential law until it reaches the triggering threshold (VZCDtrigger 0.7 V) that causes the switch to turn on. The time needed for the ZCD voltage to go from VZCDclamp to VZCDtrigger defines the duration of the off-time TOFF.

Figure 6. Circuit implementing FOT control with the L6563S

The circuit in Figure 6. makes TOFF a function of the RMS line voltage thanks to the peak holding effect of T1 (which acts as a buffer) along with R and C whose time constant is significantly longer than a line half-cycle. With the addition of R0 and T1, as long as the

voltage on the ZCD pin during TOFF is above Vmult+VBE, C is discharged through R and R0, following the law:

Equation 1

V′
	(t) = V
ZCD		ZCDclamp

− R R0 + R

( + )

Vmult VBE e

−	t (R+R0 )		R
	(RR0 ) C	+		(Vmult + VBE )
			R0 + R

As V’ZCD(t) falls below Vmult+VBE, T1 is cut off and C is discharged through R only, so that its evolution from that point on is described by:

Equation 2

			R	(V		) e−	t
	V′′	(t) =			+ V		R C
	ZCD		R0 + R	mult	BE

V'ZCD(t) decreases from VZCDclamp = 5.7 V to Vmult+VBE in the following time period t':

6/44	Doc ID 17005 Rev 3

AN3142

The circuit implementing the line-modulated fixed-off-time with the new L6563S

Equation 3

′

R R0

(Vmult + VBE ) R0

t

= −

C ln

R + R

0

V

(R + R

0

) − (V

+ V

) R

ZCDclamp

mult

BE

and V''ZCD(t) decreases from Vmult+VBE to VZCDtrigger = 0.7 V level in the following time period t'':

Equation 4

	V
t′′ = −RC ln	ZCDtrigger

Vmult + VBE

Figure 7 illustrates the signal on the ZCD pin with the two discharging time constants depending on the two resistors R, R0 and the L6563S parameters, particularly the upper clamp voltage and the triggering voltage of the ZCD pin.

Figure 7. ZCD pin signal with the fixed off-time generator circuit

The sum of the two time periods is the off-time function:

Equation 5

	R0
TOFF = −RC
R + R		0

(

+

VBE

)

R0

V

ln

Vmult

+ ln

ZCDtrigger

V

(R + R

0

)

−

(V

+ V

) R

(V

+ V

)

ZCDclamp

mult

BE

mult

BE

⎠

In this way, once the multiplier operating point (that is, the Vmult / VAC ratio) is fixed, with a proper selection of R and R0 it is possible to increase TOFF with the line voltage so that, at

maximum line voltage, it is always TON>TONmin = 450 ns for the L6563S [4]. This is a condition needed in order to avoid line distortion [5].

Doc ID 17005 Rev 3

7/44

The circuit implementing the line-modulated fixed-off-time with the new L6563S	AN3142

It is easy to see that TOFF is now a function of the instantaneous line voltage. We refer to this technique as “line-modulated fixed-off-time” (LM-FOT) [5].

This modification, though simple, introduces profound changes in the timing relationships, with a positive influence on the energetic relationships. From the control point of view, modulating TOFF is a feedforward term that modifies the gain but does not change its characteristics. Consequently, all of the properties of the standard FOT control are maintained. Due to the highly non-linear nature of the TOFF modulation introduced by T1 and R0, its effects are discussed only qualitatively and the quantitative aspects are provided graphically for a specific case in [5].

As a practical rule, it is convenient to first select a capacitor and then to calculate the resistor

needed to achieve the desired TOFF (see Section 4.3.7 on page 20).

As the gate voltage VGD goes high, the Rs resistor charges the timing capacitor C as quickly

as possible up to VZCDclamp, without exceeding clamp rating (IZCDx =10 mA). Then it must fulfill the following inequalities:

Equation 6

VGDx − VZCDclamp − VF				< Rs < R	VGD − VZCDclamp − VF
		VZCDclamp			V
IZCDx	+				ZCDclamp
		R

where VGD (assume VGD = 10 V) is the voltage delivered by the gate driver, VGDx = 15 V its maximum value, and VF the forward drop on D.

When working at high line/light load the on-time of the power switch becomes very short and

the Rs resistor alone is no longer able to charge C up to VZCDclamp. The speed-up capacitor Cs is then used in parallel to Rs. This capacitor causes an almost instantaneous charge of C

up to a level, after that Rs completes the charge up to VZCDclamp. It is important that the steep edge caused by Cs does not reach the clamp level, otherwise the internal clamp of the

L6563S undergoes uncontrolled current spikes (limited only by the dynamic resistance of the 1N4148 and the ESR of Cs) that could overstress the IC. Cs must then be:

Equation 7

	Cs < C		VZCDclamp
		VGDx	− VZCDclamp − VF

8/44	Doc ID 17005 Rev 3

AN3142	Designing a fixed-off-time PFC

4 Designing a fixed-off-time PFC

4.1Input specification

This first part is a detailed specification of the operating conditions of the circuit that is needed for the following calculations in Section 4.2 on page 11. In this example a 400 W,

wide input range mains PFC circuit has been considered. Some design criteria are also given.

● Mains voltage range (VAC rms):		VACmin = 90Vac VACmax = 265Vac	(1)
●	Minimum mains frequency:	fl = 47Hz	(2)
●	Rated output power (W):	Pout = 400W	(3)

Because the PFC is a boost topology, the regulated output voltage depends strongly on the maximum AC input voltage. In fact, for correct boost operation the output voltage must always be higher than the input and therefore, because Vin max is Vpk, the output has been set at 400 Vdc as the typical value. If the input voltage is higher, as typical in ballast applications, the output voltage must be set higher accordingly. As a rule of thumb the output voltage must be set 6/7% higher than the maximum input voltage peak.

● Regulated DC output voltage (Vdc) Vout = 400V

(4)

The target efficiency and PF are set here at minimum input voltage and maximum load. They are used for the following operating condition calculation of the PFC. Of course at high input voltage the efficiency is higher.

●	Expected efficiency (%):	η =	Pout	= 90%	(5)
			Pin
●	Expected power factor:	PF = 0.99			(6)

Because of the narrow loop voltage bandwidth, the PFC output can face overvoltages at startup or in case of load transients. To protect from excessive output voltage that can overstress the output components and the load, in the L6563S a device pin (PFC_OK, pin #6) has been dedicated to monitor the output voltage with a separate resistor divider, selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (Vovp), usually larger than the maximum Vout that can be expected, also including worst-case load/line transients.

● Maximum. output voltage (Vdc):

VOVP = 430V

(7)

Doc ID 17005 Rev 3

9/44

Designing a fixed-off-time PFC	AN3142

The mains frequency generates a 2fL voltage ripple on the output voltage at full load. The ripple amplitude determines the current flowing into the output capacitor and the ESR. Additionally, a certain holdup capability in case of mains dips can be requested from the PFC in which case the output capacitor must also be dimensioned, taking into account the required minimum voltage value (Vout min) after the elapsed holdup time (tHold).

●	Maximum output low frequency ripple: ∆Vout = 10V	(8)
●	Minimum output voltage after line drop (Vdc): Vout min = 300V	(9)
●	Holdup capability (ms): tHold = 20ms	(10)

The PFC minimum switching frequency is one of the main parameters used to dimension the boost inductor. Here we consider the switching frequency at low mains on the top of the sinusoid and at full load conditions. As a rule of thumb, it must be higher than the audio bandwidth in order to avoid audible noise and additionally it must not interfere with the L6563S minimum internal starter period, as given in the datasheet. On the other hand, if the minimum frequency is set too high the circuit shows excessive losses at higher input voltage and probably operates skipping switching cycles not only at light load. Typical minimum frequency range is 55-95 kHz for wide range operation.

● Minimum switching frequency (kHz) f	= 80kHz	(11)
sw min

Where fswmin = 1/(T+220 nsec) due to the ZCD - gate drive signal delay typical of the L6563S.

The design is to be done on the basis of a ripple factor (the ratio of the maximum current ripple amplitude to the inductor peak current at minimum line voltage) kr=0.34.

● Ripple factor

kr = 0.34

(12)

In order to properly select the power components of the PFC and dimension the heat sinks in case they are needed, the maximum operating ambient temperature around the PFC circuitry must be known. Please note that this is not the maximum external operating temperature of the entire equipment, but it is the local temperature at which the PFC components are working.

● Maximum ambient temperature (°C): T	= 50°C	(13)
ambx

10/44

Doc ID 17005 Rev 3

AN3142	Designing a fixed-off-time PFC

4.2Operating condition

The first step is to define the main parameters of the circuit, using the specification points given in Section 4.1 on page 9:

Rated DC output current:

Equation 8

Iout =	Pout	I	out	=	400W	= 1.00A
	Vout				400V

Maximum input power:

Equation 9

Pin = Pout Pin = 400W 100 = 444.44W η 90

Referring to the main currents shown in Figure 1, the following formula expresses the maximum value of current circulating in the boost cell which means at minimum line voltage of the selected range:

RMS input current:

Equation 10

	Iin =	Pout		I =	400W	= 4.99A
		VACmin	PF
					90Vac 0.99
				in

It is important to define the following ratios in order to continue describing the energetic relationships in the PFC:

Equation 11

kmin =	VACmin	kmin = 2	90Vac	= 0.32
	2		400V
	Vout

Equation 12

kmax =	VACmax	kmax = 2	265Vac	= 0.94
	2		400V
	Vout

From Equation 11 and Equation 12:

Line peak current:

Equation 13

IPK max =	2 Pin	I	=	2 444.44W	= 6.98A
		PK max		0.32 400V
	kmin Vout
Inductor Ripple-∆ILpk:

Doc ID 17005 Rev 3

11/44

Designing a fixed-off-time PFC										AN3142
Equation 14
∆ILpk	=		6 kr		IPK max	∆ILpk =	6	0.34	6.98A	= 2.04A
			−	3 kr			8 −	3 0.34
	8

Inductor peak current:

Equation 15

ILpk max	=		8	IPK max ILpk max	=	8		6.98A	= 8.01A
			− 3 kr			8 − 3	0.34
	8

It is also possible to calculate the RMS current flowing into the switch and into the diode, needed to calculate the losses of these two elements.

RMS switch current:

Equation 16

ISW = Pin				2 − 16 kmin		ISW	= 400W	2 − 16 0.32 = 4.22A
rms	kmin	Vout			3π	rms	0.32 400V		3π
RMS diode current:
Equation 17
IDrms =			Pin		16kmin	IDrms =	400W	16 0.32	= 2.57A
	kmin Vout				3π		0.32 400V	3π

It is worth remembering that the accuracy of the approximate energetic relationships described here is quite good at maximum load for low values of parameter k, that is, at low line voltage, but worsens at high line and as the power throughput is reduced. Since in the design phase current stress is calculated at maximum load and minimum line voltage, their accuracy is acceptable for design purposes.

12/44

Doc ID 17005 Rev 3

AN3142	Designing a fixed-off-time PFC

4.3Power section design

4.3.1Bridge rectifier

The input rectifier bridge can use standard slow recovery, low-cost devices.

Typically a 600 V device is selected in order to have good margin against mains surges. An NTC resistor limiting the current at turn-on is required to avoid overstress to the diode bridge.

The rectifier bridge power dissipation can be calculated using Equation 18, Equation 19, and Equation 20. The threshold voltage (Vth) and dynamic resistance (Rdiode) of a single

diode of the bridge can be found in the component datasheet.

Equation 18

I	= 2 Iin =	2 4.99A = 3.53A
inrms	2	2

Equation 19

I	= 2 Iin =	2 4.99A = 2.25A
in _ avg	π	π

The power dissipated on the bridge is:

Equation 20

Pbridge = 4 Rdiode I2inrms + 4 Vth Iin _ avg

Pbridge = 4 0.025Ω (3.53A)2 + 4 0.7V 2.25A = 7.53W

4.3.2Input capacitor

The input filter capacitor (Cin) is placed across the diode bridge output. This capacitor must smooth the high-frequency ripple and must sustain the maximum instantaneous input voltage. In a typical application an EMI filter is placed between the mains and the PFC circuit. In this application the EMI filter is reinforced by a differential mode Pi-filter after the bridge to reject the differential noise coming from the whole switching circuit. The design of the EMI filter (common mode and differential mode) is not described here. The value of the input filter capacitor can be calculated as follows, simply considering the output power that the PFC should deliver at full load:

Equation 21

C	in	= 2.5 10	−3 P	C	in	= 2.5 10−3	400W = 1µF
			out

The maximum value of this capacitor is limited to avoid line current distortion. The value chosen for this design is 1µF.

Doc ID 17005 Rev 3

13/44

Designing a fixed-off-time PFC	AN3142

4.3.3Output capacitor

The output bulk capacitor (Co) selection depends on the DC output voltage (4), the allowed maximum voltage (7), and the converter output power (3).

The 100/120 Hz (twice the mains frequency) voltage ripple (∆Vout = peak-to-peak ripple value) (8) is a function of the capacitor impedance and the peak capacitor current:

Equation 22

∆Vout = 2 Iout (2π 2f1l CO )2 + ESR2

With a low ESR capacitor the capacitive reactance is dominant, therefore:

Equation 23

	CO	≥	Iout		=	Pout	CO	≥	400W	= 338µF
			2π fl	∆Vout		2π fl Vout ∆Vout			2π 47Hz 400V 10V

Vout is usually selected in the range of 1.5% of the output voltage. Although ESR does not usually affect the output ripple, it should be taken into account for power loss calculations. The total RMS capacitor ripple current, including mains frequency and switching frequency components, is:

Equation 24

ICrms = ID2rms − Iout2

ICrms = (2.56A)2 − (1.0A)2 = 2.36A

If the PFC stage must guarantee a specified holdup time, the selection criterion of the capacitance changes. Co has to deliver the output power for a certain time (tHold) with a specified maximum dropout voltage (Vout min) that is the minimum output voltage value (which takes load regulation and output ripple into account). Vout min is the minimum output operating voltage before the 'power fail' detection and consequent stopping by the downstream system supplied by the PFC.

Equation 25

CO =		2 Pout	tHold	CO =	2 400W 20ms	= 242.3µF
	(V		)2 − V2
		− ∆V			(400V − 10V)2 − (300V)2
	out	out	out min

A 20% tolerance on the electrolytic capacitors must be taken into account for the right dimensioning.

Following the relationship (Equation 25), for this application a capacitor Co = 330 µF (450 V) has been selected in order to maintain a holdup capability for 22 ms. The actual output voltage ripple with this capacitor is also calculated. In detail:

14/44

Doc ID 17005 Rev 3